mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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124 lines
3.2 KiB
C++
124 lines
3.2 KiB
C++
/** Main Unit Test entry point.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <criterion/criterion.h>
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#include <criterion/options.h>
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#include <villas/utils.h>
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#include <villas/fpga/ip.h>
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#include <villas/fpga/card.h>
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#include <villas/fpga/vlnv.h>
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#include <villas/log.hpp>
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#include <villas/plugin.hpp>
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#include <villas/fpga/card.hpp>
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#include <spdlog/spdlog.h>
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#define FPGA_CARD "vc707"
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#define TEST_CONFIG "../etc/fpga.json"
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#define TEST_LEN 0x1000
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#define CPU_HZ 3392389000
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#define FPGA_AXI_HZ 125000000
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struct pci pci;
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struct vfio_container vc;
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villas::fpga::CardList fpgaCards;
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villas::fpga::PCIeCard* fpga;
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// keep to make it compile with old C tests
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struct fpga_card* card;
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static void init()
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{
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int ret;
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FILE *f;
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json_error_t err;
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villas::Plugin::dumpList();
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auto logger = loggerGetOrCreate("unittest");
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spdlog::set_pattern("[%T] [%l] [%n] %v");
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spdlog::set_level(spdlog::level::debug);
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ret = pci_init(&pci);
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cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system");
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ret = vfio_init(&vc);
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cr_assert_eq(ret, 0, "Failed to initiliaze VFIO sub-system");
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/* Parse FPGA configuration */
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f = fopen(TEST_CONFIG, "r");
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cr_assert_not_null(f, "Cannot open config file");
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json_t *json = json_loadf(f, 0, &err);
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cr_assert_not_null(json, "Cannot load JSON config");
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fclose(f);
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json_t *fpgas = json_object_get(json, "fpgas");
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cr_assert_not_null(fpgas, "No section 'fpgas' found in config");
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cr_assert(json_object_size(json) > 0, "No FPGAs defined in config");
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// get the FPGA card plugin
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villas::Plugin* plugin = villas::Plugin::lookup(villas::Plugin::Type::FpgaCard, "");
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cr_assert_not_null(plugin, "No plugin for FPGA card found");
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villas::fpga::PCIeCardFactory* fpgaCardPlugin = dynamic_cast<villas::fpga::PCIeCardFactory*>(plugin);
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// create all FPGA card instances using the corresponding plugin
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fpgaCards = fpgaCardPlugin->make(fpgas, &pci, &vc);
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if(fpgaCards.size() == 0) {
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logger->error("No FPGA cards found!");
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} else {
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fpga = fpgaCards.front().get();
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}
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cr_assert_not_null(fpga, "No FPGA card available");
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json_decref(json);
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}
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static void fini()
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{
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fpgaCards.clear();
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}
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TestSuite(fpga,
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.init = init,
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.fini = fini,
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.description = "VILLASfpga"
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);
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static void init_graph()
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{
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spdlog::set_pattern("[%T] [%l] [%n] %v");
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spdlog::set_level(spdlog::level::debug);
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}
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TestSuite(graph,
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.init = init_graph,
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.description = "Graph library"
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);
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