mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-16 00:00:02 +01:00
365 lines
8.5 KiB
C++
365 lines
8.5 KiB
C++
/** Communicate with VILLASfpga Xilinx FPGA boards
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2014-2020, Institute for Automation of Complex Power Systems, EONERC
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* @license GNU General Public License (version 3)
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*
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* VILLASnode
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <csignal>
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#include <iostream>
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#include <vector>
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#include <string>
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#include <algorithm>
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#include <jansson.h>
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#include <villas/nodes/villas_fpga.hpp>
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#include <villas/log.hpp>
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#include <villas/utils.h>
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#include <villas/utils.hpp>
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#include <villas/sample.h>
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#include <villas/plugin.h>
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#include <villas/super_node.hpp>
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#include <villas/fpga/ip.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/vlnv.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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/* Forward declartions */
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static struct plugin p;
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using namespace villas;
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using namespace villas::node;
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using namespace villas::utils;
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static struct pci pci;
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int villas_fpga_parse_config()
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{
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/* Parse FPGA configuration */
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FILE* f = fopen(configFile.c_str(), "r");
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if (f == nullptr) {
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logger->error("Cannot open config file: {}", configFile);
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}
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json_t* json = json_loadf(f, 0, nullptr);
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if (json == nullptr) {
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logger->error("Cannot parse JSON config");
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fclose(f);
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return -1;
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}
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fclose(f);
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json_t* fpgas = json_object_get(json, "fpgas");
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if (fpgas == nullptr) {
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logger->error("No section 'fpgas' found in config");
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exit(1);
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}
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return 0;
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}
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int villas_fpga_type_start(villas::node::SuperNode *sn)
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{
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int ret;
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ret = pci_init(&pci);
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if (ret) {
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logger->error("Cannot initialize PCI subsystem");
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return ret;
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}
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auto vfioContainer = villas::VfioContainer::create();
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ret = villas_fpga_parse_config();
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if (ret)
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return ret;
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// get the FPGA card plugin
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villas::Plugin* plugin = villas::Plugin::lookup(villas::Plugin::Type::FpgaCard, "");
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if (plugin == nullptr) {
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logger->error("No FPGA plugin found");
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exit(1);
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}
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villas::fpga::PCIeCardFactory* fpgaCardPlugin =
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dynamic_cast<villas::fpga::PCIeCardFactory*>(plugin);
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// create all FPGA card instances using the corresponding plugin
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auto cards = fpgaCardPlugin->make(fpgas, &pci, vfioContainer);
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return 0;
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}
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int villas_fpga_type_stop()
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{
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return 0;
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}
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int villas_fpga_init(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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return 0;
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}
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int villas_fpga_destroy(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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return 0;
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}
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int villas_fpga_parse(struct node *n, json_t *cfg)
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{
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int ret;
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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json_error_t err;
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const char *fpga_name;
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const char *dma_vlnv = "";
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const char *if_vlnv = "";
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ret = json_unpack_ex(cfg, &err, 0, "{ s: s, s?: s, s?: s }",
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"fpga", &s->setting1,
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"", &s->setting2
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);
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if (ret)
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jerror(&err, "Failed to parse configuration of node %s", node_name(n));
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return 0;
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}
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char * villas_fpga_print(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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return strf("fpga=%s, dma=%s, if=%s", f->fpga_name, f->dma_vlnv, f->);
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}
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int villas_fpga_check(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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if (s->setting1 > 100 || s->setting1 < 0)
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return -1;
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if (!s->setting2 || strlen(s->setting2) > 10)
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return -1;
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return 0;
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}
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int villas_fpga_prepare(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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for (auto& fpgaCard : cards) {
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if (fpgaCard->name == fpgaName) {
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f->card = fpgaCard;
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break;
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}
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}
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if (!card)
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logger->error("FPGA card {} not found in config or not working", fpgaName);
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// deallocate JSON config
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//json_decref(json);
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auto rtds = dynamic_cast<fpga::ip::Rtds*>
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(card->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")));
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//auto dma = dynamic_cast<fpga::ip::Dma*>
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// (card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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auto dma = dynamic_cast<fpga::ip::Dma*>
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(card->lookupIp("hier_0_axi_dma_axi_dma_1"));
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if (!rtds) {
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logger->error("No RTDS interface found on FPGA");
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return 1;
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}
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if (!dma) {
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logger->error("No DMA found on FPGA ");
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return 1;
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}
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rtds->dump();
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rtds->connect(rtds->getMasterPort(rtds->masterPort),
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dma->getSlavePort(dma->s2mmPort));
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dma->connect(dma->getMasterPort(dma->mm2sPort),
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rtds->getSlavePort(rtds->slavePort));
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auto &alloc = villas::HostRam::getAllocator();
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auto mem = alloc.allocate<int32_t>(0x100 / sizeof(int32_t));
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auto block = mem.getMemoryBlock();
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dma->makeAccesibleFromVA(block);
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// auto &mm = MemoryManager::get();
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// mm.getMemoryGraph().dump("graph.dot");
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return 0;
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}
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int villas_fpga_start(struct node *n)
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{
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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s->start_time = time_now();
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return 0;
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}
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int villas_fpga_stop(struct node *n)
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0;
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}
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int villas_fpga_pause(struct node *n)
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0;
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}
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int villas_fpga_resume(struct node *n)
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0;
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}
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int villas_fpga_read(struct node *n, struct sample *smps[], unsigned cnt, unsigned *release)
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{
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int read;
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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struct timespec now;
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dma->read(block, block.getSize());
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const size_t bytesRead = dma->readComplete();
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const size_t valuesRead = bytesRead / sizeof(int32_t);
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for (size_t i = 0; i < valuesRead; i++) {
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std::cerr << mem[i] << ";";
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}
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std::cerr << std::endl;
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return read;
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}
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int villas_fpga_write(struct node *n, struct sample *smps[], unsigned cnt, unsigned *release)
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{
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int written;
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struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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size_t memIdx = 0;
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for (unsigned i = 0; i < smps[0]->length; i++)
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f->tx_mem[memIdx++] = smps[0]->data[i].i;
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bool state = dma->write(block, memIdx * sizeof(int32_t));
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if (!state)
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logger->error("Failed to write to device");
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written = 0; /* The number of samples written */
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return written;
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}
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int villas_fpga_reverse(struct node *n)
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0;
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}
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int villas_fpga_poll_fds(struct node *n, int fds[])
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0; /* The number of file descriptors which have been set in fds */
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}
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int villas_fpga_netem_fds(struct node *n, int fds[])
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{
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//struct villas_fpga *f = (struct villas_fpga *) n->_vd;
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/* TODO: Add implementation here. */
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return 0; /* The number of file descriptors which have been set in fds */
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}
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__attribute__((constructor(110)))
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static void register_plugin() {
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if (plugins.state == State::DESTROYED)
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vlist_init(&plugins);
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p.name = "fpga";
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p.description = "Communicate with VILLASfpga Xilinx FPGA boards";
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p.type = PluginType::NODE;
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p.node.instances.state = State::DESTROYED;
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p.node.vectorize = 0;
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p.node.size = sizeof(struct villas_fpga);
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p.node.type.start = villas_fpga_type_start;
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p.node.type.stop = villas_fpga_type_stop;
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p.node.init = villas_fpga_init;
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p.node.destroy = villas_fpga_destroy;
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p.node.prepare = villas_fpga_prepare;
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p.node.parse = villas_fpga_parse;
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p.node.print = villas_fpga_print;
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p.node.check = villas_fpga_check;
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p.node.start = villas_fpga_start;
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p.node.stop = villas_fpga_stop;
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p.node.pause = villas_fpga_pause;
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p.node.resume = villas_fpga_resume;
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p.node.read = villas_fpga_read;
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p.node.write = villas_fpga_write;
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p.node.reverse = villas_fpga_reverse;
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p.node.poll_fds = villas_fpga_poll_fds;
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p.node.netem_fds = villas_fpga_netem_fds;
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vlist_init(&p.node.instances);
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vlist_push(&plugins, &p);
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}
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__attribute__((destructor(110)))
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static void deregister_plugin() {
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if (plugins.state != State::DESTROYED)
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vlist_remove_all(&plugins, &p);
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}
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