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besure that HermitCore enbales the cache

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This commit is contained in:
Stefan Lankes 2016-02-19 23:33:19 +01:00
parent 5200f73d92
commit ef01dd009d
2 changed files with 6 additions and 0 deletions
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3
hermit/arch/x86/include/asm/processor.h
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@ -196,8 +196,11 @@ extern "C" {
#define MSR_XAPIC_ENABLE (1UL << 11)
#define MSR_X2APIC_ENABLE (1UL << 10)
#define MSR_IA32_MISC_ENABLE 0x000001a0
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
#define MSR_IA32_PERF_STATUS 0x00000198
// MSR EFER bits
#define EFER_SCE (1 << 0)

3
hermit/arch/x86/kernel/processor.c
View file

@ -260,6 +260,7 @@ int cpu_detection(void) {
cr0 |= CR0_AM;
cr0 |= CR0_NE;
cr0 |= CR0_MP;
cr0 &= ~(CR0_CD|CR0_NW);
write_cr0(cr0);
cr4 = read_cr4();
@ -424,6 +425,8 @@ int cpu_detection(void) {
if (has_msr()) {
kprintf("IA32_MISC_ENABLE 0x%llx\n", rdmsr(MSR_IA32_MISC_ENABLE));
kprintf("IA32_FEATURE_CONTROL 0x%llx\n", rdmsr(MSR_IA32_FEATURE_CONTROL));
//kprintf("IA32_ENERGY_PERF_BIAS 0x%llx\n", rdmsr(MSR_IA32_ENERGY_PERF_BIAS));
//kprintf("IA32_PERF_STATUS 0x%llx\n", rdmsr(MSR_IA32_PERF_STATUS));
}
}