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220 lines
7 KiB
C
220 lines
7 KiB
C
/*
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* Copyright (c) 2014-2016, Stefan Lankes, Daniel Krebs, RWTH Aachen University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hermit/stdlib.h>
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#include <hermit/stdio.h>
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#include <hermit/errno.h>
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#include <hermit/string.h>
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#include <hermit/ctype.h>
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#include <hermit/vma.h>
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#include <hermit/logging.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/uart.h>
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#include <asm/irq.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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/*
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* This implementation based on following tutorial:
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* http://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming
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*/
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#define UART_RX 0 /* In: Receive buffer */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_TX 0 /* Out: Transmit buffer */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_LSR 5 /* Line Status Register */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Trigger RDI at FIFO level 1 byte */
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#define UART_FCR_TRIGGER_4 0x40 /* Trigger RDI at FIFO level 4 byte */
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#define UART_FCR_TRIGGER_8 0x80 /* Trigger RDI at FIFO level 8 byte */
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#define UART_FCR_TRIGGER_14 0xc0 /* Trigger RDI at FIFO level 14 byte*/
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
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#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
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#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
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#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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#define DEFAULT_UART_PORT 0xc110
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static size_t iobase = 0;
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static inline unsigned char read_from_uart(uint32_t off)
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{
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uint8_t c = 0;
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if (iobase)
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c = inportb(iobase + off);
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return c;
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}
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static inline void write_to_uart(uint32_t off, unsigned char c)
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{
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if (iobase)
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outportb(iobase + off, c);
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}
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/* Puts a single character on a serial device */
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int uart_putchar(unsigned char c)
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{
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if (!iobase)
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return 0;
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write_to_uart(UART_TX, c);
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return (int) c;
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}
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/* Uses the routine above to output a string... */
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int uart_puts(const char *text)
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{
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size_t i, len = strlen(text);
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if (!iobase)
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return 0;
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for (i = 0; i < len; i++)
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uart_putchar(text[i]);
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return len;
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}
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static int uart_config(void)
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{
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/*
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* enable FIFOs
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* clear RX and TX FIFO
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* set irq trigger to 8 bytes
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*/
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write_to_uart(UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1);
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/* disable interrupts */
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write_to_uart(UART_IER, 0);
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/* DTR + RTS */
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write_to_uart(UART_MCR, UART_MCR_DTR|UART_MCR_RTS);
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/*
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* 8bit word length
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* 1 stop bit
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* no partity
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* set DLAB=1
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*/
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char lcr = UART_LCR_WLEN8;
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write_to_uart(UART_LCR, lcr);
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lcr = read_from_uart(UART_LCR) | UART_LCR_DLAB;
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write_to_uart(UART_LCR, lcr);
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/*
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* set baudrate to 9600
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*/
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uint32_t divisor = 1843200 / 9600; //115200;
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write_to_uart(UART_DLL, divisor & 0xff);
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write_to_uart(UART_DLM, (divisor >> 8) & 0xff);
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/* set DLAB=0 */
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write_to_uart(UART_LCR, lcr & (~UART_LCR_DLAB));
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return 0;
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}
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extern const void kernel_start;
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int uart_init(void)
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{
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if (is_uhyve())
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return 0;
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pci_info_t pci_info;
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uint32_t bar = 0;
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// Searching for Intel's UART device
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if (pci_get_device_info(0x8086, 0x0936, &pci_info, 1) == 0)
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goto Lsuccess;
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// Searching for Qemu's UART device
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if (pci_get_device_info(0x1b36, 0x0002, &pci_info, 1) == 0)
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goto Lsuccess;
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// Searching for Qemu's 2x UART device (pci-serial-2x)
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if (pci_get_device_info(0x1b36, 0x0003, &pci_info, 1) == 0)
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goto Lsuccess;
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// Searching for Qemu's 4x UART device (pci-serial-4x)
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if (pci_get_device_info(0x1b36, 0x0004, &pci_info, 1) == 0)
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goto Lsuccess;
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// default value of our QEMU configuration
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iobase = DEFAULT_UART_PORT;
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// configure uart
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return uart_config();;
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Lsuccess:
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iobase = pci_info.base[bar];
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//irq_install_handler(32+pci_info.irq, uart_handler);
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kprintf("UART uses io address 0x%x\n", iobase);
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// configure uart
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return uart_config();
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}
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