Synced with comedi.
This commit is contained in:
Ian Abbott
parent
ebd3258a05
commit
df5e7fde3f
1 changed files with 524 additions and 511 deletions
207
include/comedi.h
207
include/comedi.h
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@ -21,7 +21,6 @@
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*/
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#ifndef _COMEDI_H
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#define _COMEDI_H
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@ -53,7 +52,6 @@ extern "C" {
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/* max length of device and driver names */
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#define COMEDI_NAMELEN 20
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typedef unsigned int lsampl_t;
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typedef unsigned short sampl_t;
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@ -202,8 +200,7 @@ typedef unsigned short sampl_t;
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/* subdevice types */
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enum comedi_subdevice_type
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{
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enum comedi_subdevice_type {
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COMEDI_SUBD_UNUSED, /* unused by driver */
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COMEDI_SUBD_AI, /* analog input */
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COMEDI_SUBD_AO, /* analog output */
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@ -220,8 +217,7 @@ enum comedi_subdevice_type
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/* configuration instructions */
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enum configuration_ids
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{
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enum configuration_ids {
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INSN_CONFIG_DIO_INPUT = 0,
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INSN_CONFIG_DIO_OUTPUT = 1,
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INSN_CONFIG_DIO_OPENDRAIN = 2,
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@ -236,8 +232,7 @@ enum configuration_ids
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INSN_CONFIG_FILTER = 24,
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INSN_CONFIG_CHANGE_NOTIFY = 25,
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/*ALPHA*/
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INSN_CONFIG_SERIAL_CLOCK = 26,
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/*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
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INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
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INSN_CONFIG_DIO_QUERY = 28,
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INSN_CONFIG_PWM_OUTPUT = 29,
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@ -262,8 +257,7 @@ enum configuration_ids
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INSN_CONFIG_GET_ROUTING = 4109,
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};
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enum comedi_io_direction
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{
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enum comedi_io_direction {
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COMEDI_INPUT = 0,
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COMEDI_OUTPUT = 1,
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COMEDI_OPENDRAIN = 2
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@ -289,7 +283,6 @@ enum comedi_io_direction
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#define COMEDI_BUFINFO _IOWR(CIO,14,comedi_bufinfo)
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#define COMEDI_POLL _IO(CIO,15)
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/* structures */
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typedef struct comedi_trig_struct comedi_trig;
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@ -480,8 +473,7 @@ struct comedi_bufinfo_struct{
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*/
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enum i8254_mode
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{
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enum i8254_mode {
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I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
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I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
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I8254_MODE2 = (2 << 1), /* Rate generator */
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@ -492,15 +484,12 @@ enum i8254_mode
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I8254_BINARY = 0
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};
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static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
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{
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static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) {
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if (pfi_channel < 10)
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return 0x1 + pfi_channel;
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else
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return 0xb + pfi_channel;
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}
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static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
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{
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} static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) {
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if (rtsi_channel < 7)
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return 0xb + rtsi_channel;
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else
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@ -510,8 +499,7 @@ static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
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#define NI_GPCT_COUNTING_MODE_SHIFT 16
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#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
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#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
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enum ni_gpct_mode_bits
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{
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enum ni_gpct_mode_bits {
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NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
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NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
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NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
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@ -535,23 +523,38 @@ enum ni_gpct_mode_bits
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NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
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NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
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NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_NORMAL_BITS = 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_NORMAL_BITS =
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0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
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0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
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0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
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0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
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0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
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0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
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NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
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0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
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0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
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0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
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0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
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NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
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NI_GPCT_COUNTING_DIRECTION_MASK = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_UP_BITS = 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_MASK =
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0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
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0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_UP_BITS =
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0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
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0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
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0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
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NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
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NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
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NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
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@ -562,8 +565,7 @@ enum ni_gpct_mode_bits
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/* Bits for setting a clock source with
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* INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
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enum ni_gpct_clock_source_bits
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{
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enum ni_gpct_clock_source_bits {
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NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
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NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
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NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
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@ -581,24 +583,20 @@ enum ni_gpct_clock_source_bits
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NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
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NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
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};
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static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) /* NI 660x-specific */
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{
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static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) { /* NI 660x-specific */
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return 0x10 + n;
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}
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static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
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{
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static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) {
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return 0x18 + n;
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}
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static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) /* no pfi on NI 660x */
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{
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static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) { /* no pfi on NI 660x */
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return 0x20 + n;
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}
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/* Possibilities for setting a gate source with
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INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
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May be bitwise-or'd with CR_EDGE or CR_INVERT. */
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enum ni_gpct_gate_select
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{
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enum ni_gpct_gate_select {
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/* m-series gates */
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NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
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NI_GPCT_AI_START2_GATE_SELECT = 0x12,
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@ -618,20 +616,16 @@ enum ni_gpct_gate_select
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we should add them here with an offset of 0x300 when known. */
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NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
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};
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static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
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{
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static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) {
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return 0x102 + n;
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}
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static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
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{
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static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) {
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return NI_USUAL_RTSI_SELECT(n);
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}
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static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
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{
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static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) {
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return NI_USUAL_PFI_SELECT(n);
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}
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static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
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{
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static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) {
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return 0x202 + n;
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}
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@ -642,22 +636,18 @@ enum ni_gpct_other_index {
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NI_GPCT_SOURCE_ENCODER_B,
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NI_GPCT_SOURCE_ENCODER_Z
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};
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enum ni_gpct_other_select
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{
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enum ni_gpct_other_select {
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/* m-series gates */
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// Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT
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NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
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};
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static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
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{
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static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) {
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return NI_USUAL_PFI_SELECT(n);
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}
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/* start sources for ni general-purpose counters for use with
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INSN_CONFIG_ARM */
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enum ni_gpct_arm_source
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{
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enum ni_gpct_arm_source {
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NI_GPCT_ARM_IMMEDIATE = 0x0,
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NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and the adjacent paired counter simultaneously */
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/* NI doesn't document bits for selecting hardware arm triggers. If
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@ -668,8 +658,7 @@ enum ni_gpct_arm_source
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};
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/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
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enum ni_gpct_filter_select
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{
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enum ni_gpct_filter_select {
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NI_GPCT_FILTER_OFF = 0x0,
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NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
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NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
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@ -680,8 +669,7 @@ enum ni_gpct_filter_select
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};
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/* PFI digital filtering options for ni m-series for use with INSN_CONFIG_FILTER. */
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enum ni_pfi_filter_select
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{
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enum ni_pfi_filter_select {
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NI_PFI_FILTER_OFF = 0x0,
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NI_PFI_FILTER_125ns = 0x1,
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NI_PFI_FILTER_6425ns = 0x2,
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@ -689,8 +677,7 @@ enum ni_pfi_filter_select
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};
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/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
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enum ni_mio_clock_source
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{
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enum ni_mio_clock_source {
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NI_MIO_INTERNAL_CLOCK = 0,
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NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() */
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/* the NI_MIO_PLL_* sources are m-series only */
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@ -698,16 +685,14 @@ enum ni_mio_clock_source
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NI_MIO_PLL_PXI10_CLOCK = 3,
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NI_MIO_PLL_RTSI0_CLOCK = 4
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};
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static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
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{
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static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) {
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return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
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}
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/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
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The numbers assigned are not arbitrary, they correspond to the bits required
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to program the board. */
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enum ni_rtsi_routing
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{
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enum ni_rtsi_routing {
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NI_RTSI_OUTPUT_ADR_START1 = 0,
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NI_RTSI_OUTPUT_ADR_START2 = 1,
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NI_RTSI_OUTPUT_SCLKG = 2,
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@ -719,8 +704,7 @@ enum ni_rtsi_routing
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NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
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NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock on line 7 */
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};
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static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
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{
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static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) {
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return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
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}
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@ -730,8 +714,7 @@ static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
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their routing cannot be changed. The numbers assigned are
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not arbitrary, they correspond to the bits required
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to program the board. */
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enum ni_pfi_routing
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{
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enum ni_pfi_routing {
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NI_PFI_OUTPUT_PFI_DEFAULT = 0,
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NI_PFI_OUTPUT_AI_START1 = 1,
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NI_PFI_OUTPUT_AI_START2 = 2,
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@ -757,8 +740,7 @@ enum ni_pfi_routing
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NI_PFI_OUTPUT_CDI_SAMPLE = 29,
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NI_PFI_OUTPUT_CDO_UPDATE = 30
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};
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static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
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{
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static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) {
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return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
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}
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@ -768,26 +750,22 @@ static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
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to program the board. Lines 0 to 7 can only be set to
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NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
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NI_660X_PFI_OUTPUT_COUNTER. */
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enum ni_660x_pfi_routing
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{
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enum ni_660x_pfi_routing {
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NI_660X_PFI_OUTPUT_COUNTER = 1, // counter
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NI_660X_PFI_OUTPUT_DIO = 2, // static digital output
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};
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/* NI External Trigger lines. These values are not arbitrary, but are related to
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the bits required to program the board (offset by 1 for historical reasons). */
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static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
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{
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static inline unsigned NI_EXT_PFI(unsigned pfi_channel) {
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return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
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}
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static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
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{
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static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) {
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return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
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}
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/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
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enum comedi_counter_status_flags
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{
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enum comedi_counter_status_flags {
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COMEDI_COUNTER_ARMED = 0x1,
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COMEDI_COUNTER_COUNTING = 0x2,
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COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
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@ -796,8 +774,7 @@ enum comedi_counter_status_flags
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/* Clock sources for CDIO subdevice on NI m-series boards.
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Used as the scan_begin_arg for a comedi_command. These
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sources may also be bitwise-or'd with CR_INVERT to change polarity. */
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enum ni_m_series_cdio_scan_begin_src
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{
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enum ni_m_series_cdio_scan_begin_src {
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NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
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NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
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NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
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@ -809,38 +786,74 @@ enum ni_m_series_cdio_scan_begin_src
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NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
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NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
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};
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||||
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
|
||||
{
|
||||
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
|
||||
return NI_USUAL_PFI_SELECT(pfi_channel);
|
||||
}
|
||||
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
|
||||
{
|
||||
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned
|
||||
rtsi_channel) {
|
||||
return NI_USUAL_RTSI_SELECT(rtsi_channel);
|
||||
}
|
||||
|
||||
/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command
|
||||
on NI boards. These scan begin sources can also be bitwise-or'd with
|
||||
CR_INVERT to change polarity. */
|
||||
static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
|
||||
{
|
||||
static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
|
||||
return NI_USUAL_PFI_SELECT(pfi_channel);
|
||||
}
|
||||
static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
|
||||
{
|
||||
static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) {
|
||||
return NI_USUAL_RTSI_SELECT(rtsi_channel);
|
||||
}
|
||||
|
||||
/* Bits for setting a clock source with
|
||||
* INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
|
||||
enum ni_freq_out_clock_source_bits
|
||||
{
|
||||
enum ni_freq_out_clock_source_bits {
|
||||
NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, // 10 MHz
|
||||
NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC // 100 KHz
|
||||
};
|
||||
|
||||
/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
|
||||
* 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
|
||||
enum amplc_dio_clock_source {
|
||||
AMPLC_DIO_CLK_CLKN, /* per channel external clock
|
||||
input/output pin (pin is only an
|
||||
input when clock source set to this
|
||||
value, otherwise it is an output) */
|
||||
AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */
|
||||
AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */
|
||||
AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */
|
||||
AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */
|
||||
AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
|
||||
AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
|
||||
(for channel 0, preceding counter
|
||||
channel is channel 2 on preceding
|
||||
counter subdevice, for first counter
|
||||
subdevice, preceding counter
|
||||
subdevice is the last counter
|
||||
subdevice) */
|
||||
AMPLC_DIO_CLK_EXT /* per chip external input pin */
|
||||
};
|
||||
|
||||
/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
|
||||
* 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
|
||||
enum amplc_dio_gate_source {
|
||||
AMPLC_DIO_GAT_VCC, /* internal high logic level */
|
||||
AMPLC_DIO_GAT_GND, /* internal low logic level */
|
||||
AMPLC_DIO_GAT_GATN, /* per channel external gate input */
|
||||
AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel
|
||||
minus 2 (for channels 0 or 1,
|
||||
channel minus 2 is channel 1 or 2 on
|
||||
the preceding counter subdevice, for
|
||||
the first counter subdevice the
|
||||
preceding counter subdevice is the
|
||||
last counter subdevice) */
|
||||
AMPLC_DIO_GAT_RESERVED4,
|
||||
AMPLC_DIO_GAT_RESERVED5,
|
||||
AMPLC_DIO_GAT_RESERVED6,
|
||||
AMPLC_DIO_GAT_RESERVED7
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _COMEDI_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue