fixed comment capitalization, style and indentions
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141e720356
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3 changed files with 57 additions and 47 deletions
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@ -32,19 +32,20 @@
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%include "config.inc"
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[BITS 32]
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; We use a special name to map this section at the begin of our kernel
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; => Multiboot needs its magic number at the begin of the kernel
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; => Multiboot expects its magic number at the beginning of the kernel.
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SECTION .mboot
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global start
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start:
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jmp stublet
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; This part MUST be 4byte aligned, so we solve that issue using 'ALIGN 4'
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; This part MUST be 4 byte aligned, so we solve that issue using 'ALIGN 4'.
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ALIGN 4
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mboot:
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; Multiboot macros to make a few lines more readable later
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MULTIBOOT_PAGE_ALIGN equ 1<<0
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MULTIBOOT_MEMORY_INFO equ 1<<1
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MULTIBOOT_PAGE_ALIGN equ (1 << 0)
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MULTIBOOT_MEMORY_INFO equ (1 << 1)
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MULTIBOOT_HEADER_MAGIC equ 0x1BADB002
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MULTIBOOT_HEADER_FLAGS equ MULTIBOOT_PAGE_ALIGN | MULTIBOOT_MEMORY_INFO
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MULTIBOOT_CHECKSUM equ -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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@ -57,37 +58,44 @@ mboot:
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SECTION .text
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ALIGN 4
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stublet:
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; initialize stack pointer
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; Initialize stack pointer
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mov esp, boot_stack
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add esp, KERNEL_STACK_SIZE-16
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; initialize cpu features
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; Initialize CPU features
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call cpu_init
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; interpret multiboot information
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; Interpret multiboot information
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extern multiboot_init
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push ebx
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call multiboot_init
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add esp, 4
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; jump to the boot processors's C code
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; Jump to the boot processors's C code
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extern main
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call main
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jmp $
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; This will set up the x86 control registers:
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; Caching and the floating point unit are enabled
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global cpu_init
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cpu_init:
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mov eax, cr0
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; enable caching, disable paging and fpu emulation
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and eax, 0x1ffffffb
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; ...and turn on FPU exceptions
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or eax, 0x22
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mov cr0, eax
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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; Set CR4
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mov cr4, eax
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and eax, ~(1 << 9) ; disable SSE
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or eax, (1 << 4) ; enable PSE
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mov cr4, eax
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; Set CR0
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mov eax, cr0
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and eax, ~(1 << 2) ; disable FPU emulation
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and eax, ~(1 << 30) ; enable caching
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or eax, (1 << 31) ; enable paging
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or eax, (1 << 5) ; enable FPU exceptions
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mov cr0, eax
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ret
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; This will set up our new segment registers. We need to do
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@ -108,12 +116,12 @@ gdt_flush:
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flush2:
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ret
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; The first 32 interrupt service routines (isr) entries correspond to exceptions.
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; Some exceptions will push an error code onto the stack which is specific to
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; The first 32 interrupt service routines (ISR) entries correspond to exceptions.
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; Some exceptions will push an error code onto the stack which is specific to
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; the exception caused. To decrease the complexity, we handle this by pushing a
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; dummy error code of 0 onto the stack for any ISR that doesn't push an error
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; code already.
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;
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; Dummy error code of 0 onto the stack for any ISR that doesn't push an error
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; code already.
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;
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; ISRs are registered as "Interrupt Gate".
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; Therefore, the interrupt flag (IF) is already cleared.
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@ -136,8 +144,8 @@ flush2:
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jmp common_stub
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%endmacro
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; create isr entries, where the number after the
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; pseudo error code represents following interrupts
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; Create isr entries, where the number after the
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; pseudo error code represents following interrupts:
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; 0: Divide By Zero Exception
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; 1: Debug Exception
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; 2: Non Maskable Interrupt Exception
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@ -189,18 +197,16 @@ isrstub_pseudo_error 9
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jmp common_stub
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%endmacro
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; create entries for the interrupts 0 to 23
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; Create entries for the interrupts 0 to 23
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%assign i 0
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%rep 24
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irqstub i
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%assign i i+1
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%endrep
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extern syscall_handler
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; Used to realize system calls.
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; By entering the handler, the interrupt flag is not cleared.
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global isrsyscall
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; used to realize system calls
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; by entering the handler, the interrupt flag is not cleared
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isrsyscall:
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cli
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push es
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@ -213,13 +219,14 @@ isrsyscall:
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push ebx
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push eax
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; set kernel data segmenets
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; Set kernel data segmenets
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mov ax, 0x10
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mov ds, ax
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mov es, ax
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mov eax, [esp]
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sti
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extern syscall_handler
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call syscall_handler
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cli
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@ -241,12 +248,12 @@ extern irq_handler
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extern get_current_stack
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extern finish_task_switch
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; Create a pseudo interrupt on top of the stack.
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; Afterwards, we switch to the task with iret.
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; We already are in kernel space => no pushing of SS required.
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global switch_context
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ALIGN 4
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switch_context:
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; create on the stack a pseudo interrupt
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; afterwards, we switch to the task with iret
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; we already in kernel space => no pushing of SS required
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mov eax, [esp+4] ; on the stack is already the address to store the old esp
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pushf ; push controll register
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push DWORD 0x8 ; CS
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@ -263,8 +270,6 @@ ALIGN 4
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rollback:
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ret
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extern set_kernel_stack
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ALIGN 4
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common_stub:
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pusha
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@ -274,8 +279,10 @@ common_stub:
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mov es, ax
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mov ds, ax
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; use the same handler for interrupts and exceptions
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; Use the same handler for interrupts and exceptions
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push esp
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extern set_kernel_stack
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call irq_handler
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add esp, 4
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@ -287,15 +294,15 @@ common_switch:
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call get_current_stack ; get new esp
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xchg eax, esp
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; set task switched flag
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; Set task switched flag
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mov eax, cr0
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or eax, 8
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mov cr0, eax
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; set esp0 in the task state segment
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; Set esp0 in the task state segment
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call set_kernel_stack
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; call cleanup code
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; Call cleanup code
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call finish_task_switch
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no_context_switch:
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@ -305,9 +312,12 @@ no_context_switch:
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add esp, 8
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iret
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SECTION .data
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global boot_stack
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ALIGN 4096
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boot_stack:
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TIMES (KERNEL_STACK_SIZE) DB 0xcd
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TIMES (KERNEL_STACK_SIZE) DB 0xcd
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; add some hints to the ELF file
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SECTION .note.GNU-stack noalloc noexec nowrite progbits
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@ -34,15 +34,15 @@ extern "C" {
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#define EDUOS_VERSION "0.1"
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#define MAX_TASKS 16
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#define TIMER_FREQ 100 /* in HZ */
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#define CLOCK_TICK_RATE 1193182 /* 8254 chip's internal oscillator frequency */
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#define VIDEO_MEM_ADDR 0xB8000 // the video memora address
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#define TIMER_FREQ 100 /* in HZ */
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#define CLOCK_TICK_RATE 1193182 /* 8254 chip's internal oscillator frequency */
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#define VIDEO_MEM_ADDR 0xB8000 /* the video memory address */
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#define CACHE_LINE 64
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#define KERNEL_STACK_SIZE (8*1024)
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#define KERNEL_STACK_SIZE (8<<10) /* 8 KiB */
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#define BITMAP_SIZE (128<<5) /* for 128 MiB of RAM */
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#define INT_SYSCALL 0x80
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#define BYTE_ORDER LITTLE_ENDIAN
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#define BYTE_ORDER LITTLE_ENDIAN
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#define CONFIG_VGA
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@ -179,14 +179,14 @@ int memory_init(void)
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}
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else if (mb_info->flags & MULTIBOOT_INFO_MEM) {
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size_t page;
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size_t pages_lower = mb_info->mem_lower >> 2;
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size_t pages_lower = mb_info->mem_lower >> 2; /* KiB to page number */
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size_t pages_upper = mb_info->mem_upper >> 2;
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for (page=0; page<pages_lower; page++)
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page_clear_mark(page);
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for (page=0; page<pages_upper; page++)
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page_clear_mark(page + (1<<8)); /* 1 MiB offset */
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page_clear_mark(page + 256); /* 1 MiB == 256 pages offset */
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atomic_int32_add(&total_pages, pages_lower + pages_upper);
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atomic_int32_add(&total_available_pages, pages_lower + pages_upper);
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