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added functions to handle TLB invalidation and control register access

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This commit is contained in:
Steffen Vogel 2014-08-21 20:14:59 +02:00
parent e514ae24f8
commit 9b4714113a
1 changed files with 24 additions and 1 deletions
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25
arch/x86/include/asm/processor.h
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@ -66,6 +66,22 @@ static inline size_t read_cr3(void) {
return val;
}
/** @brief Read cr2 register
* @return cr2's value
*/
static inline size_t read_cr2(void) {
size_t val;
asm volatile("mov %%cr2, %0" : "=r"(val));
return val;
}
/** @brief Write a value into cr2 register
* @param val The value you want to write into cr2
*/
static inline void write_cr2(size_t val) {
asm volatile("mov %0, %%cr2" : : "r"(val));
}
/** @brief Write a value into cr3 register
* @param val The value you want to write into cr3
*/
@ -73,7 +89,6 @@ static inline void write_cr3(size_t val) {
asm volatile("mov %0, %%cr3" : : "r"(val));
}
/** @brief Flush cache
*
* The wbinvd asm instruction which stands for "Write back and invalidate"
@ -95,6 +110,14 @@ static inline void flush_tlb(void)
write_cr3(val);
}
/** @brief Flush a specific page entry in TLB
* @param addr The (virtual) address of the page to flush
*/
static inline void tlb_flush_one_page(size_t addr)
{
asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
}
/** @brief Invalidate cache
*
* The invd asm instruction which invalidates cache without writing back