added functions to handle TLB invalidation and control register access
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1 changed files with 24 additions and 1 deletions
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@ -66,6 +66,22 @@ static inline size_t read_cr3(void) {
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return val;
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}
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/** @brief Read cr2 register
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* @return cr2's value
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*/
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static inline size_t read_cr2(void) {
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size_t val;
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asm volatile("mov %%cr2, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr2 register
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* @param val The value you want to write into cr2
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*/
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static inline void write_cr2(size_t val) {
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asm volatile("mov %0, %%cr2" : : "r"(val));
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}
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/** @brief Write a value into cr3 register
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* @param val The value you want to write into cr3
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*/
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@ -73,7 +89,6 @@ static inline void write_cr3(size_t val) {
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asm volatile("mov %0, %%cr3" : : "r"(val));
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}
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/** @brief Flush cache
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*
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* The wbinvd asm instruction which stands for "Write back and invalidate"
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@ -95,6 +110,14 @@ static inline void flush_tlb(void)
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write_cr3(val);
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}
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/** @brief Flush a specific page entry in TLB
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* @param addr The (virtual) address of the page to flush
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*/
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static inline void tlb_flush_one_page(size_t addr)
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{
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asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
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}
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/** @brief Invalidate cache
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*
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* The invd asm instruction which invalidates cache without writing back
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