393 lines
14 KiB
C
393 lines
14 KiB
C
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xdevcfg_hw.h
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*
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* This file contains the hardware interface to the Device Config Interface.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- ---------------------------------------------
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* 1.00a hvm 02/07/11 First release
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* 2.01a nm 08/01/12 Added defines for the PS Version bits,
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* removed the FIFO Flush bits from the
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* Miscellaneous Control Reg
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* 2.03a nm 04/19/13 Fixed CR# 703728.
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* Updated the register definitions as per the latest TRM
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* version UG585 (v1.4) November 16, 2012.
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* 2.04a kpc 10/07/13 Added function prototype.
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* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
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* </pre>
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*
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******************************************************************************/
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#ifndef XDCFG_HW_H /* prevent circular inclusions */
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#define XDCFG_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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* Offsets of registers from the start of the device
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* @{
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*/
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#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
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#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
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#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
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#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
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#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
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#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
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#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
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#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
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#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
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#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
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#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
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#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
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#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
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#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
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#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
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/* @} */
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/** @name Control Register Bit definitions
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* @{
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*/
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#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
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* Secure Reset
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*/
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#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
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* Reset FPGA
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*/
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#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
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#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
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#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
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#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
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* to FPGA every 4 PCAP
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* cycles
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*/
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#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
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#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
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#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
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#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
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#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
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#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
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#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
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* Status mask
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*/
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#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
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* Debug Enable
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*/
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#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
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* Debug Enable
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*/
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#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
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* Enable
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*/
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#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
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* Enable
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*/
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#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
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/* @} */
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/** @name Lock register bit definitions
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* @{
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*/
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#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
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#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
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#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
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#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
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* USER_MODE
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*/
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#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
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* security config
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* including: DAP_En,
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* DBGEN,,
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* NIDEN, SPNIEN
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*/
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/*@}*/
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/** @name Config Register Bit definitions
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* @{
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*/
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#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
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* Threshold Mask
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*/
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#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
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* Mask
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*/
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#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
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* clock edge
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*/
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#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
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* clock edge
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*/
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#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
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* increment mask
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*/
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#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
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* address increment
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* mask
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*/
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/* @} */
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/** @name Interrupt Status/Mask Register Bit definitions
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* @{
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*/
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#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
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* HIZ
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*/
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#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
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* done
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*/
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#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
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#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
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* configuration
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*/
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#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
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* reset
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*/
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#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
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* or Data or response
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* timeout
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*/
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#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
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* error
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*/
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#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
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* response timeout
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*/
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#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
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* error
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*/
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#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
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#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
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* threshold */
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#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
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* threshold */
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#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
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#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
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* overflow
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*/
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#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
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#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
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* transfers Done
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*/
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#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
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* length error
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*/
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#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
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#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
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#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
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#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
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#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
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#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
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* of Init Signal
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*/
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#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
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* of Init Signal
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*/
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#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
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XDCFG_IXR_AXI_WERR_MASK | \
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XDCFG_IXR_AXI_RTO_MASK | \
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XDCFG_IXR_AXI_RERR_MASK | \
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XDCFG_IXR_RX_FIFO_OV_MASK | \
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XDCFG_IXR_DMA_CMD_ERR_MASK |\
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XDCFG_IXR_DMA_Q_OV_MASK | \
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XDCFG_IXR_P2D_LEN_ERR_MASK |\
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XDCFG_IXR_PCFG_HMAC_ERR_MASK)
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#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
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/* @} */
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/** @name Status Register Bit definitions
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* @{
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*/
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#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
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* Queue full
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*/
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#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
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* Queue empty
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*/
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#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
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* completed DMA
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* transfers
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*/
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#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
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#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
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#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
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* during HIZ
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*/
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#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
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* done
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*/
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#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
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#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
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* config
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*/
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#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
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* POR Status
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*/
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#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
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* access
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*/
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#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
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* reset status
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*/
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#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
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* Status
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*/
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#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
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/**< BBRAM key
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* disable
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*/
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#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
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* Enable Status
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*/
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#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
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* Disable
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* status
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*/
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/* @} */
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/** @name DMA Source/Destination Transfer Length Register Bit definitions
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* @{
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*/
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#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
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/*@}*/
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/** @name Miscellaneous Control Register Bit definitions
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* @{
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*/
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#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
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#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
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#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
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/* @} */
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/** @name FIFO Threshold Bit definitions
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* @{
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*/
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#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
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#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
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#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
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#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
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/* @}*/
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/* Miscellaneous constant values */
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#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
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#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
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#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
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* address
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*/
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#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
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|
/**************************** Type Definitions *******************************/
|
||
|
|
|
||
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Read the given register.
|
||
|
|
*
|
||
|
|
* @param BaseAddr is the base address of the device
|
||
|
|
* @param RegOffset is the register offset to be read
|
||
|
|
*
|
||
|
|
* @return The 32-bit value of the register
|
||
|
|
*
|
||
|
|
* @note C-style signature:
|
||
|
|
* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XDcfg_ReadReg(BaseAddr, RegOffset) \
|
||
|
|
Xil_In32((BaseAddr) + (RegOffset))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Write to the given register.
|
||
|
|
*
|
||
|
|
* @param BaseAddr is the base address of the device
|
||
|
|
* @param RegOffset is the register offset to be written
|
||
|
|
* @param Data is the 32-bit value to write to the register
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note C-style signature:
|
||
|
|
* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
|
||
|
|
Xil_Out32((BaseAddr) + (RegOffset), (Data))
|
||
|
|
|
||
|
|
/************************** Function Prototypes ******************************/
|
||
|
|
/*
|
||
|
|
* Perform reset operation to the devcfg interface
|
||
|
|
*/
|
||
|
|
void XDcfg_ResetHw(u32 BaseAddr);
|
||
|
|
/************************** Variable Definitions *****************************/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* end of protection macro */
|