604 lines
20 KiB
C
604 lines
20 KiB
C
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/******************************************************************************
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*
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* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic_slave.c
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*
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* Contains slave functions for the XIic component. This file is necessary when
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* slave operations, sending and receiving data as a slave on the IIC bus,
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* are desired.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- ------- -----------------------------------------------
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* 1.01b jhl 3/26/02 repartioned the driver
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* 1.01c ecm 12/05/02 new rev
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* 1.13a wgr 03/22/07 Converted to new coding style.
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* 1.15a ktn 03/18/09 Minor changes to comply to Doxygen
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* 2.00a ktn 10/22/09 Converted all register accesses to 32 bit access.
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* Updated to use the HAL APIs/macros.
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* Removed the macro XIic_mEnterCriticalRegion and used
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* XIic_IntrGlobalDisable int its place.
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* Removed the macro XIic_mExitCriticalRegion and used
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* XIic_IntrGlobalEnable in its place.
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* Some of the macros have been renamed to remove _m from
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* the name and some of the macros have been renamed to be
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* consistent, see the xiic_i.h and xiic_l.h files for further
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* information
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* 2.03a rkv 01/25/11 Updated in NAAS interrupt handler to support data
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* recieved less than FIFO size prior to NAAS interrupt.
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* Fixed for CR590212.
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* 2.04a sdm 07/22/11 Added IsSlaveSetAckOff flag to the instance structure.
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* The IsSlaveSetAckOff is set when the Slave has set the
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* Ack Off in the RecvSlaveData function and is cleared in the
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* NotAddrAsSlaveHandler when the master has released the
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* bus. This flag is to be used by slave applications for
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* recovering when it has gone out of sync with the master.
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* CR 615004.
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* </pre>
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*
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****************************************************************************/
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/***************************** Include Files *******************************/
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#include "xiic.h"
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#include "xiic_i.h"
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/************************** Constant Definitions ***************************/
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/**************************** Type Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *******************/
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/************************** Function Prototypes ****************************/
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static void AddrAsSlaveHandler(XIic *InstancePtr);
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static void NotAddrAsSlaveHandler(XIic *InstancePtr);
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static void RecvSlaveData(XIic *InstancePtr);
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static void SendSlaveData(XIic *InstancePtr);
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/************************** Variable Definitions **************************/
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/*****************************************************************************/
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/**
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*
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* This function includes slave code such that slave events will be processsed.
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* It is necessary to allow slave code to be optional to reduce the size of
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* the driver. This function may be called at any time but must be prior to
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* being selected as a slave on the IIC bus. This function may be called prior
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* to the Cfg_Initialize() function and must be called before any functions in
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* this file are called.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XIic_SlaveInclude()
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{
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XIic_AddrAsSlaveFuncPtr = AddrAsSlaveHandler;
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XIic_NotAddrAsSlaveFuncPtr = NotAddrAsSlaveHandler;
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XIic_RecvSlaveFuncPtr = RecvSlaveData;
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XIic_SendSlaveFuncPtr = SendSlaveData;
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}
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/*****************************************************************************/
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/**
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*
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* This function sends data as a slave on the IIC bus and should not be called
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* until an event has occurred that indicates the device has been selected by
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* a master attempting read from the slave (XII_MASTER_READ_EVENT).
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*
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* @param InstancePtr is a pointer to the XIic instance to be worked on.
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* @param TxMsgPtr is a pointer to the data to be transmitted.
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* @param ByteCount is the number of message bytes to be sent.
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*
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* @return
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* - XST_SUCCESS indicates the message transmission has been
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* initiated.
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* - XST_IIC_NOT_SLAVE indicates the device has not been
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* selected to be a slave on the IIC bus such that data
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* cannot be sent.
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*
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* @note None.
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*
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******************************************************************************/
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int XIic_SlaveSend(XIic *InstancePtr, u8 *TxMsgPtr, int ByteCount)
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{
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u32 IntrStatus;
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u32 Status;
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/*
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* If the device is not a slave on the IIC bus then indicate an error
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* because data cannot be sent on the bus.
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*/
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Status = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_SR_REG_OFFSET);
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if ((Status & XIIC_SR_ADDR_AS_SLAVE_MASK) == 0) {
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return XST_IIC_NOT_SLAVE;
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}
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XIic_IntrGlobalDisable(InstancePtr->BaseAddress);
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/*
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* Save message state and invalidate the receive buffer pointer to
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* indicate the direction of transfer is sending.
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*/
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InstancePtr->SendByteCount = ByteCount;
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InstancePtr->SendBufferPtr = TxMsgPtr;
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InstancePtr->RecvBufferPtr = NULL;
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/*
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* Start sending the specified data and then interrupt processing will
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* complete it.
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*/
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XIic_TransmitFifoFill(InstancePtr, XIIC_SLAVE_ROLE);
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/* Clear any pending Tx empty, Tx Error and interrupt then enable them.
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* The Tx error interrupt indicates when the message is complete.
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* If data remaining to be sent, clear and enable Tx <EFBFBD> empty interrupt.
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*/
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IntrStatus = (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK);
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if (InstancePtr->SendByteCount > 1) {
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IntrStatus |= XIIC_INTR_TX_HALF_MASK;
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}
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/*
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* Clear the interrupts in the status and then enable them and then
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* exit the critical region.
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*/
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XIic_ClearEnableIntr(InstancePtr->BaseAddress, IntrStatus);
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XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function sends data as a slave on the IIC bus and should not be called
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* until an event has occurred that indicates the device has been selected by
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* a master attempting read from the slave (XII_MASTER_READ_EVENT).
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*
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* If more data is received than specified a No Acknowledge will be sent to
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* signal the Master to stop sending data. Any received data is read to prevent
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* the slave device from throttling the bus.
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*
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* @param InstancePtr is a pointer to the Iic instance to be worked on.
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* @param RxMsgPtr is a pointer to the data to be transmitted.
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* @param ByteCount is the number of message bytes to be sent.
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*
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* @return
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* - XST_SUCCESS indicates the message transmission has been
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* initiated.
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* - XST_IIC_NOT_SLAVE indicates the device has not been selected
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* to be a slave on the IIC bus such that data cannot be received.
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*
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* @internal
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*
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* The master signals the message completion differently depending on the
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* repeated start options.
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*
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* When the master is not using repeated start:
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* - Not Adressed As Slave NAAS interrupt signals the master has sent a stop
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* condition and is no longer sending data. This doesn't imply that the master
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* will not send a No Ack. It covers when the master fails to send No
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* Ackowledge before releasing the bus.
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* - Tx Error interrupt signals end of message.
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*
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* When the master is using repeated start:
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* - the Tx Error interrupt signals the master finished sending the msg.
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* - NAAS interrupt will not signal when message is complete as the
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* master may want to write or read another message with this device.
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*
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* To prevent throttling, the slave must contine to read discard the data
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* when the receive buffer is full. When unexpected bytes are received, No Ack
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* must be set and the Rx buffer continually read until either NAAS
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* or Bus Not Busy BND interrupt signals the master is no longer
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* interacting with this slave. At this point the Ack is set to ON allowing
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* this device to acknowlefge the an address sent to it for the next
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* slave message.
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*
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* The slave will always receive 1 byte before the bus is throttled causing a
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* receive pending interrupt before this routine is executed. After one byte
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* the bus will throttle. The depth is set to the proper amount immediatelly
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* allowing the master to send more bytes and then to again throttle, but at the
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* proper fifo depth. The interrupt is a level. Clearing and enabling will cause
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* the Rx interrupt to pend at the correct level.
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*
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******************************************************************************/
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int XIic_SlaveRecv(XIic *InstancePtr, u8 *RxMsgPtr, int ByteCount)
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{
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u32 Status;
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/*
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* If the device is not a slave on the IIC bus then indicate an error
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* because data cannot be received on the bus.
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*/
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Status = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_SR_REG_OFFSET);
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if ((Status & XIIC_SR_ADDR_AS_SLAVE_MASK) == 0) {
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return XST_IIC_NOT_SLAVE;
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}
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XIic_IntrGlobalDisable(InstancePtr->BaseAddress);
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/*
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* Save message state and invalidate the send buffer pointer to indicate
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* the direction of transfer is receive.
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*/
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InstancePtr->RecvByteCount = ByteCount;
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InstancePtr->RecvBufferPtr = RxMsgPtr;
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InstancePtr->SendBufferPtr = NULL;
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/*
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* Set receive FIFO occupancy depth so the Rx interrupt will occur
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* when all bytes received or if more bytes than will fit in FIFO,
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* set to max depth.
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*/
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if (ByteCount > IIC_RX_FIFO_DEPTH) {
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET,
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IIC_RX_FIFO_DEPTH - 1);
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} else {
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET,
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ByteCount - 1);
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}
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/*
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* Clear and enable receive full interrupt except when the bytes to
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* receive is only 1, don't clear interrupt as it is the only one your
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* going to get.
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*/
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if (ByteCount > 1) {
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XIic_ClearIntr(InstancePtr->BaseAddress,
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XIIC_INTR_RX_FULL_MASK);
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}
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XIic_EnableIntr(InstancePtr->BaseAddress, XIIC_INTR_RX_FULL_MASK);
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XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function is called when the IIC device is Addressed As a Slave (AAS).
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* This occurs when another device on the bus, a master, has addressed this
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* device to receive a message.
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*
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* @param InstancePtr is a pointer to the XIic instance to be worked on.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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static void AddrAsSlaveHandler(XIic *InstancePtr)
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{
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u32 Status;
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int CallValue;
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/*
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* Disable AAS interrupt to clear the interrupt condition since this is
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* interrupt does not go away and enable the not addressed as a slave
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* interrrupt to tell when the master stops data transfer.
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*/
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XIic_DisableIntr(InstancePtr->BaseAddress, XIIC_INTR_AAS_MASK);
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XIic_ClearEnableIntr(InstancePtr->BaseAddress, XIIC_INTR_NAAS_MASK);
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/*
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* Determine how the slave is being addressed and call the handler to
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* notify the user of the event.
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*/
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Status = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_SR_REG_OFFSET);
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/*
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* Determine if the master is trying to perform a read or write
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* operation.
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*/
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if (Status & XIIC_SR_MSTR_RDING_SLAVE_MASK) {
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CallValue = XII_MASTER_READ_EVENT;
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} else {
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CallValue = XII_MASTER_WRITE_EVENT;
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}
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/*
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* If being addressed with general call also indicate to handler.
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*/
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if (Status & XIIC_SR_GEN_CALL_MASK) {
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CallValue |= XII_GENERAL_CALL_EVENT;
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}
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InstancePtr->StatusHandler(InstancePtr->StatusCallBackRef, CallValue);
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return;
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}
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/*****************************************************************************/
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/**
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*
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* This function is called when the IIC device receives Not Addressed As Slave
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* (NAAS) interrupt which indicates that the master has released the bus implying
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* a data transfer is complete.
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*
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* @param InstancePtr is a pointer to the XIic instance to be worked on.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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static void NotAddrAsSlaveHandler(XIic *InstancePtr)
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{
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u32 Status;
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u32 CntlReg;
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u8 BytesToRead;
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u8 LoopCnt;
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/*
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* Disable NAAS so that the condition will not continue to interrupt
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* and enable the addressed as slave interrupt to know when a master
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* selects a slave on the bus.
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*/
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XIic_DisableIntr(InstancePtr->BaseAddress, XIIC_INTR_NAAS_MASK);
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XIic_ClearEnableIntr(InstancePtr->BaseAddress, XIIC_INTR_AAS_MASK);
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/*
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* Flush Tx FIFO by toggling TxFIFOResetBit. FIFO runs normally at 0
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* Do this incase needed to Tx FIFO with more than expected if what
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* was set to Tx was less than what the Master expected - read more
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* from this slave so FIFO had junk in it.
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*/
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XIic_FlushTxFifo(InstancePtr);
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/*
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* NAAS interrupt was asserted but received data in recieve FIFO is
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* less than Rc_FIFO_PIRQ to assert an receive full interrupt,in this
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* condition as data recieved is valid we have to read data before FIFO
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* flush.
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*/
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Status = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_SR_REG_OFFSET);
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if (!(Status & XIIC_SR_RX_FIFO_EMPTY_MASK)) {
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BytesToRead = (XIic_ReadReg(InstancePtr->BaseAddress,
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XIIC_RFO_REG_OFFSET)) + 1;
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|||
|
if (InstancePtr->RecvByteCount > BytesToRead) {
|
|||
|
|
|||
|
for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) {
|
|||
|
XIic_ReadRecvByte(InstancePtr);
|
|||
|
}
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
InstancePtr->RecvByteCount = 0;
|
|||
|
/*
|
|||
|
* Flush Rx FIFO should slave Rx had a problem, sent No ack but
|
|||
|
* still received a few bytes. Should the slave receive have disabled
|
|||
|
* acknowledgement, clear Rx FIFO.
|
|||
|
*/
|
|||
|
XIic_FlushRxFifo(InstancePtr);
|
|||
|
|
|||
|
/*
|
|||
|
* Set FIFO occupancy depth = 1 so that the first byte will throttle
|
|||
|
* next recieve msg.
|
|||
|
*/
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET, 0);
|
|||
|
|
|||
|
/*
|
|||
|
* Should the slave receive have disabled acknowledgement,
|
|||
|
* enable to allow acknowledgment for receipt of our address to
|
|||
|
* again be used as a slave.
|
|||
|
*/
|
|||
|
CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
|
|||
|
(CntlReg & ~XIIC_CR_NO_ACK_MASK));
|
|||
|
|
|||
|
InstancePtr->IsSlaveSetAckOff = FALSE;
|
|||
|
|
|||
|
/*
|
|||
|
* Which callback depends on messaging direction, the buffer pointer NOT
|
|||
|
* being used indicates the direction of data transfer.
|
|||
|
*/
|
|||
|
Status = XIic_ReadIier(InstancePtr->BaseAddress);
|
|||
|
if (InstancePtr->RecvBufferPtr == NULL) {
|
|||
|
/*
|
|||
|
* Slave was sending data so disable all transmit interrupts and
|
|||
|
* call the callback handler to indicate the transfer is
|
|||
|
* complete.
|
|||
|
*/
|
|||
|
XIic_WriteIier(InstancePtr->BaseAddress,
|
|||
|
(Status & ~XIIC_TX_INTERRUPTS));
|
|||
|
InstancePtr->SendHandler(InstancePtr->SendCallBackRef,
|
|||
|
InstancePtr->SendByteCount);
|
|||
|
}
|
|||
|
else {
|
|||
|
/*
|
|||
|
* Slave was receiving data so disable receive full interrupt
|
|||
|
* and call the callback handler to notify the transfer is
|
|||
|
* complete.
|
|||
|
*/
|
|||
|
XIic_WriteIier(InstancePtr->BaseAddress,
|
|||
|
(Status & ~XIIC_INTR_RX_FULL_MASK));
|
|||
|
InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef,
|
|||
|
InstancePtr->RecvByteCount);
|
|||
|
}
|
|||
|
return;
|
|||
|
}
|
|||
|
|
|||
|
/*****************************************************************************/
|
|||
|
/**
|
|||
|
*
|
|||
|
* This function handles data received from the IIC bus as a slave.
|
|||
|
*
|
|||
|
* When the slave expects more than the master has to send, the slave will stall
|
|||
|
* waiting for data.
|
|||
|
*
|
|||
|
* When more data is received than data expected a Nack is done to signal master
|
|||
|
* to stop sending data. The excess data is discarded to prevent bus throttling.
|
|||
|
*
|
|||
|
* The buffer may be full and the master continues to send data if the master
|
|||
|
* and slave have different message lengths. This condition is handled by sending
|
|||
|
* No Ack to the master and reading Rx data until the master stops sending data
|
|||
|
* to prevent but throttling from locking up the bus. To ever receive as a slave
|
|||
|
* again, must know when to renable bus ACKs. NAAS is used to detect when the
|
|||
|
* master is finished sending messages for any mode.
|
|||
|
|
|||
|
* @param InstancePtr is a pointer to the XIic instance to be worked on.
|
|||
|
*
|
|||
|
* @return None.
|
|||
|
*
|
|||
|
* @note None.
|
|||
|
*
|
|||
|
******************************************************************************/
|
|||
|
static void RecvSlaveData(XIic *InstancePtr)
|
|||
|
{
|
|||
|
u32 CntlReg;
|
|||
|
u8 BytesToRead;
|
|||
|
u8 LoopCnt;
|
|||
|
u8 Temp;
|
|||
|
|
|||
|
/*
|
|||
|
* When receive buffer has no room for the receive data discard it.
|
|||
|
*/
|
|||
|
if (InstancePtr->RecvByteCount == 0) {
|
|||
|
/*
|
|||
|
* Set ACKnowlege OFF to signal master to stop sending data.
|
|||
|
*/
|
|||
|
CntlReg = XIic_ReadReg(InstancePtr->BaseAddress,
|
|||
|
XIIC_CR_REG_OFFSET);
|
|||
|
CntlReg |= XIIC_CR_NO_ACK_MASK;
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
|
|||
|
CntlReg);
|
|||
|
|
|||
|
/*
|
|||
|
* Set a Flag to indicate that the Slave has set the ACK Off.
|
|||
|
*/
|
|||
|
InstancePtr->IsSlaveSetAckOff = TRUE;
|
|||
|
|
|||
|
|
|||
|
/*
|
|||
|
* Clear excess received data to prevent bus throttling and set
|
|||
|
* receive FIFO occupancy to throttle at the 1st byte received.
|
|||
|
*/
|
|||
|
XIic_FlushRxFifo(InstancePtr);
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress,
|
|||
|
XIIC_RFD_REG_OFFSET, 0);
|
|||
|
|
|||
|
return;
|
|||
|
}
|
|||
|
/*
|
|||
|
* Use occupancy count to determine how many bytes to read from the
|
|||
|
* FIFO, count is zero based so add 1, read that number of bytes from
|
|||
|
* the FIFO.
|
|||
|
*/
|
|||
|
BytesToRead = (XIic_ReadReg(InstancePtr->BaseAddress,
|
|||
|
XIIC_RFO_REG_OFFSET)) + 1;
|
|||
|
for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) {
|
|||
|
XIic_ReadRecvByte(InstancePtr);
|
|||
|
}
|
|||
|
|
|||
|
/*
|
|||
|
* Set receive FIFO depth for the number of bytes to be received such
|
|||
|
* that a receive interrupt will occur, the count is 0 based, the
|
|||
|
* last byte of the message has to be received seperately to ack the
|
|||
|
* message.
|
|||
|
*/
|
|||
|
if (InstancePtr->RecvByteCount > IIC_RX_FIFO_DEPTH) {
|
|||
|
Temp = IIC_RX_FIFO_DEPTH - 1;
|
|||
|
} else {
|
|||
|
if (InstancePtr->RecvByteCount == 0) {
|
|||
|
Temp = 0;
|
|||
|
} else {
|
|||
|
Temp = InstancePtr->RecvByteCount - 1;
|
|||
|
}
|
|||
|
}
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress,
|
|||
|
XIIC_RFD_REG_OFFSET, (u32) Temp);
|
|||
|
|
|||
|
return;
|
|||
|
}
|
|||
|
|
|||
|
/*****************************************************************************/
|
|||
|
/**
|
|||
|
*
|
|||
|
* This function sends data on the IIC bus as a slave.
|
|||
|
*
|
|||
|
* When message data has been sent, but the master keeps reading data, the FIFO
|
|||
|
* is filled to prevent bus throttling. There is no way to notify master of this
|
|||
|
* condition. While sending data as a slave a transmit error indicates the
|
|||
|
* master has completed the data transfer.
|
|||
|
*
|
|||
|
* NAAS interrupt signals when repeated start occurred and the msg is finished
|
|||
|
* and BNB signals when the master sent a stop.
|
|||
|
*
|
|||
|
* @param InstancePtr is a pointer to the XIic instance to be worked on.
|
|||
|
*
|
|||
|
* @return None.
|
|||
|
*
|
|||
|
* @note None.
|
|||
|
*
|
|||
|
******************************************************************************/
|
|||
|
static void SendSlaveData(XIic *InstancePtr)
|
|||
|
{
|
|||
|
/*
|
|||
|
* When message has been sent, but master keeps reading data, must put a
|
|||
|
* byte in the FIFO or bus will throttle. There is no way to notify
|
|||
|
* master of this condition.
|
|||
|
*/
|
|||
|
if (InstancePtr->SendByteCount == 0) {
|
|||
|
XIic_WriteReg(InstancePtr->BaseAddress,
|
|||
|
XIIC_DTR_REG_OFFSET, 0xFF);
|
|||
|
return;
|
|||
|
}
|
|||
|
|
|||
|
/*
|
|||
|
* Send the data by filling the transmit FIFO.
|
|||
|
*/
|
|||
|
XIic_TransmitFifoFill(InstancePtr, XIIC_SLAVE_ROLE);
|
|||
|
/*
|
|||
|
* When the amount of data remaining to send is less than the half mark
|
|||
|
* of the FIFO making the use of <EFBFBD> empty interrupt unnecessary,
|
|||
|
* disable it. Is this a problem that it's checking against 1 rather
|
|||
|
* than half?
|
|||
|
*/
|
|||
|
if (InstancePtr->SendByteCount < 1) {
|
|||
|
XIic_DisableIntr(InstancePtr->BaseAddress,
|
|||
|
XIIC_INTR_TX_HALF_MASK);
|
|||
|
}
|
|||
|
return;
|
|||
|
}
|