This is the main header file of Xilinx Video Timing Controller (VTC) core. The VTC core detects video signals, independently overrides any one of them, re-generates video signals with +/- delay and with polarity inversion and generates up to 16 one cycle frame sync outputs.<p>
<b>Core Features </b> The core has the following main features:<ul>
<li>Detect video signals:</li><li>horizontal sync</li><li>horizontal blank</li><li>vertical sync</li><li>vertical blank</li><li>active video</li><li>field id</li><li>Independently override any one signal.</li><li>Re-generate video signals with +/- delay and with polarity inversion.</li><li>Generate up to 16 one cycle frame sync outputs.</li></ul>
<b>Software Initialization & Configuration</b><p>
The application needs to do following steps in order for preparing the VTC to be ready to process video signal handling.<p>
<ul>
<li>Call XVtc_LookupConfig using a device ID to find the core configuration.</li><li>Call XVtc_CfgInitialize to initialize the device and the driver instance associated with it.</li><li>Call XVtc_SetGenerator to set up the video signals to generate, if desired.</li><li>Call XVtc_SetPolarity to set up the video signal polarity.</li><li>Call XVtc_SetSource for source selection</li><li>Call XVtc_SetGeneratorHoriOffset to set up the Generator VBlank/VSync horizontal offsets, if values other than the default are needed</li><li>Call XVtc_EnableSync, if generator needs to be synced to the detector</li><li>Call XVtc_Enable to enable/start the VTC device.</li></ul>
<li>Active Chroma signal lock</li><li>Active Video Signal Lock</li><li>Field ID Signal Lock</li><li>Vertical Blank Signal Lock</li><li>Vertical Sync Signal Lock</li><li>Horizontal Blank Signal Lock</li><li>Horizontal Sync Signal Lock</li></ul>
This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.<p>
<b> Threads </b><p>
This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.<p>
<b> Asserts </b><p>
Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.<p>
<b> Building the driver </b><p>
The Vtc driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.<p>
