2014-06-24 16:45:01 +05:30
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/******************************************************************************
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*
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2015-01-20 17:17:41 +05:30
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* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
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2014-06-24 16:45:01 +05:30
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xaxivdma.h
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*
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* This is the Xilinx MVI AXI Video DMA device driver. The DMA engine transfers
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* frames from the AXI Bus or to the AXI Bus. It is in the chain of video
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* IPs, which process video frames.
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*
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* It supports the following features:
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* - Continuous transfers of video frames, AKA circular buffer mode
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* - Continuous transfers of one specific video frame, AKA park mode
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* - Optionally only transfer a certain amount of video frames
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* - Optionally transfer unaligned frame buffers
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*
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* An AXI Video DMA engine can have one or two channels. If configured as two
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* channels, then one of the channels reads data from memory, and the other
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* channel writes to the memory.
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*
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* For a full description of AXI Video DMA features, please see the hardware
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* spec.
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*
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* The driver composes of three parts: initialization, start a DMA transfer, and
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* interrupt handling.
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*
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* <b> Driver Initialization </b>
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*
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* To initialize the driver, the caller needs to pass a configuration structure
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* to the driver. This configuration structure contains information about the
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* hardware build.
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*
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* A caller can manually setup the configuration structure, or call
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* XAxiVdma_LoopkupConfig().
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*
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* The sequence of initialization of the driver is:
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* 1. XAxiVdma_LookupConfig() to get the configuration structure, or manually
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* setup the structure.
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* 2. XAxiVdma_CfgInitialize() to initialize the driver & device.
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* 3. XAxiVdma_SetFrmStore() to set the desired frame store number which
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* is optional.
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* 4. If interrupt is desired:
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* - Set frame counter using XAxiVdma_SetFrameCounter()
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* - Set call back functions for each channel. There are two types of call
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* backfunctions: general and error
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* - Enable interrupts that the user cares about
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*
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* <b>Start a DMA Transaction </b>
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*
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* If you are using the driver API to start the transfer, then there are two
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* ways to start a DMA transaction:
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*
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* 1. Invoke XAxiVdma_StartWriteFrame() or XAxiVdma_StartReadFrame() to start a
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* DMA operation, depending on the purpose of the transfer (Read or Write).
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*
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* 2. Or, call the phased functions as the following:
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* - Call XAxiVdma_DmaConfig() to set up a DMA operation configuration
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* - Call XAxiVdma_DmaSetBufferAddr() to set up the DMA buffers
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* - Call XAxiVdma_DmaStart() to kick off the DMA operation
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*
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* If you are writing your own functions to start the transfer, the order of
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* setting up the hardware must be the following:
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*
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* - Do any processing or setting, but do not start the hardware, means do not
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* set the RUN/STOP bit in the XAXIVDMA_CR_OFFSET register.
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* - After any reset you need to do, write the head of your BD ring into the
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* XAXIVDMA_CDESC_OFFSET register.
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* - You can do other setup for the harware.
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* - Start your hardware, by setting up the RUN/STOP bit in the
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* XAXIVDMA_CR_OFFSET register.
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* - You can do other setup for the hardware.
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* - If you are done with all the setup, now write the tail of your BD ring to
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* the XAXIVDMA_TDESC_OFFSET register to start the transfer.
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*
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* You can refer to XAxiVdma_ChannelStartTransfer() to see how this order is
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* preserved there. The function is in xaxivdma_channel.c.
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*
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* Note a Read VDMA could work with one out of multiple write VDMA instances
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* and vice versa. The PointNum in structure XAxiVdma_DmaSetup decides which
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* VDMA instance this VDMA is working with.
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*
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* <b>Interrupt Handling </b>
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*
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* Each VDMA channel supports 2 kinds of interrupts:
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* - General Interrupt: An interrupt other than error interrupt.
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* - Error Interrupt: An error just happened.
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*
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* The driver does the interrupt handling, and dispatch to the user application
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* through callback functions that user has registered. If there are no
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* registered callback functions, then a stub callback function is called.
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*
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* Each channel has two interrupt callback functions. One for IOC and delay
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* interrupt, or general interrupt; one for error interrupt.
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*
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* <b>Reset</b>
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*
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* Reset a DMA channel causes the channel enter the following state:
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*
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* - Interrupts are disabled
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* - Coalescing threshold is one
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* - Delay counter is 0
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* - RUN/STOP bit low
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* - Halted bit high
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* - XAXIVDMA_CDESC_OFFSET register has 0
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* - XAXIVDMA_TDESC_OFFSET register has 0
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*
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* If there is an active transfer going on when reset (or stop) is issued to
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* the hardware, the current transfer will gracefully finish. For a maximum
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* transfer length of (0x1FFF * 0xFFFF) bytes, on a 100 MHz system, it can take
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* as long as 1.34 seconds, assuming that the system responds to DMA engine's
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* requests quickly.
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*
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* To ensure that the hardware finishes the reset, please use
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* XAxiVdma_ResetNotDone() to check for completion of the reset.
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*
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* To start a transfer after a reset, the following actions are the minimal
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* requirement before setting RUN/STOP bit high to avoid crashing the system:
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*
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* - XAXIVDMA_CDESC_OFFSET register has a valid BD pointer, it should be the
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* head of the BD ring.
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* - XAXIVDMA_TDESC_OFFSET register has a valid BD pointer, it should be the
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* tail of the BD ring.
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*
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* If you are using the driver API to start a transfer after a reset, then it
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* should be fine.
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*
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* <b>Stop</b>
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*
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* Stop a channel using XAxiVDma_DmaStop() is similar to a reset, except the
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* registers are kept intact.
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*
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* To start a transfer after a stop:
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*
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* - If there are error bits in the status register, then a reset is necessary.
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* Please refer to the <b>Reset</b> section for more details on how to start a
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* transfer after a reset.
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* - If there are no error bits in the status register, then you can call
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* XAxiVdma_DmaStart() to start the transfer again. Note that the transfer
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* always starts from the first video frame.
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*
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* <b> Examples</b>
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*
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* We provide one example on how to use the AXI VDMA with AXI Video IPs. This
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* example does not work by itself. To make it work, you must have two other
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* Video IPs to connect to the VDMA. One of the Video IP does the write and the
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* other does the read.
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*
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* <b>Cache Coherency</b>
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*
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* This driver does not handle any cache coherency for the data buffers.
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* The application is responsible for handling cache coherency, if the cache
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* is enabled.
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*
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* <b>Alignment</b>
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*
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* The VDMA supports any buffer alignment when DRE is enabled in the hardware
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* configuration. It only supports word-aligned buffers otherwise. Note that
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* "word" is defined by C_M_AXIS_MM2S_TDATA_WIDTH and C_S_AXIS_S2MM_TDATA_WIDTH
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* for the read and write channel specifically.
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*
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* If the horizonal frame size is not word-aligned, then DRE must be enabled
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* in the hardware. Otherwise, undefined results happen.
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*
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* <b>Address Translation</b>
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*
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* Buffer addresses for transfers are physical addresses. If the system does not
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* use MMU, then physical and virtual addresses are the same.
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*
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* <b>API Change from PLB Video DMA</b>
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*
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* We try to keep the API as consistent with the PLB Video DMA driver as
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* possible. However, due to hardware differences, some of the PLB video DMA
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* driver APIs are changed or removed. Two API functions are added to the AXI
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* DMA driver.
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*
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* For details on the API changes, please refer to xaxivdma_porting_guide.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 08/16/10 First release
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* 2.00a jz 12/10/10 Added support for direct register access mode, v3 core
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* 2.01a jz 01/19/11 Added ability to re-assign BD addresses
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* Replaced include xenv.h with string.h in xaxivdma_i.h
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* file.
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* 2.01a rkv 03/28/11 Added support for frame store register and
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* XAxiVdma_ChannelInit API is changed.
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* 3.00a srt 08/26/11 - Added support for Flush on Frame Sync and dynamic
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* programming of Line Buffer Thresholds.
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* - XAxiVdma_ChannelErrors API is changed to support for
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* Flush on Frame Sync feature.
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* - Two flags, XST_VDMA_MISMATCH_ERROR & XAXIVDMA_MIS
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* MATCH_ERROR are added to report error status when
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* Flush on Frame Sync feature is enabled.
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* 4.00a srt 11/21/11 - XAxiVdma_ChannelSetBufferAddr API is changed to
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* support 32 Frame Stores.
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* - XAxiVdma_ChannelConfig API is changed to support
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* modified Park Offset Register bits.
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* - Added APIs:
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* XAxiVdma_FsyncSrcSelect()
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* XAxiVdma_GenLockSourceSelect()
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* - Modified structures XAxiVdma_Config and XAxiVdma to
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* include new parameters.
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* 4.01a srt 06/13/12 - Added APIs:
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* XAxiVdma_GetDmaChannelErrors()
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* XAxiVdma_ClearDmaChannelErrors()
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* XAxiVdma_ClearChannelErrors()
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* - XAxiVdma_ChannelErrors API is changed to remove
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* Mismatch error logic.
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* - Removed Error checking logic in the channel APIs.
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* Provided User APIs to do this.
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* - Added new error bit mask XAXIVDMA_SR_ERR_SOF_LATE_MASK
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* - XAXIVDMA_MISMATCH_ERROR flag is deprecated.
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* - Modified the logic of Error handling in interrupt
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* handlers.
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* 4.02a srt 10/11/12 - XAxiVdma_SetFrmStore function changed to remove
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* Reset logic after setting number of frame stores.
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* (CR 678734)
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* - Changed Error bitmasks to support IP version 5.02a.
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* (CR 679959)
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* 4.03a srt 01/18/13 - Updated logic of GenLockSourceSelect() & FsyncSrcSelect()
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* APIs for newer versions of IP (CR: 691052).
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* - Modified CfgInitialize() API to initialize
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* StreamWidth parameters and added TDATA_WIDTH parameters
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* to tcl file (CR 691866)
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* - Updated DDR base address for IPI designs (CR 703656).
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* 4.04a srt 03/03/13 - Support for the GenlockRepeat Control bit (Bit 15)
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* added in the new version of IP v5.04 (CR: 691391)
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*
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* - Updated driver tcl, xaxivdma_g.c and XAxiVdma_Config
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* structure in xaxivdma.h to import the relevant VDMA IP
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* DEBUG_INFO_* parameters into the driver.
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* This fixes CR# 703738.
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* 4.05a srt 05/01/3 - Merged v4.03a driver with v4.04a driver.
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* Driver v4.03a - Supports VDMA IPv5.04a XPS release
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* Driver v4.04a - Supports VDMA IPv6.00a IPI release
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* The parameters C_ENABLE_DEBUG_* are only available in
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* VDMA IPv6.00a. These parameters should be set to '1'
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* for older versions of IP (XPS) and added this logic in
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* the driver tcl file.
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* - Added unalignment checks for Hsize and Stride
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* (CR 710279)
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* 4.06a srt 04/09/13 - Added support for the newly added S2MM_DMA_IRQ_MASK
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* register (CR 734741)
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* 5.0 adk 19/12/13 - Updated as per the New Tcl API's
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2015-01-20 17:17:40 +05:30
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* 5.1 adk 20/01/15 Added support for peripheral test. Created the self
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* test example to include it on peripheral test's(CR#823144).
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2015-01-29 12:38:45 +05:30
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* 5.1 adk 29/01/15 Added the sefltest api (XAxiVdma_Selftest) to the driver source files
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* (xaxivdma_selftest.c) and called this from the selftest example
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2014-06-24 16:45:01 +05:30
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XAXIVDMA_H_ /* Prevent circular inclusions */
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#define XAXIVDMA_H_ /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xaxivdma_hw.h"
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#include "xaxivdma_i.h"
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#include "xstatus.h"
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#include "xil_assert.h"
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/************************** Constant Definitions *****************************/
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/**
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* VDMA data transfer direction
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*/
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#define XAXIVDMA_WRITE 1 /**< DMA transfer into memory */
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#define XAXIVDMA_READ 2 /**< DMA transfer from memory */
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/**
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* Frame Sync Source Selection
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*/
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#define XAXIVDMA_CHAN_FSYNC 0
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#define XAXIVDMA_CHAN_OTHER_FSYNC 1
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#define XAXIVDMA_S2MM_TUSER_FSYNC 2
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/**
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* GenLock Source Selection
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*/
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#define XAXIVDMA_EXTERNAL_GENLOCK 0
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#define XAXIVDMA_INTERNAL_GENLOCK 1
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/**
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* GenLock Mode Constants
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*/
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#define XAXIVDMA_GENLOCK_MASTER 0
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#define XAXIVDMA_GENLOCK_SLAVE 1
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#define XAXIVDMA_DYN_GENLOCK_MASTER 2
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#define XAXIVDMA_DYN_GENLOCK_SLAVE 3
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/**
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* Interrupt type for setting up callback
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*/
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#define XAXIVDMA_HANDLER_GENERAL 1 /**< Non-Error Interrupt Type */
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#define XAXIVDMA_HANDLER_ERROR 2 /**< Error Interrupt Type */
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/**
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* Flag to signal that device is ready to be used
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*/
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#define XAXIVDMA_DEVICE_READY 0x11111111
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/**
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* Debug Configuration Parameter Constants (C_ENABLE_DEBUG_INFO_*)
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*/
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#define XAXIVDMA_ENABLE_DBG_THRESHOLD_REG 0x01
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#define XAXIVDMA_ENABLE_DBG_FRMSTORE_REG 0x02
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#define XAXIVDMA_ENABLE_DBG_FRM_CNTR 0x04
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#define XAXIVDMA_ENABLE_DBG_DLY_CNTR 0x08
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#define XAXIVDMA_ENABLE_DBG_ALL_FEATURES 0x0F
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/* Defined for backward compatiblity.
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* This is a typical DMA Internal Error, which on detection doesnt require a
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* reset (as opposed to other errors). So user on seeing this need only to
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* reinitialize channels.
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*
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*/
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#ifndef XST_VDMA_MISMATCH_ERROR
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#define XST_VDMA_MISMATCH_ERROR 1430
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#endif
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/**************************** Type Definitions *******************************/
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/*****************************************************************************/
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/**
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* Callback type for general interrupts
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*
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* @param CallBackRef is a callback reference passed in by the upper layer
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* when setting the callback functions, and passed back to the
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* upper layer when the callback is called.
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* @param InterruptTypes indicates the detailed type(s) of the interrupt.
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* Its value equals 'OR'ing one or more XAXIVDMA_IXR_* values defined
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* in xaxivdma_hw.h
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*****************************************************************************/
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typedef void (*XAxiVdma_CallBack) (void *CallBackRef, u32 InterruptTypes);
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/*****************************************************************************/
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/**
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* Callback type for Error interrupt.
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*
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* @param CallBackRef is a callback reference passed in by the upper layer
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* when setting the callback function, and it is passed back to the
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* upper layer when the callback is called.
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* @param ErrorMask is a bit mask indicating the cause of the error. Its
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* value equals 'OR'ing one or more XAXIVDMA_IXR_* values defined in
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* xaxivdma_hw.h
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*****************************************************************************/
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typedef void (*XAxiVdma_ErrorCallBack) (void *CallBackRef, u32 ErrorMask);
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/**
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* This typedef contains the hardware configuration information for a VDMA
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* device. Each VDMA device should have a configuration structure associated
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* with it.
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*/
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typedef struct {
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u16 DeviceId; /**< DeviceId is the unique ID of the device */
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u32 BaseAddress; /**< BaseAddress is the physical base address of the
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* device's registers */
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u16 MaxFrameStoreNum; /**< The maximum number of Frame Stores */
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int HasMm2S; /**< Whether hw build has read channel */
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int HasMm2SDRE; /**< Read channel supports unaligned transfer */
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int Mm2SWordLen; /**< Read channel word length */
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int HasS2Mm; /**< Whether hw build has write channel */
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int HasS2MmDRE; /**< Write channel supports unaligned transfer */
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int S2MmWordLen; /**< Write channel word length */
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int HasSG; /**< Whether hardware has SG engine */
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int EnableVIDParamRead;
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/**< Read Enable for video parameters in direct
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* register mode */
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int UseFsync; /**< DMA operations synchronized to Frame Sync */
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int FlushonFsync; /**< VDMA Transactions are flushed & channel states
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* reset on Frame Sync */
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int Mm2SBufDepth; /**< Depth of Read Channel Line Buffer FIFO */
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int S2MmBufDepth; /**< Depth of Write Channel Line Buffer FIFO */
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int Mm2SGenLock; /**< Mm2s Gen Lock Mode */
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int S2MmGenLock; /**< S2Mm Gen Lock Mode */
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int InternalGenLock; /**< Internal Gen Lock */
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int S2MmSOF; /**< S2MM Start of Flag Enable */
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int Mm2SStreamWidth; /**< MM2S TData Width */
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int S2MmStreamWidth; /**< S2MM TData Width */
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int Mm2SThresRegEn; /**< MM2S Threshold Register Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_1
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configuration parameter */
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int Mm2SFrmStoreRegEn;/**< MM2S Frame Store Register Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_5
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configuration parameter */
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int Mm2SDlyCntrEn; /**< MM2S Delay Counter (Control Reg) Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_6
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configuration parameter */
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int Mm2SFrmCntrEn; /**< MM2S Frame Counter (Control Reg) Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_7
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configuration parameter */
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int S2MmThresRegEn; /**< S2MM Threshold Register Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_9
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configuration parameter */
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int S2MmFrmStoreRegEn;/**< S2MM Frame Store Register Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_13
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configuration parameter */
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int S2MmDlyCntrEn; /**< S2MM Delay Counter (Control Reg) Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_14
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configuration parameter */
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int S2MmFrmCntrEn; /**< S2MM Frame Counter (Control Reg) Enable Flag
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This corresponds to C_ENABLE_DEBUG_INFO_15
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configuration parameter */
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int EnableAllDbgFeatures;/**< Enable all Debug features
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This corresponds to C_ENABLE_DEBUG_ALL
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configuration parameter */
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} XAxiVdma_Config;
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/**
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* The XAxiVdma_DmaSetup structure contains all the necessary information to
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* start a frame write or read.
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*
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*/
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typedef struct {
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int VertSizeInput; /**< Vertical size input */
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int HoriSizeInput; /**< Horizontal size input */
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int Stride; /**< Stride */
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int FrameDelay; /**< Frame Delay */
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int EnableCircularBuf; /**< Circular Buffer Mode? */
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int EnableSync; /**< Gen-Lock Mode? */
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int PointNum; /**< Master we synchronize with */
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int EnableFrameCounter; /**< Frame Counter Enable */
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u32 FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
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/**< Start Addresses of Frame Store Buffers. */
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int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */
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int GenLockRepeat; /**< Gen-Lock Repeat? */
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} XAxiVdma_DmaSetup;
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/**
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* The XAxiVdmaFrameCounter structure contains the interrupt threshold settings
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* for both the transmit and the receive channel.
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*
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*/
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typedef struct {
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u8 ReadFrameCount; /**< Interrupt threshold for Receive */
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u8 ReadDelayTimerCount; /**< Delay timer threshold for receive */
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u8 WriteFrameCount; /**< Interrupt threshold for transmit */
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u8 WriteDelayTimerCount;/**< Delay timer threshold for transmit */
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} XAxiVdma_FrameCounter;
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/**
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* Channel callback functions
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*/
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typedef struct {
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XAxiVdma_CallBack CompletionCallBack; /**< Call back for completion intr */
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void *CompletionRef; /**< Call back ref */
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XAxiVdma_ErrorCallBack ErrCallBack; /**< Call back for error intr */
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void *ErrRef; /**< Call back ref */
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} XAxiVdma_ChannelCallBack;
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/**
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* The XAxiVdma driver instance data.
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*/
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typedef struct {
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u32 BaseAddr; /**< Memory address for this device */
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int HasSG; /**< Whether hardware has SG engine */
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int IsReady; /**< Whether driver is initialized */
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int MaxNumFrames; /**< Number of frames to work on */
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int HasMm2S; /**< Whether hw build has read channel */
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int HasMm2SDRE; /**< Whether read channel has DRE */
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int HasS2Mm; /**< Whether hw build has write channel */
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int HasS2MmDRE; /**< Whether write channel has DRE */
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int EnableVIDParamRead; /**< Read Enable for video parameters in
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* direct register mode */
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int UseFsync; /**< DMA operations synchronized to
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* Frame Sync */
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int InternalGenLock; /**< Internal Gen Lock */
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XAxiVdma_ChannelCallBack ReadCallBack; /**< Call back for read channel */
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XAxiVdma_ChannelCallBack WriteCallBack; /**< Call back for write channel */
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XAxiVdma_Channel ReadChannel; /**< Channel to read from memory */
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XAxiVdma_Channel WriteChannel; /**< Channel to write to memory */
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} XAxiVdma;
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/************************** Function Prototypes ******************************/
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/* Initialization */
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XAxiVdma_Config *XAxiVdma_LookupConfig(u16 DeviceId);
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int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr,
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u32 EffectiveAddr);
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/* Engine and channel operations */
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void XAxiVdma_Reset(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_ResetNotDone(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_IsBusy(XAxiVdma *InstancePtr, u16 Direction);
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u32 XAxiVdma_CurrFrameStore(XAxiVdma *InstancePtr, u16 Direction);
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u32 XAxiVdma_GetVersion(XAxiVdma *InstancePtr);
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u32 XAxiVdma_GetStatus(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_SetLineBufThreshold(XAxiVdma *InstancePtr, int LineBufThreshold,
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u16 Direction);
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int XAxiVdma_StartParking(XAxiVdma *InstancePtr, int FrameIndex,
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u16 Direction);
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void XAxiVdma_StopParking(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_StartFrmCntEnable(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_IntrEnable(XAxiVdma *InstancePtr, u32 IntrType, u16 Direction);
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void XAxiVdma_IntrDisable(XAxiVdma *InstancePtr, u32 IntrType ,u16 Direction);
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u32 XAxiVdma_IntrGetPending(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_IntrClear(XAxiVdma *InstancePtr, u32 IntrType ,u16 Direction);
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int XAxiVdma_SetBdAddrs(XAxiVdma *InstancePtr, u32 BdAddrPhys, u32 BdAddrVirt,
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int NumBds, u16 Direction);
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XAxiVdma_Channel *XAxiVdma_GetChannel(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_SetFrmStore(XAxiVdma *InstancePtr, u8 FrmStoreNum, u16 Direction);
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void XAxiVdma_GetFrmStore(XAxiVdma *InstancePtr, u8 *FrmStoreNum,
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u16 Direction);
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int XAxiVdma_FsyncSrcSelect(XAxiVdma *InstancePtr, u32 Source,
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u16 Direction);
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int XAxiVdma_GenLockSourceSelect(XAxiVdma *InstancePtr, u32 Source,
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u16 Direction);
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int XAxiVdma_GetDmaChannelErrors(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_ClearDmaChannelErrors(XAxiVdma *InstancePtr, u16 Direction,
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u32 ErrorMask);
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int XAxiVdma_MaskS2MMErrIntr(XAxiVdma *InstancePtr, u32 ErrorMask,
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u16 Direction);
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/* Transfers */
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int XAxiVdma_StartWriteFrame(XAxiVdma *InstancePtr,
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XAxiVdma_DmaSetup *DmaConfigPtr);
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int XAxiVdma_StartReadFrame(XAxiVdma *InstancePtr,
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XAxiVdma_DmaSetup *DmaConfigPtr);
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int XAxiVdma_DmaConfig(XAxiVdma *InstancePtr, u16 Direction,
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XAxiVdma_DmaSetup *DmaConfigPtr);
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int XAxiVdma_DmaSetBufferAddr(XAxiVdma *InstancePtr, u16 Direction,
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u32 *BufferAddrSet);
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int XAxiVdma_DmaStart(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_DmaStop(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_DmaRegisterDump(XAxiVdma *InstancePtr, u16 Direction);
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int XAxiVdma_SetFrameCounter(XAxiVdma *InstancePtr,
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XAxiVdma_FrameCounter *FrameCounterCfgPtr);
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void XAxiVdma_GetFrameCounter(XAxiVdma *InstancePtr,
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XAxiVdma_FrameCounter *FrameCounterCfgPtr);
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/*
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* Interrupt related functions in xaxivdma_intr.c
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*/
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void XAxiVdma_ReadIntrHandler(void * InstancePtr);
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void XAxiVdma_WriteIntrHandler(void * InstancePtr);
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int XAxiVdma_SetCallBack(XAxiVdma * InstancePtr, u32 HandlerType,
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void *CallBackFunc, void *CallBackRef, u16 Direction);
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2015-01-29 12:38:45 +05:30
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int XAxiVdma_Selftest(XAxiVdma * InstancePtr);
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2014-06-24 16:45:01 +05:30
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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