211 lines
8.4 KiB
C
211 lines
8.4 KiB
C
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xbram.h
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*
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* If ECC is not enabled, this driver exists only to allow the tools to
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* create a memory test application and to populate xparameters.h with memory
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* range constants. In this case there is no source code.
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*
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* If ECC is enabled, this file contains the software API definition of the
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* Xilinx BRAM Interface Controller (XBram) device driver.
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*
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* The Xilinx BRAM controller is a soft IP core designed for Xilinx
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* FPGAs and contains the following general features:
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* - LMB v2.0 bus interfaces with byte enable support
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* - Used in conjunction with bram_block peripheral to provide fast BRAM
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* memory solution for MicroBlaze ILMB and DLMB ports
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* - Supports byte, half-word, and word transfers
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* - Supports optional BRAM error correction and detection.
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*
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* The driver provides interrupt management functions. Implementation of
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* interrupt handlers is left to the user. Refer to the provided interrupt
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* example in the examples directory for details.
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*
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* This driver is intended to be RTOS and processor independent. Any needs for
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* dynamic memory management, threads or thread mutual exclusion, virtual
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* memory, or cache control must be satisfied by the layer above this driver.
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*
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* <b>Initialization & Configuration</b>
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*
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* The XBram_Config structure is used by the driver to configure
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* itself. This configuration structure is typically created by the tool-chain
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* based on HW build properties.
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*
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* To support multiple runtime loading and initialization strategies employed
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* by various operating systems, the driver instance can be initialized as
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* follows:
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*
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* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
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* Uses a configuration structure provided by the caller. If running in a
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* system with address translation, the provided virtual memory base address
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* replaces the physical address present in the configuration structure.
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*
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* @note
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*
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* This API utilizes 32 bit I/O to the BRAM registers. With less
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* than 32 bits, the unused bits from registers are read as zero and written as
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* don't cares.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 3.00a sa 05/11/10 Added ECC support
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* 3.01a sa 01/13/12 Changed Selftest API from
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* XBram_SelfTest(XBram *InstancePtr) to
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* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
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* fixed a problem with interrupt generation for CR 639274
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* Modified Selftest example to return XST_SUCCESS when
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* ECC is not enabled and return XST_FAILURE when ECC is
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* enabled and Control Base Address is zero (CR 636581)
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* Modified Selftest to use correct CorrectableCounterBits
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* for CR 635655
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* Updated to check CorrectableFailingDataRegs in the case
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* of LMB BRAM.
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* Added CorrectableFailingDataRegs and
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* UncorrectableFailingDataRegs to the config structure to
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* distinguish between AXI BRAM and LMB BRAM.
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* These registers are not present in the current version of
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* the AXI BRAM Controller.
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* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
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* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
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* to support both xps and vivado designs.
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* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
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* when ecc is disabled cr:705002.
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* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
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* flush the Cache after writing to BRAM in InjectErrors
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* API(CR #719011)
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* 4.0 adk 19/12/13 Updated as per the New Tcl API's
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* </pre>
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*****************************************************************************/
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#ifndef XBRAM_H /* prevent circular inclusions */
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#define XBRAM_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files ********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xstatus.h"
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#include "xbram_hw.h"
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/************************** Constant Definitions ****************************/
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/**************************** Type Definitions ******************************/
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/**
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* This typedef contains configuration information for the device.
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*/
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typedef struct {
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u16 DeviceId; /**< Unique ID of device */
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u32 DataWidth; /**< BRAM data width */
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int EccPresent; /**< Is ECC supported in H/W */
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int FaultInjectionPresent; /**< Is Fault Injection
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* supported in H/W */
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int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
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* supported in H/W */
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int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
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* Registers supported in H/W */
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int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
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* Registers supported in H/W */
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int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
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* Registers supported in H/W */
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int EccStatusInterruptPresent; /**< Are ECC status and interrupts
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* supported in H/W */
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int CorrectableCounterBits; /**< Number of bits in the
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* Correctable Error Counter */
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int EccOnOffRegister; /**< Is ECC on/off register supported
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* in h/w */
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int EccOnOffResetValue; /**< Reset value of the ECC on/off
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* register in h/w */
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int WriteAccess; /**< Is write access enabled in
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* h/w */
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u32 MemBaseAddress; /**< Device memory base address */
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u32 MemHighAddress; /**< Device memory high address */
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u32 CtrlBaseAddress; /**< Device register base address.*/
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u32 CtrlHighAddress; /**< Device register base address.*/
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} XBram_Config;
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/**
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* The XBram driver instance data. The user is required to
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* allocate a variable of this type for every BRAM device in the
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* system. A pointer to a variable of this type is then passed to the driver
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* API functions.
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*/
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typedef struct {
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XBram_Config Config; /* BRAM config structure */
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u32 IsReady; /* Device is initialized and ready */
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} XBram;
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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/*
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* Functions in xbram_sinit.c
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*/
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XBram_Config *XBram_LookupConfig(u16 DeviceId);
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/*
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* Functions implemented in xbram.c
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*/
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int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
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u32 EffectiveAddr);
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/*
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* Functions implemented in xbram_selftest.c
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*/
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int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
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/*
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* Functions implemented in xbram_intr.c
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*/
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void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
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void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
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void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
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u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
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u32 XBram_InterruptGetStatus(XBram *InstancePtr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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