358 lines
10 KiB
C
358 lines
10 KiB
C
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/******************************************************************************
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*
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* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xaxidma_example_simple_poll.c
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*
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* This file demonstrates how to use the xaxidma driver on the Xilinx AXI
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* DMA core (AXIDMA) to transfer packets in polling mode when the AXI DMA core
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* is configured in simple mode.
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*
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* This code assumes a loopback hardware widget is connected to the AXI DMA
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* core for data packet loopback.
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*
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* To see the debug print, you need a Uart16550 or uartlite in your system,
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* and please set "-DDEBUG" in your compiler options. You need to rebuild your
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* software executable.
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*
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* Make sure that MEMORY_BASE is defined properly as per the HW system. The
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* h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
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* throughput mode, it is 512MB. These limits are need to ensured for
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* proper operation of this code.
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*
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 4.00a rkv 02/22/11 New example created for simple DMA, this example is for
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* simple DMA
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* 5.00a srt 03/06/12 Added Flushing and Invalidation of Caches to fix CRs
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* 648103, 648701.
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* Added V7 DDR Base Address to fix CR 649405.
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* 6.00a srt 03/27/12 Changed API calls to support MCDMA driver.
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* 7.00a srt 06/18/12 API calls are reverted back for backward compatibility.
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* 7.01a srt 11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
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* DDR memory limit of the h/w system built with Area mode
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* 7.02a srt 03/01/13 Updated DDR base address for IPI designs (CR 703656).
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*
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* </pre>
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*
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* ***************************************************************************
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*/
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/***************************** Include Files *********************************/
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#include "xaxidma.h"
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#include "xparameters.h"
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#include "xdebug.h"
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#if defined(XPAR_UARTNS550_0_BASEADDR)
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#include "xuartns550_l.h" /* to use uartns550 */
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#endif
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/******************** Constant Definitions **********************************/
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/*
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* Device hardware build related constants.
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*/
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#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID
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#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_V6DDR_0_S_AXI_BASEADDR
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#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_S6DDR_0_S0_AXI_BASEADDR
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#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#elif XPAR_MIG7SERIES_0_BASEADDR
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#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR
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#endif
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#ifndef DDR_BASE_ADDR
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#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
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DEFAULT SET TO 0x01000000
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#define MEM_BASE_ADDR 0x01000000
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#else
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#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000)
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#endif
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#define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000)
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#define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00300000)
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#define RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x004FFFFF)
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#define MAX_PKT_LEN 0x20
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#define TEST_START_VALUE 0xC
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#define NUMBER_OF_TRANSFERS 10
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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#if (!defined(DEBUG))
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extern void xil_printf(const char *format, ...);
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#endif
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int XAxiDma_SimplePollExample(u16 DeviceId);
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static int CheckData(void);
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/************************** Variable Definitions *****************************/
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/*
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* Device instance definitions
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*/
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XAxiDma AxiDma;
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/*****************************************************************************/
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/*
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* The entry point for this example. It invokes the example function,
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* and reports the execution status.
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*
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* @param None.
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*
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* @return
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* - XST_SUCCESS if example finishes successfully
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* - XST_FAILURE if example fails.
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*
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* @note None.
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*
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******************************************************************************/
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int main()
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{
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int Status;
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xil_printf("\r\n--- Entering main() --- \r\n");
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/* Run the poll example for simple transfer */
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Status = XAxiDma_SimplePollExample(DMA_DEV_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("XAxiDma_SimplePollExample: Failed\r\n");
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return XST_FAILURE;
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}
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xil_printf("XAxiDma_SimplePollExample: Passed\r\n");
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xil_printf("--- Exiting main() --- \r\n");
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return XST_SUCCESS;
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}
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#if defined(XPAR_UARTNS550_0_BASEADDR)
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/*****************************************************************************/
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/*
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*
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* Uart16550 setup routine, need to set baudrate to 9600, and data bits to 8
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*
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* @param None.
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void Uart550_Setup(void)
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{
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/* Set the baudrate to be predictable
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*/
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XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
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XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
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XUN_LCR_8_DATA_BITS);
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}
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#endif
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/*****************************************************************************/
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/**
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* The example to do the simple transfer through polling. The constant
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* NUMBER_OF_TRANSFERS defines how many times a simple transfer is repeated.
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*
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* @param DeviceId is the Device Id of the XAxiDma instance
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*
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* @return
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* - XST_SUCCESS if example finishes successfully
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* - XST_FAILURE if error occurs
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*
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* @note None
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*
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*
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******************************************************************************/
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int XAxiDma_SimplePollExample(u16 DeviceId)
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{
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XAxiDma_Config *CfgPtr;
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int Status;
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int Tries = NUMBER_OF_TRANSFERS;
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int Index;
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u8 *TxBufferPtr;
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u8 *RxBufferPtr;
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u8 Value;
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TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
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RxBufferPtr = (u8 *)RX_BUFFER_BASE;
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/* Initialize the XAxiDma device.
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*/
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CfgPtr = XAxiDma_LookupConfig(DeviceId);
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if (!CfgPtr) {
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xil_printf("No config found for %d\r\n", DeviceId);
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return XST_FAILURE;
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}
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Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed %d\r\n", Status);
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return XST_FAILURE;
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}
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if(XAxiDma_HasSg(&AxiDma)){
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xil_printf("Device configured as SG mode \r\n");
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return XST_FAILURE;
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}
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/* Disable interrupts, we use polling mode
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*/
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XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
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XAXIDMA_DEVICE_TO_DMA);
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XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
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XAXIDMA_DMA_TO_DEVICE);
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Value = TEST_START_VALUE;
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for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
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TxBufferPtr[Index] = Value;
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Value = (Value + 1) & 0xFF;
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}
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/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
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* is enabled
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*/
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Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
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for(Index = 0; Index < Tries; Index ++) {
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Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
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MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
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MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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while ((XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) ||
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(XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))) {
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/* Wait */
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}
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Status = CheckData();
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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}
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/* Test finishes successfully
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*/
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/*
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*
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* This function checks data buffer after the DMA transfer is finished.
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*
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* @param None
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*
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* @return
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* - XST_SUCCESS if validation is successful.
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* - XST_FAILURE otherwise.
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*
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* @note None.
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*
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******************************************************************************/
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static int CheckData(void)
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{
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u8 *RxPacket;
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int Index = 0;
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u8 Value;
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RxPacket = (u8 *) RX_BUFFER_BASE;
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Value = TEST_START_VALUE;
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/* Invalidate the DestBuffer before receiving the data, in case the
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* Data Cache is enabled
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*/
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Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN);
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for(Index = 0; Index < MAX_PKT_LEN; Index++) {
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if (RxPacket[Index] != Value) {
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xil_printf("Data error %d: %x/%x\r\n",
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Index, (unsigned int)RxPacket[Index],
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(unsigned int)Value);
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return XST_FAILURE;
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}
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Value = (Value + 1) & 0xFF;
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}
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return XST_SUCCESS;
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}
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