<h1>bram v4_0</h1><p>If ECC is not enabled, this driver exists only to allow the tools to create a memory test application and to populate xparameters.h with memory range constants. In this case there is no source code.</p>
<p>If ECC is enabled, this file contains the software API definition of the Xilinx BRAM Interface Controller (<aclass="el"href="struct_x_bram.html">XBram</a>) device driver.</p>
<p>The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features:</p>
<li>LMB v2.0 bus interfaces with byte enable support</li>
<li>Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports</li>
<li>Supports byte, half-word, and word transfers</li>
<li>Supports optional BRAM error correction and detection.</li>
</ul>
<p>The driver provides interrupt management functions. Implementation of interrupt handlers is left to the user. Refer to the provided interrupt example in the examples directory for details.</p>
<p>This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
<p><b>Initialization & Configuration</b></p>
<p>The <aclass="el"href="struct_x_bram___config.html">XBram_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized as follows:</p>
<ul>
<li>XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
<p>This API utilizes 32 bit I/O to the BRAM registers. With less than 32 bits, the unused bits from registers are read as zero and written as don't cares.</p>
