<h1>emaclite v4_0</h1><p>The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx Ethernet Lite 10/100 MAC (EmacLite).</p>
<p>The Xilinx Ethernet Lite 10/100 MAC supports the following features:</p>
<ul>
<li>Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers</li>
<li>Independent internal transmit and receive buffers</li>
<li>CSMA/CD compliant operations for half-duplex modes</li>
<li>Unicast and broadcast</li>
<li>Automatic FCS insertion</li>
<li>Automatic pad insertion on transmit</li>
<li>Configurable ping/pong buffers for either/both transmit and receive buffer areas</li>
<li>Interrupt driven mode</li>
<li>Internal loop back</li>
<li>MDIO Support to access PHY Registers</li>
</ul>
<p>The Xilinx Ethernet Lite 10/100 MAC does not support the following features:</p>
<ul>
<li>multi-frame buffering only 1 transmit frame is allowed into each transmit buffer, only 1 receive frame is allowed into each receive buffer. the hardware blocks reception until buffer is emptied</li>
<li>Pause frame (flow control) detection in full-duplex mode</li>
<li>Programmable inter frame gap</li>
<li>Multicast and promiscuous address filtering</li>
<li>Automatic source address insertion or overwrite</li>
</ul>
<p><b>Driver Description</b></p>
<p>The device driver enables higher layer software (e.g., an application) to communicate to the EmacLite. The driver handles transmission and reception of Ethernet frames, as well as configuration of the controller. It does not handle protocol stack functionality such as Link Layer Control (LLC) or the Address Resolution Protocol (ARP). The protocol stack that makes use of the driver handles this functionality. This implies that the driver is simply a pass-through mechanism between a protocol stack and the EmacLite.</p>
<p>Since the driver is a simple pass-through mechanism between a protocol stack and the EmacLite, no assembly or disassembly of Ethernet frames is done at the driver-level. This assumes that the protocol stack passes a correctly formatted Ethernet frame to the driver for transmission, and that the driver does not validate the contents of an incoming frame. A single device driver can support multiple EmacLite devices.</p>
<p>The driver supports interrupt driven mode and the default mode of operation is polled mode. If interrupts are desired, XEmacLite_InterruptEnable() must be called.</p>
<p><b>Device Configuration</b></p>
<p>The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the <aclass="el"href="xemaclite__g_8c.html">xemaclite_g.c</a> file. A table is defined where each entry contains configuration information for an EmacLite device. This information includes such things as the base address of the memory-mapped device and the number of buffers.</p>
<p><b>Interrupt Processing</b></p>
<p>After _Initialize is called, _InterruptEnable can be called to enable the interrupt driven functionality. If polled operation is desired, just call _Send and check the return code. If XST_FAILURE is returned, call _Send with the same data until XST_SUCCESS is returned. The same idea applies to _Recv. Call _Recv until the returned length is non-zero at which point the received data is in the buffer provided in the function call.</p>
<p>The Transmit and Receive interrupts are enabled within the _InterruptEnable function and disabled in the _InterruptDisable function. The _Send and _Recv functions acknowledge the EmacLite generated interrupts associated with each function. It is the application's responsibility to acknowledge any associated Interrupt Controller interrupts if it is used in the system.</p>
<p><b>Memory Buffer Alignment</b></p>
<p>The alignment of the input/output buffers for the _Send and _Recv routine is not required to be 32 bits. If the buffer is not aligned on a 32-bit boundary there will be a performance impact while the driver aligns the data for transmission or upon reception.</p>
<p>For optimum performance, the user should provide a 32-bit aligned buffer to the _Send and _Recv routines.</p>
<p><b>Asserts</b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.</p>
<p>This driver requires EmacLite hardware version 1.01a and higher. It is not compatible with earlier versions of the EmacLite hardware. Use version 1.00a software driver for hardware version 1.00a/b.</p>
<p>The RX hardware is enabled from powerup and there is no disable. It is possible that frames have been received prior to the initialization of the driver. If this situation is possible, call <aclass="el"href="xemaclite_8c.html#ae7ced3b39bd2f06d037660e884c0706b">XEmacLite_FlushReceive()</a> to empty the receive buffers after initialization.</p>
<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
