<h1>iic v3_0</h1><p><aclass="el"href="struct_x_iic.html">XIic</a> is the driver for an IIC master or slave device.</p>
<p>In order to reduce the memory requirements of the driver the driver is partitioned such that there are optional parts of the driver. Slave, master, and multimaster features are optional such that all these files are not required at the same time. In order to use the slave and multimaster features of the driver, the user must call functions (XIic_SlaveInclude and XIic_MultiMasterInclude) to dynamically include the code. These functions may be called at any time.</p>
<p>Two sets of higher level API's are available in the <aclass="el"href="struct_x_iic.html">XIic</a> driver that can be used for Transmission/Reception in Master mode :</p>
<li><aclass="el"href="xiic_8h.html#a977382e8a20bd5e690229f82af2e7603">XIic_MasterSend()</a>/ <aclass="el"href="xiic_8h.html#a337bf0d322d4a7d9b4f8baa30e00ab45">XIic_MasterRecv()</a> which is used in normal mode.</li>
<li><aclass="el"href="xiic_8h.html#ac4c6388d0db3b08ddcd47f0b2459ff3c">XIic_DynMasterSend()</a>/ <aclass="el"href="xiic_8h.html#a4d7985d95cd029ab0b0f2a5ccc614793">XIic_DynMasterRecv()</a> which is used in Dynamic mode.</li>
</ul>
<p>Similarly two sets of lower level API's are available in <aclass="el"href="struct_x_iic.html">XIic</a> driver that can be used for Transmission/Reception in Master mode:</p>
<li><aclass="el"href="xiic__l_8c.html#a952044c7351320eabd1c5eb88a86df72">XIic_Send()</a>/ <aclass="el"href="xiic__l_8c.html#a5f5a62605b7b98a12b7205009c3127ab">XIic_Recv()</a> which is used in normal mode</li>
<li><aclass="el"href="xiic__l_8c.html#a5d71de29f1ef78850860fbb10b5a0a3e">XIic_DynSend()</a>/ <aclass="el"href="xiic__l_8c.html#a5183097e8363be354a6f7f488940228f">XIic_DynRecv()</a> which is used in Dynamic mode.</li>
</ul>
<p>The user should use a single set of APIs as per his requirement and should not intermix them.</p>
<p>All the driver APIs can be used for read, write and combined mode of operations on the IIC bus.</p>
<p>In the normal mode IIC support both 7-bit and 10-bit addressing, and in the dynamic mode support only 7-bit addressing.</p>
<p><b>Initialization & Configuration</b></p>
<p>The <aclass="el"href="struct_x_iic___config.html">XIic_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in one of the following ways:</p>
<ul>
<li><aclass="el"href="xiic_8h.html#ad36c610ec3139cef71f3795f9ce81308">XIic_Initialize()</a> - The driver looks up its own configuration structure created by the tool-chain based on an ID provided by the tool-chain.</li>
</ul>
<ul>
<li><aclass="el"href="xiic_8c.html#ae1d05b288ae1f48c484d0fd308e72f8c">XIic_CfgInitialize()</a> - The driver uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
</ul>
<p><b>General Purpose Output</b> The IIC hardware provides a General Purpose Output Register that allows the user to connect general purpose outputs to devices, such as a write protect, for an EEPROM. This register is parameterizable in the hardware such that there could be zero bits in this register and in this case it will cause a bus error if read or written.</p>
<p><b>Bus Throttling</b></p>
<p>The IIC hardware provides bus throttling which allows either the device, as either a master or a slave, to stop the clock on the IIC bus. This feature allows the software to perform the appropriate processing for each interrupt without an unreasonable response restriction. With this design, it is important for the user to understand the implications of bus throttling.</p>
<p><b>Repeated Start</b></p>
<p>An application can send multiple messages, as a master, to a slave device and re-acquire the IIC bus each time a message is sent. The repeated start option allows the application to send multiple messages without re-acquiring the IIC bus for each message. The transactions involving repeated start are also called combined transfers if there is Read and Write in the same transaction.</p>
<p>The repeated start feature works with all the API's in <aclass="el"href="struct_x_iic.html">XIic</a> driver.</p>
<p>The Repeated Start feature also could cause the application to lock up, or monopolize the IIC bus, should repeated start option be enabled and sequences of messages never end(periodic data collection). Also when repeated start is not disable before the last master message is sent or received, will leave the bus captive to the master, but unused.</p>
<p><b>Addressing</b></p>
<p>The IIC hardware is parameterized such that it can be built for 7 or 10 bit addresses. The driver provides the ability to control which address size is sent in messages as a master to a slave device. The address size which the hardware responds to as a slave is parameterized as 7 or 10 bits but fixed by the hardware build.</p>
<p>Addresses are represented as hex values with no adjustment for the data direction bit as the software manages address bit placement. This is especially important as the bit placement is not handled the same depending on which options are used such as repeated start and 7 vs 10 bit addessing.</p>
<p><b>Data Rates</b></p>
<p>The IIC hardware is parameterized such that it can be built to support data rates from DC to 400KBit. The frequency of the interrupts which occur is proportional to the data rate.</p>
<p><b>Polled Mode Operation</b></p>
<p>This driver does not provide a polled mode of operation primarily because polled mode which is non-blocking is difficult with the amount of interaction with the hardware that is necessary.</p>
<p><b>Interrupts</b></p>
<p>The device has many interrupts which allow IIC data transactions as well as bus status processing to occur.</p>
<p>The interrupts are divided into two types, data and status. Data interrupts indicate data has been received or transmitted while the status interrupts indicate the status of the IIC bus. Some of the interrupts, such as Not Addressed As Slave and Bus Not Busy, are only used when these specific events must be recognized as opposed to being enabled at all times.</p>
<p>Many of the interrupts are not a single event in that they are continuously present such that they must be disabled after recognition or when undesired. Some of these interrupts, which are data related, may be acknowledged by the software by reading or writing data to the appropriate register, or must be disabled. The following interrupts can be continuous rather than single events.</p>
<p>The following interrupts are not passed directly to the application thru the status callback. These are only used internally for the driver processing and may result in the receive and send handlers being called to indicate completion of an operation. The following interrupts are data related rather than status.</p>
<p>The following table provides a mapping of the interrupts to the events which are passed to the status handler and the intended role (master or slave) for the event. Some interrupts can cause multiple events which are combined together into a single status event such as XII_MASTER_WRITE_EVENT and XII_GENERAL_CALL_EVENT </p>
<pre>
Interrupt Event(s) Role</pre><pre> Arbitration Lost Interrupt XII_ARB_LOST_EVENT Master
</pre><p><b>Not Addressed As Slave Interrupt</b></p>
<p>The Not Addressed As Slave interrupt is not passed directly to the application thru the status callback. It is used to determine the end of a message being received by a slave when there was no stop condition (repeated start). It will cause the receive handler to be called to indicate completion of the operation.</p>
<p><b>RTOS Independence</b></p>
<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
