<h1>llfifo v4_0</h1><p>The Xilinx Dual Channel Fifo driver component. This driver supports the Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.</p>
<p>For a full description of the bridge features, please see the HW spec. This driver supports the following features:</p>
<ul>
<li>Memory mapped access to host interface registers</li>
<p>It is fairly simple to use the API provided by this FIFO driver. The only somewhat tricky part is that the calling code must correctly call a couple routines in the right sequence for receive and transmit.</p>
<p>This sequence is described here. Check the routine functional descriptions for information on how to use a specific API routine.</p>
<p>A frame is received by using the following sequence:<br/>
1) call <aclass="el"href="xllfifo_8h.html#a12da547aa1c9a85e2b0b151f438ff9d5">XLlFifo_RxOccupancy()</a> to check the occupancy count<br/>
2) call <aclass="el"href="xllfifo_8h.html#a53af32ae6901462cc8d6fb9adc04655e">XLlFifo_RxGetLen()</a> to get the length of the next incoming frame<br/>
3) call <aclass="el"href="xllfifo_8h.html#aadc3685592b060c0d864850e86be5c03">XLlFifo_Read()</a> one or more times to read the number of bytes reported by <aclass="el"href="xllfifo_8h.html#a53af32ae6901462cc8d6fb9adc04655e">XLlFifo_RxGetLen()</a>.<br/>
</p>
<p>For example: </p>
<pre>
while (<aclass="el"href="xllfifo_8h.html#a12da547aa1c9a85e2b0b151f438ff9d5">XLlFifo_RxOccupancy(&RxInstance)</a>) {
</pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code calls RxGetLen() twice in a row and then receive the data for two frames. Each frame must be read in by calling RxGetLen() just prior to reading the data.</p>
<p>A frame is transmittted by using the following sequence:<br/>
1) call <aclass="el"href="xllfifo_8h.html#a1fa93f486abaaf35c7d599a8cd91b295">XLlFifo_Write()</a> one or more times to write all the of bytes in the next frame.<br/>
2) call <aclass="el"href="xllfifo_8h.html#acd09ed5189e0b85994901102655964f7">XLlFifo_TxSetLen()</a> to begin the transmission of frame just written.<br/>
</pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code writes the data for two frames and then calls TxSetLen() twice in a row. Each frame must be written by writting the data for one frame and then calling TxSetLen().</p>
<p>This driver does not handle interrupts from the FIFO hardware. The software layer above may make use of the interrupts by setting up its own handlers for the interrupts.</p>