152 lines
7 KiB
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152 lines
7 KiB
HTML
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<html>
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<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>
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xllfifo.c File Reference
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</title>
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<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
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</head>
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<hr class="whs1">
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<!-- Generated by Doxygen 1.4.5 -->
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<div class="tabs">
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<ul>
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<li><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="annotated.html"><span>Classes</span></a></li>
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<li id="current"><a href="files.html"><span>Files</span></a></li>
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</ul></div>
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<div class="tabs">
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<ul>
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<li><a href="files.html"><span>File List</span></a></li>
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<li><a href="globals.html"><span>File Members</span></a></li>
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</ul></div>
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<h1>xllfifo.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
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The Xilinx local link FIFO driver component. This driver supports the Xilinx xps_ll_fifo core.<p>
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<pre>
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MODIFICATION HISTORY:</pre><p>
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<pre> Ver Who Date Changes
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----- ---- -------- -------------------------------------------------------
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1.00a jvb 10/13/06 First release
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1.00a xd 12/17/07 Added type casting to fix CR #456850
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1.02a jz 12/04/09 Hal phase 1 support
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2.00a hbm 01/20/10 Hal phase 1 support, bump up major release
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2.01a asa 09/17/10 Added code for resetting Streaming interface
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for CR574868
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3.00a adk 08/10/13 Added support for AXI4 Datainterface.Updated
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XLlFifo_RxGetWord, XLlFifo_TxPutword inorder to
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handle AXI4 Datainterface. Added Config
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initialization for the driver.
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</pre>
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<p>
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<code>#include "xstatus.h"</code><br>
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<code>#include "xllfifo.h"</code><br>
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<code>#include "xil_assert.h"</code><br>
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<table border="0" cellpadding="0" cellspacing="0">
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<tr><td></td></tr>
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<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="xllfifo_8c.html#2fe123c957f759858100542feb21be2d">XLlFifo_CfgInitialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="xllfifo_8c.html#83642984b46fd728640f099a09eeeebd">XLlFifo_Initialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, u32 BaseAddress)</td></tr>
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</table>
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<hr><h2>Function Documentation</h2>
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<a class="anchor" name="2fe123c957f759858100542feb21be2d"></a><!-- doxytag: member="xllfifo.c::XLlFifo_CfgInitialize" ref="2fe123c957f759858100542feb21be2d" args="(XLlFifo *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)" --><p>
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<table class="mdTable" cellpadding="2" cellspacing="0">
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<tr>
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<td class="mdRow">
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<table cellpadding="0" cellspacing="0" border="0">
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<tr>
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<td class="md" nowrap valign="top">int XLlFifo_CfgInitialize </td>
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<td class="md" valign="top">( </td>
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<td class="md" nowrap valign="top"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> * </td>
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<td class="mdname" nowrap> <em>InstancePtr</em>, </td>
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</tr>
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<tr>
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<td class="md" nowrap align="right"></td>
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<td class="md"></td>
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<td class="md" nowrap>XLlFifo_Config * </td>
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<td class="mdname" nowrap> <em>Config</em>, </td>
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</tr>
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<tr>
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<td class="md" nowrap align="right"></td>
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<td class="md"></td>
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<td class="md" nowrap>u32 </td>
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<td class="mdname" nowrap> <em>EffectiveAddress</em></td>
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</tr>
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<tr>
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<td class="md"></td>
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<td class="md">) </td>
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<td class="md" colspan="2"></td>
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</tr>
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</table>
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</td>
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</tr>
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</table>
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<table cellspacing="5" cellpadding="0" border="0">
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<tr>
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<td>
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</td>
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<td>
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<p>
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XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it.<p>
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<dl compact><dt><b>Parameters:</b></dt><dd>
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<table border="0" cellspacing="2" cellpadding="0">
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<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em> </td><td>is a pointer to the Axi Streaming FIFO instance to be worked on. </td></tr>
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<tr><td valign="top"></td><td valign="top"><em>CfgPtr</em> </td><td>references the structure holding the hardware configuration for the Axi Streaming FIFO core to initialize. </td></tr>
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<tr><td valign="top"></td><td valign="top"><em>EffectiveAddr</em> </td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config->BaseAddress for this parameters, passing the physical address instead.</td></tr>
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</table>
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</dl>
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<dl compact><dt><b>Returns:</b></dt><dd>N/A </dd></dl>
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</td>
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</tr>
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</table>
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<a class="anchor" name="83642984b46fd728640f099a09eeeebd"></a><!-- doxytag: member="xllfifo.c::XLlFifo_Initialize" ref="83642984b46fd728640f099a09eeeebd" args="(XLlFifo *InstancePtr, u32 BaseAddress)" --><p>
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<table class="mdTable" cellpadding="2" cellspacing="0">
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<tr>
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<td class="mdRow">
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<table cellpadding="0" cellspacing="0" border="0">
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<tr>
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<td class="md" nowrap valign="top">void XLlFifo_Initialize </td>
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<td class="md" valign="top">( </td>
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<td class="md" nowrap valign="top"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> * </td>
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<td class="mdname" nowrap> <em>InstancePtr</em>, </td>
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</tr>
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<tr>
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<td class="md" nowrap align="right"></td>
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<td class="md"></td>
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<td class="md" nowrap>u32 </td>
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<td class="mdname" nowrap> <em>BaseAddress</em></td>
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</tr>
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<tr>
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<td class="md"></td>
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<td class="md">) </td>
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<td class="md" colspan="2"></td>
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</tr>
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</table>
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</td>
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</tr>
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</table>
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<table cellspacing="5" cellpadding="0" border="0">
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<tr>
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<td>
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</td>
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<td>
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<p>
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XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it.<p>
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<dl compact><dt><b>Parameters:</b></dt><dd>
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<table border="0" cellspacing="2" cellpadding="0">
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<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em> </td><td>references the memory instance to be associated with the FIFO device upon initialization.</td></tr>
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<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em> </td><td>is the processor address used to access the base address of the Fifo device.</td></tr>
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</table>
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</dl>
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<dl compact><dt><b>Returns:</b></dt><dd>N/A </dd></dl>
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</td>
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</tr>
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</table>
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
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