237 lines
9.3 KiB
C
237 lines
9.3 KiB
C
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/*******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*******************************************************************************/
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/******************************************************************************/
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/**
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*
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* @file xdptx_example_common.c
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*
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* Contains a design example using the XDptx driver. It performs a self test on
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* the DisplayPort TX core by training the main link at the maximum common
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* capabilities between the TX and RX and checking the lane status.
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*
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* @note The DisplayPort TX core does not work alone. Some platform
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* initialization will need to happen prior to calling XDptx driver
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* functions. See XAPP1178 as a reference.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a als 06/17/14 Initial creation.
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* </pre>
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*
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*******************************************************************************/
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/******************************* Include Files ********************************/
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#include "xdptx_example_common.h"
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#include "xstatus.h"
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/**************************** Function Prototypes *****************************/
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static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate);
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static void Dptx_StartVideoStream(XDptx *InstancePtr);
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/**************************** Function Definitions ****************************/
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u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
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{
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u32 Status;
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Status = Dptx_StartLink(InstancePtr, LaneCount, LinkRate);
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if (Status == XST_SUCCESS) {
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Dptx_StartVideoStream(InstancePtr);
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} else {
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xil_printf("<-- Failed to train.\n");
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
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{
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XDptx_Config *ConfigPtr;
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u32 Status;
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/* Obtain the device configuration for the DisplayPort TX core. */
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ConfigPtr = XDptx_LookupConfig(DeviceId);
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if (!ConfigPtr) {
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return XST_FAILURE;
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}
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XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
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/* Initialize the DisplayPort TX core. */
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Status = XDptx_InitializeTx(InstancePtr);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
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{
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u32 VsLevelTx;
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u32 PeLevelTx;
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u32 Status;
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/* Obtain the capabilities of the sink by reading the monitor's DPCD. */
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Status = XDptx_GetSinkCapabilities(InstancePtr);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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#if defined(USE_MAX_LINK)
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Status = XDptx_CheckLinkStatus(InstancePtr,
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InstancePtr->LinkConfig.MaxLaneCount);
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#else
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Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
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#endif
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if (Status == XST_SUCCESS) {
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xil_printf("-> Does not need training.\n");
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if (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
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XDPTX_LINK_BW_SET) == LinkRate) {
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return XST_SUCCESS;
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}
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}
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else if (Status == XST_FAILURE) {
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xil_printf("-> Needs training.\n");
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}
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else {
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xil_printf("-> Error checking link status.\n");
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return XST_FAILURE;
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}
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#if defined(USE_MAX_LINK)
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/* Configure the main link based on the common capabilities of the
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* transmitter core and the sink monitor. */
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Status = XDptx_CfgMainLinkMax(InstancePtr);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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#else
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XDptx_SetLinkRate(InstancePtr, LinkRate);
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XDptx_SetLaneCount(InstancePtr, LaneCount);
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XDptx_SetEnhancedFrameMode(InstancePtr, 1);
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XDptx_SetDownspread(InstancePtr, 0);
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#endif
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xil_printf("******************************************\n");
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Status = XDptx_EstablishLink(InstancePtr);
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if (Status != XST_SUCCESS) {
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xil_printf("!!! Training failed !!!\n");
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xil_printf("******************************************\n");
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return XST_FAILURE;
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}
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VsLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
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XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
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PeLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
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XDPTX_PHY_POSTCURSOR_LANE_0);
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xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
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InstancePtr->LinkConfig.LinkRate,
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InstancePtr->LinkConfig.LaneCount);
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xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
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InstancePtr->LinkConfig.VsLevel, VsLevelTx,
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InstancePtr->LinkConfig.PeLevel, PeLevelTx);
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xil_printf("******************************************\n");
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return XST_SUCCESS;
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}
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static void Dptx_StartVideoStream(XDptx *InstancePtr)
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{
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u32 Status;
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u8 AuxData[1];
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/* Set the bits per color. If not set, the default is 6. */
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XDptx_CfgMsaSetBpc(InstancePtr, 8);
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/* Choose a method for selecting the video mode. There are 3 ways to do this:
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* 1) Use the preferred timing from the monitor's EDID:
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* XDptx_GetEdid(InstancePtr);
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* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
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*
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* 2) Use a standard video timing mode (see mode_table.h):
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* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
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*
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* 3) Use a custom configuration for the main stream attributes:
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* XDptx_MainStreamAttributes MsaConfigCustom;
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* MsaConfigCustom.MVid = 108000;
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* MsaConfigCustom.HSyncPolarity = 0;
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* MsaConfigCustom.VSyncPolarity = 0;
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* MsaConfigCustom.HSyncPulseWidth = 112;
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* MsaConfigCustom.VSyncPulseWidth = 3;
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* MsaConfigCustom.HResolution = 1280;
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* MsaConfigCustom.VResolution = 1024;
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* MsaConfigCustom.VBackPorch = 38;
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* MsaConfigCustom.VFrontPorch = 1;
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* MsaConfigCustom.HBackPorch = 248;
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* MsaConfigCustom.HFrontPorch = 48;
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* XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1);
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*/
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Status = XDptx_GetEdid(InstancePtr);
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if (Status == XST_SUCCESS) {
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XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
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XDPTX_VM_640x480_60_P);
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}
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else {
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
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XDPTX_VM_640x480_60_P);
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}
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/* Disable MST for this example. */
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AuxData[0] = 0;
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XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData);
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XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_TX_MST_CONFIG,
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0x0);
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/* Disable main stream to force sending of IDLE patterns. */
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XDptx_DisableMainLink(InstancePtr);
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/* Reset the transmitter. */
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XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET,
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XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
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XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, 0x0);
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/* Configure video stream source or generator here. This function needs
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* to be implemented in order for video to be displayed and is hardware
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* system specific. It is up to the user to implement this function. */
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Dptx_ConfigureVidgen(InstancePtr);
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/*********************************/
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XDptx_EnableMainLink(InstancePtr);
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}
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