582 lines
17 KiB
C
582 lines
17 KiB
C
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/******************************************************************************
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*
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* Copyright (C) 2003 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xhwicap_i.h
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*
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* This head file contains internal identifiers, which are those shared
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* between the files of the driver. It is intended for internal use
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* only.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a bjb 11/14/03 First release
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* 1.00b nps 02/09/05 V4 changes
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* 1.01a tjb 10/14/05 V4 Updates
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* 2.00a sv 10/14/07 V5 Updates
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* 3.01a sv 10/19/09 Corrected the V5 BOOTSTS and CTL_1 Register definitions
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* as they were wrongly defined
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* 4.00a hvm 11/13/09 Updated with V6 changes
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* 5.00a hvm 2/25/10 Added changes to support S6
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* 6.00a hvm 08/01/11 Added support for K7
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* 7.00a bss 03/14/12 Added Virtex 7, Artix 7 and Zynq Device families
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* 8.01a bss 05/14/12 Added the define XHI_COR_1 for CR718042
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* 9.0 bss 02/20/14 Added XHI_DEV_FAMILY_K8 for Kintex 8 devices. #CR764668
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*
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* </pre>
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*
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*****************************************************************************/
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#ifndef XHWICAP_I_H_ /* prevent circular inclusions */
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#define XHWICAP_I_H_ /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files ********************************/
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#include "xhwicap_family.h"
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/************************** Constant Definitions ****************************/
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#define XHI_DEV_FAMILY_V4 2 /* Virtex4 */
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#define XHI_DEV_FAMILY_V5 3 /* Virtex5 */
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#define XHI_DEV_FAMILY_V6 4 /* Virtex6 */
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#define XHI_DEV_FAMILY_S6 5 /* Spartan6 */
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#define XHI_DEV_FAMILY_K7 7 /* Kintex7 */
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#define XHI_DEV_FAMILY_V7 8 /* Virtex7 */
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#define XHI_DEV_FAMILY_A7 9 /* Artix7 */
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#define XHI_DEV_FAMILY_ZYNQ 10 /* Zynq */
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#define XHI_DEV_FAMILY_K8 11 /* Zynq */
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#if ((XHI_FPGA_FAMILY == XHI_DEV_FAMILY_K7) ||\
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(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_A7) ||\
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(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_V7) ||\
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(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_K8) ||\
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(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_ZYNQ))
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#define XHI_DEV_FAMILY_7SERIES 6 /* 7 SERIES */
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#define XHI_FAMILY XHI_DEV_FAMILY_7SERIES
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#else
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#define XHI_FAMILY XHI_FPGA_FAMILY
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#endif
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/**
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* @name Configuration Type1/Type2 packet headers masks
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* @{
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*/
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#define XHI_TYPE_MASK 0x7
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#define XHI_REGISTER_MASK 0x1F
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#define XHI_OP_MASK 0x3
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#if XHI_FAMILY == XHI_DEV_FAMILY_S6
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#define XHI_WORD_COUNT_MASK_TYPE_1 0x1F
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#define XHI_TYPE_SHIFT 13
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#define XHI_REGISTER_SHIFT 5
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#define XHI_OP_SHIFT 11
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#else
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#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FF
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#define XHI_WORD_COUNT_MASK_TYPE_2 0x07FFFFFF
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#define XHI_TYPE_SHIFT 29
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#define XHI_REGISTER_SHIFT 13
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#define XHI_OP_SHIFT 27
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#endif
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#define XHI_TYPE_1 1
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#define XHI_TYPE_2 2
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#define XHI_OP_WRITE 2
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#define XHI_OP_READ 1
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/* @} */
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#if XHI_FAMILY == XHI_DEV_FAMILY_S6
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/*
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* Addresses of the Configuration Registers
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*/
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#define XHI_CRC 0
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#define XHI_FAR_MAJ 1
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#define XHI_FAR_MIN 2
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#define XHI_FDRI 3
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#define XHI_FDRO 4
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#define XHI_CMD 5
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#define XHI_CTL 6
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#define XHI_MASK 7
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#define XHI_STAT 8
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#define XHI_LOUT 9
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#define XHI_COR1 10
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#define XHI_COR2 11
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#define XHI_PWRDN_REG 12
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#define XHI_FLR 13
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#define XHI_IDCODE 14
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#define XHI_CWDT 15
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#define XHI_HC_OPT_REG 16
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#define XHI_CSBO 18
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#define XHI_GENERAL1 19
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#define XHI_GENERAL2 20
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#define XHI_GENERAL3 21
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#define XHI_GENERAL4 22
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#define XHI_GENERAL5 23
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#define XHI_MODE_REG 24
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#define XHI_PU_GWE 25
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#define XHI_PU_GTS 26
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#define XHI_MFWR 27
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#define XHI_CCLK_FREQ 28
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#define XHI_SEU_OPT 29
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#define XHI_EXP_SIGN 30
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#define XHI_RDBK_SIGN 31
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#define XHI_BOOTSTS 32
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#define XHI_EYE_MASK 33
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#define CBC_REG 34
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#define XHI_NUM_REGISTERS 35 /* Note that there is skip at
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* number 17. There is no register
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* at with this number */
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#else
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/*
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* Addresses of the Configuration Registers
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*/
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#define XHI_CRC 0
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#define XHI_FAR 1
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#define XHI_FDRI 2
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#define XHI_FDRO 3
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#define XHI_CMD 4
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#define XHI_CTL 5
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#define XHI_MASK 6
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#define XHI_STAT 7
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#define XHI_LOUT 8
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#define XHI_COR 9
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#define XHI_MFWR 10
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#define XHI_CBC 11
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#define XHI_IDCODE 12
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#define XHI_AXSS 13
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#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
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#define XHI_NUM_REGISTERS 14
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#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
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(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
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/* Virtex5 or Virtex6 or Kintex 7*/
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#define XHI_C0R_1 14
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#define XHI_CSOB 15
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#define XHI_WBSTAR 16
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#define XHI_TIMER 17
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#define XHI_BOOTSTS 22
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#define XHI_CTL_1 24
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#define XHI_NUM_REGISTERS 25 /* Note that the register numbering
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* is not sequential in V5/V6 and
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*there are gaps */
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#define XHI_COR_1 14
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#endif
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#endif
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/**
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* @name Frame Address Register mask(s)
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* @{
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*/
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#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
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#define XHI_FAR_BOTTOM_MASK 0x1
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#define XHI_FAR_BLOCK_MASK 0x7
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#define XHI_FAR_MAJOR_FRAME_MASK 0xFF
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#define XHI_FAR_HCLKROW_MASK 0x1F
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#define XHI_FAR_MINOR_FRAME_MASK 0xFF
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#define XHI_FAR_COLUMN_MASK 0xFF
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#define XHI_FAR_MINOR_MASK 0x3F
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#define XHI_FAR_BOTTOM_SHIFT 22
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#define XHI_FAR_BLOCK_SHIFT 19
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#define XHI_FAR_MAJOR_FRAME_SHIFT 17
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#define XHI_FAR_HCLKROW_SHIFT 14
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#define XHI_FAR_MINOR_FRAME_SHIFT 9
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#define XHI_FAR_COLUMN_SHIFT 6
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#define XHI_FAR_MINOR_SHIFT 0
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/*
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* Address Block Types in the Frame Address Register
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*/
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#define XHI_FAR_CLB_BLOCK 0 /**< CLB/IO/CLK Block */
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#define XHI_FAR_BRAM_BLOCK 1 /**< Block RAM interconnect */
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#define XHI_FAR_BRAM_INT_BLOCK 2 /**< Block RAM content */
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#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
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(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
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/* Virtex5 or Virtex6 */
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#define XHI_FAR_BLOCK_MASK 0x7
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#define XHI_FAR_TOP_BOTTOM_MASK 0x1
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#define XHI_FAR_MAJOR_FRAME_MASK 0xFF
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#define XHI_FAR_ROW_ADDR_MASK 0x1F
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#define XHI_FAR_MINOR_FRAME_MASK 0xFF
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#define XHI_FAR_COLUMN_ADDR_MASK 0xFF
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#define XHI_FAR_MINOR_ADDR_MASK 0x7F
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#define XHI_FAR_BLOCK_SHIFT 21
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#define XHI_FAR_TOP_BOTTOM_SHIFT 20
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#define XHI_FAR_MAJOR_FRAME_SHIFT 17
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#define XHI_FAR_ROW_ADDR_SHIFT 15
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#define XHI_FAR_MINOR_FRAME_SHIFT 9
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#define XHI_FAR_COLUMN_ADDR_SHIFT 7
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#define XHI_FAR_MINOR_ADDR_SHIFT 0
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/*
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* Address Block Types in the Frame Address Register
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*/
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#define XHI_FAR_CLB_BLOCK 0 /**< CLB/IO/CLK Block */
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#define XHI_FAR_BRAM_BLOCK 1 /**< Block RAM interconnect */
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#endif
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/* @} */
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/*
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* Configuration Commands
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*/
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#define XHI_CMD_NULL 0
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#define XHI_CMD_WCFG 1
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#define XHI_CMD_MFW 2
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#if XHI_FAMILY == XHI_DEV_FAMILY_S6
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#define XHI_CMD_LFRM 3
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#else
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#define XHI_CMD_DGHIGH 3
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#endif
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#define XHI_CMD_RCFG 4
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#define XHI_CMD_START 5
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#define XHI_CMD_RCAP 6
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#define XHI_CMD_RCRC 7
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#define XHI_CMD_AGHIGH 8
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#define XHI_CMD_SWITCH 9
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#define XHI_CMD_GRESTORE 10
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#define XHI_CMD_SHUTDOWN 11
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#if (XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5) || \
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(XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
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#define XHI_CMD_GCAPTURE 12
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#endif
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#define XHI_CMD_DESYNCH 13
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#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
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#define XHI_CMD_IPROG 14
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#endif
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#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
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(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
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/* Virtex5 or Virtex6 */
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#define XHI_CMD_IPROG 15
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#define XHI_CMD_CRCC 16
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#define XHI_CMD_LTIMER 17
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#endif
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#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
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(XHI_OP_READ << XHI_OP_SHIFT))
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#define XHI_TYPE_2_WRITE ( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
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(XHI_OP_WRITE << XHI_OP_SHIFT) )
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#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
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#define XHI_SYNC_PACKET1 0xAA99
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#define XHI_SYNC_PACKET2 0x5566
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#define XHI_DUMMY_PACKET 0xFFFF
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#define XHI_NOOP_PACKET 0x2000
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#define XHI_TYPE1_WRITE (XHI_TYPE_1 << XHI_TYPE_SHIFT) | \
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((XHI_OP_WRITE << XHI_OP_SHIFT))
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#define XHI_TYPE2_CNT_MASK 0x07FFFFFF
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#define XHI_TYPE_1_PACKET_MAX_WORDS 32
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#define XHI_DEVICE_ID_READ 0x29C2
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#define XHI_BLOCK_SHIFT 12
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#define XHI_ROW_SHIFT 8
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#define XHI_COR1_DEFAULT 0x3d10
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#define XHI_COR2_DEFAULT 0x9EE
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#else
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/*
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||
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* Packet constants
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||
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*/
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||
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#define XHI_SYNC_PACKET 0xAA995566
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||
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#define XHI_DUMMY_PACKET 0xFFFFFFFF
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#define XHI_DEVICE_ID_READ 0x28018001
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||
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#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
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||
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|
||
|
|
#define XHI_TYPE_1_PACKET_MAX_WORDS 2047
|
||
|
|
#define XHI_TYPE_1_HEADER_BYTES 4
|
||
|
|
#define XHI_TYPE_2_HEADER_BYTES 8
|
||
|
|
|
||
|
|
|
||
|
|
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
|
||
|
|
#define XHI_NUM_FRAME_BYTES 164 /* Number of bytes in a frame */
|
||
|
|
#define XHI_NUM_FRAME_WORDS 41 /* Number of Words in a frame */
|
||
|
|
#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME 83 /* Num of Words in a frame read
|
||
|
|
* from the device including
|
||
|
|
* the NULL frame and an extra
|
||
|
|
* 32 bit word
|
||
|
|
*/
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Virtex6 or 7 SERIES */
|
||
|
|
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
|
||
|
|
#define XHI_NUM_FRAME_BYTES 324 /* Number of bytes in a frame */
|
||
|
|
#define XHI_NUM_FRAME_WORDS 81 /* Number of Words in a frame */
|
||
|
|
#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME 162 /* Num of Words in a frame read
|
||
|
|
* from the device including
|
||
|
|
* the NULL frame
|
||
|
|
*/
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#if XHI_FAMILY == XHI_DEV_FAMILY_S6 /* Spartan6 */
|
||
|
|
#define XHI_NUM_FRAME_BYTES 130 /* Number of bytes in a frame */
|
||
|
|
#define XHI_NUM_FRAME_WORDS 65 /* Number of Words in a frame */
|
||
|
|
#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME 131 /* Num of Words in a frame read
|
||
|
|
* from the device including
|
||
|
|
* the NULL frame
|
||
|
|
*/
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
|
||
|
|
|
||
|
|
#define XHI_GCLK_FRAMES 3
|
||
|
|
#define XHI_IOB_FRAMES 30
|
||
|
|
#define XHI_DSP_FRAMES 21
|
||
|
|
#define XHI_CLB_FRAMES 22
|
||
|
|
#define XHI_BRAM_FRAMES 64
|
||
|
|
#define XHI_BRAM_INT_FRAMES 20
|
||
|
|
|
||
|
|
#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5 */
|
||
|
|
|
||
|
|
#define XHI_GCLK_FRAMES 4
|
||
|
|
#define XHI_IOB_FRAMES 54
|
||
|
|
#define XHI_DSP_FRAMES 28
|
||
|
|
#define XHI_CLB_FRAMES 36
|
||
|
|
#define XHI_BRAM_FRAMES 64
|
||
|
|
#define XHI_BRAM_INT_FRAMES 30
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/* Device Resources */
|
||
|
|
#define CLB 0
|
||
|
|
#define DSP 1
|
||
|
|
#define BRAM 2
|
||
|
|
#define BRAM_INT 3
|
||
|
|
#define IOB 4
|
||
|
|
#define IOI 5
|
||
|
|
#define CLK 6
|
||
|
|
#define MGT 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The number of words reserved for the header
|
||
|
|
*/
|
||
|
|
#define XHI_HEADER_BUFFER_WORDS 20
|
||
|
|
#define XHI_HEADER_BUFFER_BYTES (XHI_HEADER_BUFFER_WORDS << 2)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* CLB major frames start at 3 for the first column (since we are using
|
||
|
|
* column numbers that start at 1, when the column is added to this offset,
|
||
|
|
* that first one will be 3 as required.
|
||
|
|
*/
|
||
|
|
#define XHI_CLB_MAJOR_FRAME_OFFSET 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Constant to use for CRC check when CRC has been disabled
|
||
|
|
*/
|
||
|
|
#define XHI_DISABLED_AUTO_CRC 0x0000DEFC
|
||
|
|
#define XHI_DISABLED_AUTO_CRC_ONE 0x9876
|
||
|
|
#define XHI_DISABLED_AUTO_CRC_TWO 0xDEFC
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Major Row Offset
|
||
|
|
*/
|
||
|
|
#define XHI_CLB_MAJOR_ROW_OFFSET 96+(32*XHI_HEADER_BUFFER_WORDS)-1
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Number of times to poll the Status Register
|
||
|
|
*/
|
||
|
|
#define XHI_MAX_RETRIES 1000
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Mask for the Device ID read from the ID code Register
|
||
|
|
*/
|
||
|
|
#define XHI_DEVICE_ID_CODE_MASK 0x0FFFFFFF
|
||
|
|
|
||
|
|
|
||
|
|
/**************************** Type Definitions *******************************/
|
||
|
|
|
||
|
|
|
||
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 1 packet header that reads back the requested Configuration
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param Register is the address of the register to be read back.
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to read the specified register
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_Type1Read(Register) \
|
||
|
|
( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
|
||
|
|
(XHI_OP_READ << XHI_OP_SHIFT) )
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 2 packet header that reads back the requested Configuration
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param Register is the address of the register to be read back.
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to read the specified register
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_Type2Read(Register) \
|
||
|
|
( XHI_TYPE_2_READ | (Register << XHI_REGISTER_SHIFT))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 1 packet header that writes to the requested Configuration
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param Register is the address of the register to be written to.
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to write the specified register
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_Type1Write(Register) \
|
||
|
|
( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
|
||
|
|
(XHI_OP_WRITE << XHI_OP_SHIFT) )
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 2 packet header that writes to the requested Configuration
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param Register is the address of the register to be written to.
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to write the specified register
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_Type2Write(Register) \
|
||
|
|
( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
|
||
|
|
(XHI_OP_WRITE << XHI_OP_SHIFT) )
|
||
|
|
|
||
|
|
#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 1 packet header that is written to the Frame Address
|
||
|
|
* Register (FAR) for a Virtex4 device.
|
||
|
|
*
|
||
|
|
* @param Top - top (0) or bottom (1) half of device
|
||
|
|
* @param Block - Address Block Type (CLB or BRAM address space)
|
||
|
|
* @param HClkRow - H Clock row
|
||
|
|
* @param MajorAddress - CLB or BRAM column
|
||
|
|
* @param MinorAdderss - Frame within column
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to write the FAR
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_SetupFarV4(Top, Block, HClkRow, MajorAddress, MinorAddress) \
|
||
|
|
((Top << XHI_FAR_BOTTOM_SHIFT) | \
|
||
|
|
(Block << XHI_FAR_BLOCK_SHIFT) | \
|
||
|
|
(HClkRow << XHI_FAR_HCLKROW_SHIFT) | \
|
||
|
|
(MajorAddress << XHI_FAR_COLUMN_SHIFT) | \
|
||
|
|
(MinorAddress << XHI_FAR_MINOR_SHIFT))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
|
||
|
|
(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Generates a Type 1 packet header that is written to the Frame Address
|
||
|
|
* Register (FAR) for a Virtex5 device.
|
||
|
|
*
|
||
|
|
* @param Block - Address Block Type (CLB or BRAM address space)
|
||
|
|
* @param Top - top (0) or bottom (1) half of device
|
||
|
|
* @param Row - Row Address
|
||
|
|
* @param ColumnAddress - CLB or BRAM column
|
||
|
|
* @param MinorAddress - Frame within a column
|
||
|
|
*
|
||
|
|
* @return Type 1 packet header to write the FAR
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XHwIcap_SetupFarV5(Top, Block, Row, ColumnAddress, MinorAddress) \
|
||
|
|
(Block << XHI_FAR_BLOCK_SHIFT) | \
|
||
|
|
((Top << XHI_FAR_TOP_BOTTOM_SHIFT) | \
|
||
|
|
(Row << XHI_FAR_ROW_ADDR_SHIFT) | \
|
||
|
|
(ColumnAddress << XHI_FAR_COLUMN_ADDR_SHIFT) | \
|
||
|
|
(MinorAddress << XHI_FAR_MINOR_ADDR_SHIFT))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/************************** Function Prototypes ******************************/
|
||
|
|
|
||
|
|
|
||
|
|
/************************** Variable Definitions ****************************/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|