<h1>hwicap v10_0</h1><p>The Xilinx <aclass="el"href="struct_x_hw_icap.html">XHwIcap</a> driver supports the Xilinx Hardware Internal Configuration Access Port (HWICAP) device.</p>
<p>The HWICAP device is used for reconfiguration of select FPGA resources as well as loading partial bitstreams from the system memory through the Internal Configuration Access Port (ICAP).</p>
<p>The source code for the XHwIcap_SetClbBits and XHwIcap_GetClbBits functions are not included. These functions are delivered as .o files. These files have been compiled using gcc version 4.1.1. Libgen uses the appropriate .o files for the target processor.</p>
<p><b> Initialization and Configuration </b></p>
<p>The device driver enables higher layer software (e.g., an application) to communicate to the HWICAP device.</p>
<p><aclass="el"href="xhwicap_8c.html#a928bb0618a3f4bab3264eceb7b898d6d">XHwIcap_CfgInitialize()</a> API is used to initialize the HWICAP device. The user needs to first call the <aclass="el"href="xhwicap_8h.html#a8966aa32e3b990dc44e6cfcbdfbf2f2d">XHwIcap_LookupConfig()</a> API which returns the Configuration structure pointer which is passed as a parameter to the <aclass="el"href="xhwicap_8c.html#a928bb0618a3f4bab3264eceb7b898d6d">XHwIcap_CfgInitialize()</a> API.</p>
<p><b> Interrupts </b></p>
<p>The driver provides an interrupt handler XHwIcap_IntrHandler for handling the interrupt from the HWICAP device. The users of this driver have to register this handler with the interrupt system and provide the callback functions. The callback functions are invoked by the interrupt handler based on the interrupt source.</p>
<p>The driver supports interrupt mode only for writing to the ICAP device and is NOT supported for reading from the ICAP device.</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
<p><b> Building the driver </b></p>
<p>The <aclass="el"href="struct_x_hw_icap.html">XHwIcap</a> driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
<p>There are a few items to be aware of when using this driver: 1) Only Virtex4, Virtex5, Virtex6, Spartan6, 7 series and Zynq devices are supported. 2) The ICAP port is disabled when the configuration mode, via the MODE pins, is set to Boundary Scan/JTAG. The ICAP is enabled in all other configuration modes and it is possible to configure the device via JTAG in all configuration modes. 3) Reading or writing to columns containing SRL16's or LUT RAM's can cause corruption of data in those elements. Avoid reading or writing to columns containing SRL16's or LUT RAM's. 4) Only the LUT and SRL are accesible, all other features of the slice are not available through this interface. 5) The Spartan6 devices access is 16-bit access and is 32 bit for all other devices. 6) In a Zynq device the ICAP needs to be selected using the XDcfg_SelectIcapInterface API of the DevCfg driver (clear the PCAP_PR bit of Control register in the Device Config Interface) before it can be accessed using the HwIcap.</p>
