<tr><tdclass="memItemLeft"align="right"valign="top">int </td><tdclass="memItemRight"valign="bottom"><aclass="el"href="xadcps_8c.html#ac586b30d9704eecc92119c437430d3ef">XAdcPs_SetSingleChParams</a> (<aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> *InstancePtr, u8 Channel, int IncreaseAcqCycles, int IsEventMode, int IsDifferentialMode)</td></tr>
<tr><tdclass="memItemLeft"align="right"valign="top">void </td><tdclass="memItemRight"valign="bottom"><aclass="el"href="xadcps_8c.html#a25ad16579977f4b366c57c5b0bdd8b65">XAdcPs_SetSequencerEvent</a> (<aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> *InstancePtr, int IsEventMode)</td></tr>
<p>This function initializes a specific <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> device/instance. This function must be called prior to using the XADC device.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>ConfigPtr</em> </td><td>points to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> device configuration structure. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>EffectiveAddr</em> </td><td>is the device base address in the virtual memory address space. If the address translation is not used then the physical address is passed. Unexpected errors may occur if the address mapping is changed after this function is invoked.</td></tr>
<dlclass="note"><dt><b>Note:</b></dt><dd>The user needs to first call the <aclass="el"href="xadcps_8h.html#ae1c891154549887e7e99466fe0c90656">XAdcPs_LookupConfig()</a> API which returns the Configuration structure pointer which is passed as a parameter to the <aclass="el"href="xadcps_8c.html#a57807452402a6b52dd48083f676bd4ff">XAdcPs_CfgInitialize()</a> API. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>The divisor read from the Configuration Register 2.</dd></dl>
<dlclass="note"><dt><b>Note:</b></dt><dd>The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Channel</em> </td><td>is the channel number. Use the XADCPS_CH_* defined in the file <aclass="el"href="xadcps_8h.html">xadcps.h</a>. The valid channels are</p>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 16-bit value representing the ADC converted data for the specified channel. The XADC Monitor/ADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.</dd></dl>
<dlclass="note"><dt><b>Note:</b></dt><dd>The channels 7,8,9 are used for calibration of the device and hence there is no associated data with this channel. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>This is the bit-mask of the enabled alarm outputs in the Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and XADCPS_CFR1_OT_MASK defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the returned value. Bit positions of 1 indicate that the alarm output is enabled. Bit positions of 0 indicate that the alarm output is disabled.</dd></dl>
<dlclass="note"><dt><b>Note:</b></dt><dd>The implementation of the alarm enables in the Configuration register 1 is such that alarms for the bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The enabled alarm outputs returned by this function is the negated value of the the data read from the Configuration Register 1. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>AlarmThrReg</em> </td><td>is the index of an Alarm Threshold Register to be read. Use XADCPS_ATR_* constants defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to specify the index.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>The averaging read from the Configuration Register 0 is returned. Use the XADCPS_AVG_* bit definitions defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> file to interpret the returned value :<ul>
<li>XADCPS_AVG_0_SAMPLES means no averaging</li>
<li>XADCPS_AVG_16_SAMPLES means 16 samples of averaging</li>
<li>XADCPS_AVG_64_SAMPLES means 64 samples of averaging</li>
<li>XADCPS_AVG_256_SAMPLES means 256 samples of averaging</li>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>CoeffType</em> </td><td>specifies the calibration coefficient to be read. Use XADCPS_CALIB_* constants defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> to specify the calibration coefficient to be read.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 16-bit value representing the calibration coefficient. The XADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 32-bit value representing the contents of the Config Register. Use the XADCPS_SR_*_MASK constants defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the returned value.</dd></dl>
<p>This function reads the Minimum/Maximum measurement for one of the specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> to specify the parameters (Temperature, VccInt, VccAux, VBram, VccPInt, VccPAux and VccPDro).</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>MeasurementType</em> </td><td>specifies the parameter for which the Minimum/Maximum measurement has to be read. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> to specify the data to be read.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 16-bit value representing the maximum/minimum measurement for specified parameter. The XADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 32-bit value representing the contents of the Config Register. Use the XADCPS_SR_*_MASK constants defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the returned value.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>A 32-bit value representing the contents of the Miscellaneous Status Register. Use the XADCPS_MSTS_*_MASK constants defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the returned value.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>The acquisition time for all the channels. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the Channel numbers. Bit masks of 1 are the channels for which acquisition cycles are extended and bit mask of 0 are the channels for which acquisition cycles are not extended.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>The status of averaging (enabled/disabled) for all the channels. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the Channel numbers. Bit masks of 1 are the channels for which averaging is enabled and bit mask of 0 are the channels for averaging is disabled</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the Channel numbers. Bit masks of 1 are the channels that are enabled and bit mask of 0 are the channels that are disabled.</dd>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<dlclass="return"><dt><b>Returns:</b></dt><dd>The input mode for all the channels. Use XADCPS_SEQ_CH_* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to interpret the Channel numbers. Bit masks of 1 are the channels for which input mode is differential and bit mask of 0 are the channels for which input mode is unipolar.</dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>RegOffset</em> </td><td>is the offset of the XADC register to be read.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Divisor</em> </td><td>is clock divisor used to derive ADCCLK from DCLK. Valid values of the divisor are</p>
<ul>
<li>0 to 255. Values 0, 1, 2 are all mapped to 2. Refer to the device specification for more details</li>
<dlclass="note"><dt><b>Note:</b></dt><dd>- The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2.<ul>
<li>There is no Assert on the minimum value of the Divisor. </li>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>AlmEnableMask</em> </td><td>is the bit-mask of the alarm outputs to be enabled in the Configuration Register 1. Bit positions of 1 will be enabled. Bit positions of 0 will be disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and XADCPS_CFR1_OT_MASK masks defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a>.</td></tr>
<dlclass="note"><dt><b>Note:</b></dt><dd>The implementation of the alarm enables in the Configuration register 1 is such that the alarms for bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The alarm outputs specified by the AlmEnableMask are negated before writing to the Configuration Register 1. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>AlarmThrReg</em> </td><td>is the index of an Alarm Threshold Register to be set. Use XADCPS_ATR_* constants defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> to specify the index. </td></tr>
<p>This function sets the number of samples of averaging that is to be done for all the channels in both the single channel mode and sequence mode of operations.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Average</em> </td><td>is the number of samples of averaging programmed to the Configuration Register 0. Use the XADCPS_AVG_* definitions defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a> file :</p>
<ul>
<li>XADCPS_AVG_0_SAMPLES for no averaging</li>
<li>XADCPS_AVG_16_SAMPLES for 16 samples of averaging</li>
<li>XADCPS_AVG_64_SAMPLES for 64 samples of averaging</li>
<li>XADCPS_AVG_256_SAMPLES for 256 samples of averaging</li>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Calibration</em> </td><td>is the Calibration to be applied. Use XADCPS_CFR1_CAL*_* bits defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a>. Multiple calibrations can be enabled at a time by oring the XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits. Calibration can be disabled by specifying XADCPS_CFR1_CAL_DISABLE_MASK;</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Data</em> </td><td>is the 32 bit data to be written to the Register.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Data</em> </td><td>is the 32 bit data to be written to the Register.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Channel</em> </td><td>specifies the channel to be used for the external Mux. Please read the Device Spec for which channels are valid for which mode.</td></tr>
<dlclass="note"><dt><b>Note:</b></dt><dd>There is no Assert in this function for checking the channel number if the external Mux is used. The user should provide a valid channel number. </dd></dl>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<p>This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers. The sequencer must be disabled before writing to these regsiters.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>AcqCyclesChMask</em> </td><td>is the bit mask of all the channels for which the number of acquisition cycles is to be extended. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to specify the Channel numbers. Acquisition cycles will be extended to 10 ADCCLK cycles for bit masks of 1 and will be the default 4 ADCCLK cycles for bit masks of 0. The AcqCyclesChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Acquisition Time Sequencer Registers.</td></tr>
<p>This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers. The sequencer must be disabled before writing to these regsiters.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>AvgEnableChMask</em> </td><td>is the bit mask of all the channels for which averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to specify the Channel numbers. Averaging will be enabled for bit masks of 1 and disabled for bit mask of 0. The AvgEnableChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Averaging Enable Sequencer Registers.</td></tr>
<p>This function enables the specified channels in the ADC Channel Selection Sequencer Registers. The sequencer must be disabled before writing to these regsiters.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>ChEnableMask</em> </td><td>is the bit mask of all the channels to be enabled. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to specify the Channel numbers. Bit masks of 1 will be enabled and bit mask of 0 will be disabled. The ChEnableMask is a 32 bit mask that is written to the two 16 bit ADC Channel Selection Sequencer Registers.</td></tr>
<p>This function sets the Analog input mode for the specified channels in the ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled before writing to these regsiters.</p>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InputModeChMask</em> </td><td>is the bit mask of all the channels for which the input mode is differential mode. Use XADCPS_SEQ_CH__* defined in <aclass="el"href="xadcps__hw_8h.html">xadcps_hw.h</a> to specify the channel numbers. Differential input mode will be set for bit masks of 1 and unipolar input mode for bit masks of 0. The InputModeChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Analog-Input Mode Sequencer Registers.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>IsEventMode</em> </td><td>is a boolean parameter that specifies continuous sampling (specify FALSE) or event driven sampling mode (specify TRUE) for the given channel.</td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>SequencerMode</em> </td><td>is the sequencer mode to be set. Use XADCPS_SEQ_MODE_* bits defined in <aclass="el"href="xadcps_8h.html">xadcps.h</a>. </td></tr>
<dlclass="note"><dt><b>Note:</b></dt><dd>Only one of the modes can be enabled at a time. Please read the Spec of the XADC for further information about the sequencer modes. </dd></dl>
</div>
</div>
<aclass="anchor"id="ac586b30d9704eecc92119c437430d3ef"></a><!-- doxytag: member="xadcps.c::XAdcPs_SetSingleChParams" ref="ac586b30d9704eecc92119c437430d3ef" args="(XAdcPs *InstancePtr, u8 Channel, int IncreaseAcqCycles, int IsEventMode, int IsDifferentialMode)" -->
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Channel</em> </td><td>is the channel number for the singel channel mode. The valid channels are 0 to 6, 8, and 13 to 31. If the external Mux is used then this specifies the channel oonnected to the external Mux. Please read the Device Spec to know which channels are valid. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>IncreaseAcqCycles</em> </td><td>is a boolean parameter which specifies whether the Acquisition time for the external channels has to be increased to 10 ADCCLK cycles (specify TRUE) or remain at the default 4 ADCCLK cycles (specify FALSE). This parameter is only valid for the external channels. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>IsDifferentialMode</em> </td><td>is a boolean parameter which specifies unipolar(specify FALSE) or differential mode (specify TRUE) for the analog inputs. The input mode is only valid for the external channels.</td></tr>
<li>The number of samples for the averaging for all the channels is set by using the function XAdcPs_SetAvg.</li>
<li>The calibration of the device is done by doing a ADC conversion on the calibration channel(channel 8). The input parameters IncreaseAcqCycles, IsDifferentialMode and IsEventMode are not valid for this channel </li>
<tr><tdvalign="top"></td><tdvalign="top"><em>InstancePtr</em> </td><td>is a pointer to the <aclass="el"href="struct_x_adc_ps.html">XAdcPs</a> instance. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>RegOffset</em> </td><td>is the offset of the XADC register to be written. </td></tr>
<tr><tdvalign="top"></td><tdvalign="top"><em>Data</em> </td><td>is the data to be written.</td></tr>
