2014-06-24 16:45:01 +05:30
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/******************************************************************************
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*
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2015-01-08 18:30:20 +05:30
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* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
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2014-06-24 16:45:01 +05:30
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic.h
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*
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* XIic is the driver for an IIC master or slave device.
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*
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* In order to reduce the memory requirements of the driver the driver is
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* partitioned such that there are optional parts of the driver.
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* Slave, master, and multimaster features are optional such that all these files
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* are not required at the same time.
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* In order to use the slave and multimaster features of the driver, the user
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* must call functions (XIic_SlaveInclude and XIic_MultiMasterInclude)
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* to dynamically include the code. These functions may be called at any time.
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*
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* Two sets of higher level API's are available in the XIic driver that can
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* be used for Transmission/Reception in Master mode :
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* - XIic_MasterSend()/ XIic_MasterRecv() which is used in normal mode.
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* - XIic_DynMasterSend()/ XIic_DynMasterRecv() which is used in Dynamic mode.
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*
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* Similarly two sets of lower level API's are available in XIic driver that
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* can be used for Transmission/Reception in Master mode:
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* - XIic_Send()/ XIic_Recv() which is used in normal mode
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* - XIic_DynSend()/ XIic_DynRecv() which is used in Dynamic mode.
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*
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* The user should use a single set of APIs as per his requirement and
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* should not intermix them.
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*
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* All the driver APIs can be used for read, write and combined mode of
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* operations on the IIC bus.
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*
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* In the normal mode IIC support both 7-bit and 10-bit addressing, and in
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* the dynamic mode support only 7-bit addressing.
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*
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* <b>Initialization & Configuration</b>
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*
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* The XIic_Config structure is used by the driver to configure itself. This
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* configuration structure is typically created by the tool-chain based on HW
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* build properties.
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*
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* To support multiple runtime loading and initialization strategies employed
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* by various operating systems, the driver instance can be initialized in one
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* of the following ways:
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*
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* - XIic_Initialize() - The driver looks up its own
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* configuration structure created by the tool-chain based on an ID provided
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* by the tool-chain.
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*
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* - XIic_CfgInitialize() - The driver uses a configuration structure provided
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* by the caller. If running in a system with address translation, the
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* provided virtual memory base address replaces the physical address present
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* in the configuration structure.
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*
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* <b>General Purpose Output</b>
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* The IIC hardware provides a General Purpose Output Register that allows the
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* user to connect general purpose outputs to devices, such as a write protect,
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* for an EEPROM. This register is parameterizable in the hardware such that
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* there could be zero bits in this register and in this case it will cause
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* a bus error if read or written.
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*
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* <b>Bus Throttling</b>
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*
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* The IIC hardware provides bus throttling which allows either the device, as
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* either a master or a slave, to stop the clock on the IIC bus. This feature
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* allows the software to perform the appropriate processing for each interrupt
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* without an unreasonable response restriction. With this design, it is
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* important for the user to understand the implications of bus throttling.
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*
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* <b>Repeated Start</b>
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*
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* An application can send multiple messages, as a master, to a slave device
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* and re-acquire the IIC bus each time a message is sent. The repeated start
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* option allows the application to send multiple messages without re-acquiring
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* the IIC bus for each message. The transactions involving repeated start
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* are also called combined transfers if there is Read and Write in the
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* same transaction.
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*
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* The repeated start feature works with all the API's in XIic driver.
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*
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* The Repeated Start feature also could cause the application to lock up, or
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* monopolize the IIC bus, should repeated start option be enabled and sequences
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* of messages never end(periodic data collection).
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* Also when repeated start is not disable before the last master message is
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* sent or received, will leave the bus captive to the master, but unused.
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*
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* <b>Addressing</b>
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*
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* The IIC hardware is parameterized such that it can be built for 7 or 10
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* bit addresses. The driver provides the ability to control which address
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* size is sent in messages as a master to a slave device. The address size
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* which the hardware responds to as a slave is parameterized as 7 or 10 bits
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* but fixed by the hardware build.
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*
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* Addresses are represented as hex values with no adjustment for the data
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* direction bit as the software manages address bit placement. This is
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* especially important as the bit placement is not handled the same depending
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* on which options are used such as repeated start and 7 vs 10 bit addessing.
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*
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* <b>Data Rates</b>
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*
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* The IIC hardware is parameterized such that it can be built to support
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* data rates from DC to 400KBit. The frequency of the interrupts which
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* occur is proportional to the data rate.
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*
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* <b>Polled Mode Operation</b>
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*
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* This driver does not provide a polled mode of operation primarily because
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* polled mode which is non-blocking is difficult with the amount of
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* interaction with the hardware that is necessary.
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*
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* <b>Interrupts</b>
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*
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* The device has many interrupts which allow IIC data transactions as well
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* as bus status processing to occur.
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*
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* The interrupts are divided into two types, data and status. Data interrupts
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* indicate data has been received or transmitted while the status interrupts
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* indicate the status of the IIC bus. Some of the interrupts, such as Not
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* Addressed As Slave and Bus Not Busy, are only used when these specific
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* events must be recognized as opposed to being enabled at all times.
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*
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* Many of the interrupts are not a single event in that they are continuously
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* present such that they must be disabled after recognition or when undesired.
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* Some of these interrupts, which are data related, may be acknowledged by the
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* software by reading or writing data to the appropriate register, or must
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* be disabled. The following interrupts can be continuous rather than single
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* events.
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* - Data Transmit Register Empty/Transmit FIFO Empty
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* - Data Receive Register Full/Receive FIFO
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* - Transmit FIFO Half Empty
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* - Bus Not Busy
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* - Addressed As Slave
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* - Not Addressed As Slave
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*
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* The following interrupts are not passed directly to the application thru the
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* status callback. These are only used internally for the driver processing
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* and may result in the receive and send handlers being called to indicate
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* completion of an operation. The following interrupts are data related
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* rather than status.
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* - Data Transmit Register Empty/Transmit FIFO Empty
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* - Data Receive Register Full/Receive FIFO
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* - Transmit FIFO Half Empty
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* - Slave Transmit Complete
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*
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* <b>Interrupt To Event Mapping</b>
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*
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* The following table provides a mapping of the interrupts to the events which
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* are passed to the status handler and the intended role (master or slave) for
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* the event. Some interrupts can cause multiple events which are combined
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* together into a single status event such as XII_MASTER_WRITE_EVENT and
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* XII_GENERAL_CALL_EVENT
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* <pre>
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* Interrupt Event(s) Role
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*
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* Arbitration Lost Interrupt XII_ARB_LOST_EVENT Master
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* Transmit Error XII_SLAVE_NO_ACK_EVENT Master
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* IIC Bus Not Busy XII_BUS_NOT_BUSY_EVENT Master
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* Addressed As Slave XII_MASTER_READ_EVENT, Slave
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* XII_MASTER_WRITE_EVENT, Slave
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* XII_GENERAL_CALL_EVENT Slave
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* </pre>
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* <b>Not Addressed As Slave Interrupt</b>
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*
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* The Not Addressed As Slave interrupt is not passed directly to the
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* application thru the status callback. It is used to determine the end of
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* a message being received by a slave when there was no stop condition
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* (repeated start). It will cause the receive handler to be called to
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* indicate completion of the operation.
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*
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* <b>RTOS Independence</b>
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*
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* This driver is intended to be RTOS and processor independent. It works
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* with physical addresses only. Any needs for dynamic memory management,
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* threads or thread mutual exclusion, virtual memory, or cache control must
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* be satisfied by the layer above this driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.01a rfp 10/19/01 release
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* 1.01c ecm 12/05/02 new rev
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* 1.01d jhl 10/08/03 Added general purpose output feature
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* 1.01d sv 05/09/05 Changed the data being written to the Address/Control
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* Register and removed the code for testing the
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* Receive Data Register in XIic_SelfTest function of
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* xiic_selftest.c source file
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* 1.02a jvb 12/14/05 I separated dependency on the static config table and
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* xparameters.h from the driver initialization by moving
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* _Initialize and _LookupConfig to _sinit.c. I also added
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* the new _CfgInitialize routine.
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* 1.02a mta 03/09/06 Added a new function XIic_IsIicBusy() which returns
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* whether IIC Bus is Busy or Free.
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* 1.02a mta 03/09/06 Implemented Repeated Start in the Low Level Driver.
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* 1.03a mta 07/17/06 Added files to support Dynamic IIC controller in High
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* level driver. Added xiic_dyn_master.c. Added support
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* for IIC Dynamic controller in Low level driver in xiic_l.c
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* 1.13a wgr 03/22/07 Converted to new coding style.
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* 1.13b ecm 11/29/07 added BB polling loops to the DynSend and DynRecv
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* routines to handle the race condition with BNB in IISR.
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* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
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* file
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* 1.14a ecm 11/13/08 changed BB polling loops in DynRecv to handle race
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* condition, CR491889. DynSend was correct from v1.13.b
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* 1.15a ktn 02/17/09 Fixed XIic_GetAddress() to return correct device address.
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* 1.16a ktn 07/17/09 Updated the XIic_SelfTest() to test only Interrupt
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* Registers.
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* 2.00a ktn 10/22/09 Converted all register accesses to 32 bit access.,
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* Removed the macro XIIC_RESET, XIic_Reset API should be
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* used in its place.
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* Removed the XIIC_CLEAR_STATS macro, XIic_ClearStats API
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* should be used in its place.
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* Removed the macro XIic_mEnterCriticalRegion,
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* XIic_IntrGlobalDisable should be used in its place.
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* Removed the macro XIic_mExitCriticalRegion,
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* XIic_IntrGlobalEnable should be used in its place.
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* Some of the macros have been renamed to remove _m from
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* the name see the xiic_i.h and xiic_l.h file for further
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* information (Example XIic_mClearIntr is now
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* XIic_ClearIntr).
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* Some of the macros have been renamed to be consistent,
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* see the xiic_l.h file for further information
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* (Example XIIC_WRITE_IIER is renamed as XIic_WriteIier).
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* The driver has been updated to use the HAL APIs/macros
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* (Example XASSERT_NONVOID is now Xil_AssertNonvoid)
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* 2.01a ktn 04/09/10 Updated TxErrorhandler in xiic_intr.c to be called for
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* Master Transmitter case based on Addressed As Slave (AAS)
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* bit rather than MSMS bit(CR 540199).
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* 2.02a sdm 10/08/10 Updated to disable the device at the end of the transfer,
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* using Addressed As Slave (AAS) bit when addressed as
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* slave in XIic_Send for CR565373.
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* 2.03a rkv 01/25/11 Updated in NAAS interrupt handler to support data
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* recieved less than FIFO size prior to NAAS interrupt.
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* Fixed for CR590212.
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* 2.04a sdm 07/22/11 Added IsSlaveSetAckOff flag to the instance structure.
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* This flag is set when the Slave has set the Ack Off in the
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* RecvSlaveData function (xiic_slave.c) and
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* is cleared in the NotAddrAsSlaveHandler (xiic_slave.c)
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* when the master has released the bus. This flag is
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* to be used by slave applications for recovering when it
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* has gone out of sync with the master for CR 615004.
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* Removed a compiler warning in XIic_Send (xiic_l.c)
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* 2.05a bss 02/05/12 Assigned RecvBufferPtr in XIic_MasterSend API and
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* SendBufferPtr in XIic_MasterRecv to NULL in xiic_master.c
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* 2.06a bss 02/14/13 Modified TxErrorHandler in xiic_intr.c to fix CR #686483
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* Modified xiic_eeprom_example.c to fix CR# 683509.
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* Modified bitwise OR to logical OR in
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* XIic_InterruptHandler API in xiic_intr.c.
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* 2.07a adk 18/04/13 Updated the code to avoid unused variable warnings
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* when compiling with the -Wextra -Wall flags.
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|
|
|
* Changes done in files xiic.c and xiic_i.h. CR:705001
|
|
|
|
|
* 2.08a adk 29/07/13 In Low level driver In repeated start condition the
|
|
|
|
|
* Direction of Tx bit must be disabled in recv condition
|
|
|
|
|
* It Fixes the CR:685759 Changes are done in the file
|
|
|
|
|
* xiic_l.c in the function XIic_Recv.
|
|
|
|
|
* 3.0 adk 19/12/13 Updated as per the New Tcl API's
|
2015-01-08 18:30:19 +05:30
|
|
|
* 3.1 adk 01/08/15 When configured as a slave return the actual number of
|
|
|
|
|
* bytes have been received/sent by the Master
|
|
|
|
|
* to the user callback (CR: 828504). Changes are made in the
|
|
|
|
|
* file xiic_slave.c.
|
2014-06-24 16:45:01 +05:30
|
|
|
* </pre>
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
#ifndef XIIC_H /* prevent circular inclusions */
|
|
|
|
|
#define XIIC_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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|
|
/***************************** Include Files *********************************/
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|
#include "xil_types.h"
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|
#include "xil_assert.h"
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|
#include "xstatus.h"
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|
#include "xiic_l.h"
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/************************** Constant Definitions *****************************/
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/** @name Configuration options
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|
*
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* The following options may be specified or retrieved for the device and
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* enable/disable additional features of the IIC bus. Each of the options
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* are bit fields such that more than one may be specified.
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* @{
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|
*/
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/**
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* <pre>
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|
* XII_GENERAL_CALL_OPTION The general call option allows an IIC slave to
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* recognized the general call address. The status
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* handler is called as usual indicating the device
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* has been addressed as a slave with a general
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* call. It is the application's responsibility to
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* perform any special processing for the general
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* call.
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*
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* XII_REPEATED_START_OPTION The repeated start option allows multiple
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* messages to be sent/received on the IIC bus
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* without rearbitrating for the bus. The messages
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* are sent as a series of messages such that the
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* option must be enabled before the 1st message of
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* the series, to prevent an stop condition from
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* being generated on the bus, and disabled before
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* the last message of the series, to allow the
|
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|
|
* stop condition to be generated.
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*
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|
* XII_SEND_10_BIT_OPTION The send 10 bit option allows 10 bit addresses
|
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* to be sent on the bus when the device is a
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* master. The device can be configured to respond
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|
* as to 7 bit addresses even though it may be
|
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|
|
* communicating with other devices that support 10
|
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|
|
* bit addresses. When this option is not enabled,
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* only 7 bit addresses are sent on the bus.
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*
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|
|
|
* </pre>
|
|
|
|
|
*/
|
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|
#define XII_GENERAL_CALL_OPTION 0x00000001
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|
#define XII_REPEATED_START_OPTION 0x00000002
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#define XII_SEND_10_BIT_OPTION 0x00000004
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/*@}*/
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|
|
/** @name Status events
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*
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|
|
* The following status events occur during IIC bus processing and are passed
|
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|
|
* to the status callback. Each event is only valid during the appropriate
|
|
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|
|
* processing of the IIC bus. Each of these events are bit fields such that
|
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|
|
* more than one may be specified.
|
|
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|
|
* @{
|
|
|
|
|
*/
|
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|
|
#define XII_BUS_NOT_BUSY_EVENT 0x00000001 /**< Bus transitioned to not busy */
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#define XII_ARB_LOST_EVENT 0x00000002 /**< Arbitration was lost */
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|
|
#define XII_SLAVE_NO_ACK_EVENT 0x00000004 /**< Slave did not ACK (had error) */
|
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|
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#define XII_MASTER_READ_EVENT 0x00000008 /**< Master reading from slave */
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|
|
#define XII_MASTER_WRITE_EVENT 0x00000010 /**< Master writing to slave */
|
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|
|
#define XII_GENERAL_CALL_EVENT 0x00000020 /**< General call to all slaves */
|
|
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|
|
/*@}*/
|
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|
|
/*
|
|
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|
|
* The following address types are used when setting and getting the addresses
|
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|
|
* of the driver. These are mutually exclusive such that only one or the other
|
|
|
|
|
* may be specified.
|
|
|
|
|
*/
|
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|
|
#define XII_ADDR_TO_SEND_TYPE 1 /**< Bus address of slave device */
|
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|
|
#define XII_ADDR_TO_RESPOND_TYPE 2 /**< This device's bus address as slave */
|
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|
|
/**************************** Type Definitions *******************************/
|
|
|
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|
|
/**
|
|
|
|
|
* This typedef contains configuration information for the device.
|
|
|
|
|
*/
|
|
|
|
|
typedef struct {
|
|
|
|
|
u16 DeviceId; /**< Unique ID of device */
|
|
|
|
|
u32 BaseAddress; /**< Device base address */
|
|
|
|
|
int Has10BitAddr; /**< Does device have 10 bit address decoding */
|
|
|
|
|
u8 GpOutWidth; /**< Number of bits in general purpose output */
|
|
|
|
|
} XIic_Config;
|
|
|
|
|
|
|
|
|
|
/****************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
* This callback function data type is defined to handle the asynchronous
|
|
|
|
|
* processing of sent and received data of the IIC driver. The application
|
|
|
|
|
* using this driver is expected to define a handler of this type to support
|
|
|
|
|
* interrupt driven mode. The handlers are called in an interrupt context such
|
|
|
|
|
* that minimal processing should be performed. The handler data type is
|
|
|
|
|
* utilized for both send and receive handlers.
|
|
|
|
|
*
|
|
|
|
|
* @param CallBackRef is a callback reference passed in by the upper
|
|
|
|
|
* layer when setting the callback functions, and passed back
|
|
|
|
|
* to the upper layer when the callback is invoked. Its type is
|
|
|
|
|
* unimportant to the driver component, so it is a void pointer.
|
|
|
|
|
* @param ByteCount indicates the number of bytes remaining to be sent or
|
|
|
|
|
* received. A value of zero indicates that the requested number
|
|
|
|
|
* of bytes were sent or received.
|
|
|
|
|
*
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
typedef void (*XIic_Handler) (void *CallBackRef, int ByteCount);
|
|
|
|
|
|
|
|
|
|
/******************************************************************************/
|
|
|
|
|
/**
|
|
|
|
|
* This callback function data type is defined to handle the asynchronous
|
|
|
|
|
* processing of status events of the IIC driver. The application using
|
|
|
|
|
* this driver is expected to define a handler of this type to support
|
|
|
|
|
* interrupt driven mode. The handler is called in an interrupt context such
|
|
|
|
|
* that minimal processing should be performed.
|
|
|
|
|
*
|
|
|
|
|
* @param CallBackRef is a callback reference passed in by the upper
|
|
|
|
|
* layer when setting the callback functions, and passed back
|
|
|
|
|
* to the upper layer when the callback is invoked. Its type is
|
|
|
|
|
* unimportant to the driver component, so it is a void pointer.
|
|
|
|
|
* @param StatusEvent indicates one or more status events that occurred.
|
|
|
|
|
* See the definition of the status events above.
|
|
|
|
|
*
|
|
|
|
|
********************************************************************************/
|
|
|
|
|
typedef void (*XIic_StatusHandler) (void *CallBackRef, int StatusEvent);
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* XIic statistics
|
|
|
|
|
*/
|
|
|
|
|
typedef struct {
|
|
|
|
|
u8 ArbitrationLost;/**< Number of times arbitration was lost */
|
|
|
|
|
u8 RepeatedStarts; /**< Number of repeated starts */
|
|
|
|
|
u8 BusBusy; /**< Number of times bus busy status returned */
|
|
|
|
|
u8 RecvBytes; /**< Number of bytes received */
|
|
|
|
|
u8 RecvInterrupts; /**< Number of receive interrupts */
|
|
|
|
|
u8 SendBytes; /**< Number of transmit bytes received */
|
|
|
|
|
u8 SendInterrupts; /**< Number of transmit interrupts */
|
|
|
|
|
u8 TxErrors; /**< Number of transmit errors (no ack) */
|
|
|
|
|
u8 IicInterrupts; /**< Number of IIC (device) interrupts */
|
|
|
|
|
} XIicStats;
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* The XIic driver instance data. The user is required to allocate a
|
|
|
|
|
* variable of this type for every IIC device in the system. A pointer
|
|
|
|
|
* to a variable of this type is then passed to the driver API functions.
|
|
|
|
|
*/
|
|
|
|
|
typedef struct {
|
|
|
|
|
XIicStats Stats; /**< Statistics */
|
|
|
|
|
u32 BaseAddress; /**< Device base address */
|
|
|
|
|
int Has10BitAddr; /**< TRUE when 10 bit addressing in design */
|
|
|
|
|
int IsReady; /**< Device is initialized and ready */
|
|
|
|
|
int IsStarted; /**< Device has been started */
|
|
|
|
|
int AddrOfSlave; /**< Slave Address writing to */
|
|
|
|
|
|
|
|
|
|
u32 Options; /**< Current operating options */
|
|
|
|
|
u8 *SendBufferPtr; /**< Buffer to send (state) */
|
|
|
|
|
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
|
|
|
|
|
u8 TxAddrMode; /**< State of Tx Address transmission */
|
|
|
|
|
int SendByteCount; /**< Number of data bytes in buffer (state) */
|
|
|
|
|
int RecvByteCount; /**< Number of empty bytes in buffer (state) */
|
|
|
|
|
|
|
|
|
|
u32 BNBOnly; /**< TRUE when BNB interrupt needs to */
|
|
|
|
|
/**< call callback */
|
|
|
|
|
u8 GpOutWidth; /**< General purpose output width */
|
|
|
|
|
|
|
|
|
|
XIic_StatusHandler StatusHandler; /**< Status Handler */
|
|
|
|
|
void *StatusCallBackRef; /**< Callback reference for status handler */
|
|
|
|
|
XIic_Handler RecvHandler; /**< Receive Handler */
|
|
|
|
|
void *RecvCallBackRef; /**< Callback reference for Recv handler */
|
|
|
|
|
XIic_Handler SendHandler; /**< Send Handler */
|
|
|
|
|
void *SendCallBackRef; /**< Callback reference for send handler */
|
|
|
|
|
int IsDynamic; /**< TRUE when Dynamic control is used */
|
|
|
|
|
int IsSlaveSetAckOff; /**< TRUE when Slave has set the ACK Off */
|
|
|
|
|
|
|
|
|
|
} XIic;
|
|
|
|
|
|
|
|
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
|
|
|
|
|
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Initialization functions in xiic_sinit.c
|
|
|
|
|
*/
|
|
|
|
|
int XIic_Initialize(XIic *InstancePtr, u16 DeviceId);
|
|
|
|
|
XIic_Config *XIic_LookupConfig(u16 DeviceId);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Functions in xiic.c
|
|
|
|
|
*/
|
|
|
|
|
int XIic_CfgInitialize(XIic *InstancePtr, XIic_Config *Config,
|
|
|
|
|
u32 EffectiveAddr);
|
|
|
|
|
|
|
|
|
|
int XIic_Start(XIic *InstancePtr);
|
|
|
|
|
int XIic_Stop(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
void XIic_Reset(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
int XIic_SetAddress(XIic *InstancePtr, int AddressType, int Address);
|
|
|
|
|
u16 XIic_GetAddress(XIic *InstancePtr, int AddressType);
|
|
|
|
|
|
|
|
|
|
int XIic_SetGpOutput(XIic *InstancePtr, u8 OutputValue);
|
|
|
|
|
int XIic_GetGpOutput(XIic *InstancePtr, u8 *OutputValuePtr);
|
|
|
|
|
|
|
|
|
|
u32 XIic_IsSlave(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
void XIic_SetRecvHandler(XIic *InstancePtr, void *CallBackRef,
|
|
|
|
|
XIic_Handler FuncPtr);
|
|
|
|
|
void XIic_SetSendHandler(XIic *InstancePtr, void *CallBackRef,
|
|
|
|
|
XIic_Handler FuncPtr);
|
|
|
|
|
void XIic_SetStatusHandler(XIic *InstancePtr, void *CallBackRef,
|
|
|
|
|
XIic_StatusHandler FuncPtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Interrupt functions in xiic_intr.c
|
|
|
|
|
*/
|
|
|
|
|
void XIic_InterruptHandler(void *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Master send and receive functions in normal mode in xiic_master.c
|
|
|
|
|
*/
|
|
|
|
|
int XIic_MasterRecv(XIic *InstancePtr, u8 *RxMsgPtr, int ByteCount);
|
|
|
|
|
int XIic_MasterSend(XIic *InstancePtr, u8 *TxMsgPtr, int ByteCount);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Master send and receive functions in dynamic mode in xiic_master.c
|
|
|
|
|
*/
|
|
|
|
|
int XIic_DynMasterRecv(XIic *InstancePtr, u8 *RxMsgPtr, u8 ByteCount);
|
|
|
|
|
int XIic_DynMasterSend(XIic *InstancePtr, u8 *TxMsgPtr, u8 ByteCount);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Dynamic IIC Core Initialization.
|
|
|
|
|
*/
|
|
|
|
|
int XIic_DynamicInitialize(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Slave send and receive functions in xiic_slave.c
|
|
|
|
|
*/
|
|
|
|
|
void XIic_SlaveInclude(void);
|
|
|
|
|
int XIic_SlaveRecv(XIic *InstancePtr, u8 *RxMsgPtr, int ByteCount);
|
|
|
|
|
int XIic_SlaveSend(XIic *InstancePtr, u8 *TxMsgPtr, int ByteCount);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Statistics functions in xiic_stats.c
|
|
|
|
|
*/
|
|
|
|
|
void XIic_GetStats(XIic *InstancePtr, XIicStats *StatsPtr);
|
|
|
|
|
void XIic_ClearStats(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Self test functions in xiic_selftest.c
|
|
|
|
|
*/
|
|
|
|
|
int XIic_SelfTest(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Bus busy Function in xiic.c
|
|
|
|
|
*/
|
|
|
|
|
u32 XIic_IsIicBusy(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Options functions in xiic_options.c
|
|
|
|
|
*/
|
|
|
|
|
void XIic_SetOptions(XIic *InstancePtr, u32 Options);
|
|
|
|
|
u32 XIic_GetOptions(XIic *InstancePtr);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Multi-master functions in xiic_multi_master.c
|
|
|
|
|
*/
|
|
|
|
|
void XIic_MultiMasterInclude(void);
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* end of protection macro */
|
