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dp: rx: Waiting for PHY to be ready based on number of lanes.

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If the DisplayPort core is configured for 1 or 2 maximum lanes, wait for PHY to
be ready only on those lanes rather than waiting on all 4 lanes.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-25 22:02:29 -08:00 • committed by Nava kishore Manne
parent e81ba1fde6
commit 05f71ab631
1 changed files with 19 additions and 5 deletions
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24
XilinxProcessorIPLib/drivers/dp/src/xdp.c
View file

@ -1744,22 +1744,36 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
XDP_RX_PHY_CONFIG_GTRX_RESET_MASK);
/* Wait until all lane CPLLs have locked. */
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK |
XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK);
if (InstancePtr->Config.MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK |
XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK);
}
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Remove the reset from the PHY. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_PHY_CONFIG,
XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
/* Wait until the PHY has completed the reset cycle. */
Status = XDp_WaitPhyReady(InstancePtr,
if (InstancePtr->Config.MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK |
XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK |
XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK |
XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK |
XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK);
}
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}