sw_apps: openamp: modified matrix_multiply application
This patch modifies openamp matrix_multiply application to remove the hardcoded shared memory region and support for the memory region configuration as per requirement of the code in MPU region settings Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
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2 changed files with 23 additions and 43 deletions
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@ -36,6 +36,7 @@
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#include "xil_cache.h"
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#include "xil_mmu.h"
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#include "baremetal.h"
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#include "env.h"
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XScuGic InterruptController;
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@ -87,38 +88,6 @@ void zynqMP_r5_irq_isr() {
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XScuGic_CPUWriteReg(&InterruptController,XSCUGIC_EOI_OFFSET, raw_irq);
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}
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/***********************************************************************
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*
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*
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* zynqMP_r5_map_mem_region
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*
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*
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* This function sets-up the region of memory based on the given
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* attributes
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* There is no MMU for R5, no need to map phy address to vrt_addr
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*
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* @param addr - Starting address of memory region
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* @parma size - size of region
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* @param attrib - Attributes for memory region
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*
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*
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* OUTPUTS
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*
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* None
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*
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***********************************************************************/
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void zynqMP_r5_map_mem_region(u32 addr, u32 size, u32 attrib) {
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u32 Index, NumSize;
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/* Calculating the number of MBs required for the shared region*/
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NumSize = size / 0x100000;
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/* Xil_SetTlbAttributes is designed to configure memory for 1MB
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* region. The API is called multiple times to configure the number
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* of MBs required by shared memory size (calculated as NumSize)*/
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for (Index = 0; Index < NumSize; Index ++)
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Xil_SetTlbAttributes(addr + 0x100000 * Index, attrib);
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}
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/*
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***********************************************************************
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* IPI handling
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@ -230,6 +199,28 @@ void platform_cache_disable() {
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}
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void platform_map_mem_region(unsigned int va,unsigned int pa, unsigned int size,unsigned int flags) {
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unsigned int r5_flags;
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/* Assume DEVICE_SHARED if nothing indicates this is memory. */
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r5_flags = DEVICE_SHARED;
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if (flags & SHARED_MEM) {
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r5_flags = NORM_SHARED_NCACHE;
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if (flags & WB_CACHE) {
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r5_flags = NORM_SHARED_WB_WA;
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} else if (flags & WT_CACHE) {
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r5_flags = NORM_SHARED_WT_NWA;
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}
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} else if (flags & MEM_MAPPED) {
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r5_flags = NORM_NSHARED_NCACHE;
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if (flags & WB_CACHE) {
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r5_flags = NORM_NSHARED_WB_WA;
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} else if (flags & WT_CACHE) {
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r5_flags = NORM_NSHARED_WT_NWA;
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}
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}
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Xil_SetMPURegion(pa, size, r5_flags | PRIV_RW_USER_RW);
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return;
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}
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@ -88,14 +88,6 @@
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#define NUM_MATRIX 2
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#define SHUTDOWN_MSG 0xEF56A55A
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/*
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* Shared memory location as defined in linux device tree for remoteproc
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* User may need to check with device tree of remoteproc and ensure the
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* share memory address is same
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*/
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#define SHARED_MEMORY 0x3ED00000
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#define SHARED_SIZE 0x400000 /* size of the shared memory*/
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typedef struct _matrix {
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unsigned int size;
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unsigned int elements[MAX_SIZE][MAX_SIZE];
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@ -184,9 +176,6 @@ static void Matrix_Multiply(const matrix *m, const matrix *n, matrix *r) {
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}
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static void init_system() {
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/* configure MPU for shared memory region */
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zynqMP_r5_map_mem_region(SHARED_MEMORY, SHARED_SIZE, NORM_SHARED_NCACHE | PRIV_RW_USER_RW);
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/* Initilaize GIC */
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zynqMP_r5_gic_initialize();
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