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xilskey: Corrected error code names

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Error codes names of efuse PL Ultrascale are corrected

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
VNSL Durga 2015-10-10 17:21:25 +05:30 • committed by Nava kishore Manne
parent 2af5aa5b71
commit 09c1374102
2 changed files with 15 additions and 9 deletions
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7
lib/sw_services/xilskey/src/include/xilskey_utils.h
View file

@ -427,6 +427,8 @@ typedef enum {
XSK_EFUSEPL_ERROR_READ_PAGE_OUT_OF_RANGE, XSK_EFUSEPL_ERROR_READ_PAGE_OUT_OF_RANGE,
XSK_EFUSEPL_ERROR_FUSE_ROW_RANGE, XSK_EFUSEPL_ERROR_FUSE_ROW_RANGE,
XSK_EFUSEPL_ERROR_IN_PROGRAMMING_ROW,
XSK_EFUSEPL_ERROR_PRGRMG_ROWS_NOT_EMPTY,
/** /**
* XSKEfusepl_Program_Efuse() error codes * XSKEfusepl_Program_Efuse() error codes
*/ */
@ -450,7 +452,10 @@ typedef enum {
XSK_EFUSEPL_ERROR_FUSE_BUSY = 0x1F00, XSK_EFUSEPL_ERROR_FUSE_BUSY = 0x1F00,
XSK_EFUSEPL_ERROR_READING_FUSE_RSA_ROW = 0x2000, XSK_EFUSEPL_ERROR_READING_FUSE_RSA_ROW = 0x2000,
XSK_EFUSEPL_ERROR_TIMER_INTIALISE_ULTRA = 0x2200, XSK_EFUSEPL_ERROR_TIMER_INTIALISE_ULTRA = 0x2200,
XSK_EFUSEPL_ERROR_READING_FUSE_SEC = 0x2300 XSK_EFUSEPL_ERROR_READING_FUSE_SEC = 0x2300,
XSK_EFUSEPL_ERROR_PRGRMG_FUSE_SEC_ROW = 0x2500,
XSK_EFUSEPL_ERROR_PRGRMG_USER_KEY = 0x4000,
XSK_EFUSEPL_ERROR_PRGRMG_RSA_HASH = 0x8000
}XSKEfusePl_ErrorCodes; }XSKEfusePl_ErrorCodes;

17
lib/sw_services/xilskey/src/xilskey_epl.c
View file

@ -50,6 +50,7 @@
* 3.00 vns 31/07/15 Added efuse functionality for Ultrascale. * 3.00 vns 31/07/15 Added efuse functionality for Ultrascale.
* 4.0 vns 10/01/15 provided conditional compilation to support * 4.0 vns 10/01/15 provided conditional compilation to support
* ZynqMp platform also. * ZynqMp platform also.
* Corrected error code names of Ultrascale efuse PL
* *
****************************************************************************/ ****************************************************************************/
/***************************** Include Files *********************************/ /***************************** Include Files *********************************/
@ -1755,10 +1756,10 @@ static inline u8 XilSKey_EfusePl_ReadBit_Ultra(u8 Row, u8 Bit, u8 MarginOption,
} }
} }
/** /**
* If row = 1- then bits should be supported from 0 to 6 * If row = 10 then bits should be supported from 0 to 5
*/ */
if ((Row == XSK_EFUSEPL_SEC_ROW_ULTRA) && if ((Row == XSK_EFUSEPL_SEC_ROW_ULTRA) &&
(Row > XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA) ) { (Bit > XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA) ) {
ErrorCode = XSK_EFUSEPL_ERROR_WRITE_BIT_OUT_OF_RANGE; ErrorCode = XSK_EFUSEPL_ERROR_WRITE_BIT_OUT_OF_RANGE;
return XST_FAILURE; return XST_FAILURE;
} }
@ -2341,7 +2342,7 @@ static inline u32 XilSKey_EfusePl_Program_Ultra(XilSKey_EPl *InstancePtr)
XSK_EFUSEPL_USER_ROW_ULTRA, UserDataInBytes, XSK_EFUSEPL_USER_ROW_ULTRA, UserDataInBytes,
XSK_EFUSEPL_PAGE_0_ULTRA); XSK_EFUSEPL_PAGE_0_ULTRA);
if (Status != XST_SUCCESS) { if (Status != XST_SUCCESS) {
return Status; return (XSK_EFUSEPL_ERROR_PRGRMG_USER_KEY + Status);
} }
} }
@ -2357,7 +2358,7 @@ static inline u32 XilSKey_EfusePl_Program_Ultra(XilSKey_EPl *InstancePtr)
XSK_EFUSEPL_RSA_ROW_END_ULTRA, XSK_EFUSEPL_RSA_ROW_END_ULTRA,
RsaDataInBytes, XSK_EFUSEPL_PAGE_1_ULTRA); RsaDataInBytes, XSK_EFUSEPL_PAGE_1_ULTRA);
if (Status != XST_SUCCESS) { if (Status != XST_SUCCESS) {
return Status; return (XSK_EFUSEPL_ERROR_PRGRMG_RSA_HASH + Status);;
} }
} }
@ -2374,7 +2375,7 @@ static inline u32 XilSKey_EfusePl_Program_Ultra(XilSKey_EPl *InstancePtr)
SecData[XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA] = SecData[XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA] =
InstancePtr->DecoderDisable; InstancePtr->DecoderDisable;
if(XilSKey_EfusePl_ProgramSecRegister(SecData) != XST_SUCCESS) { if(XilSKey_EfusePl_ProgramSecRegister(SecData) != XST_SUCCESS) {
return (XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_CNTRL_ROW + return (XSK_EFUSEPL_ERROR_PRGRMG_FUSE_SEC_ROW +
ErrorCode); ErrorCode);
} }
@ -2558,7 +2559,7 @@ static inline u32 XilSKey_EfusePl_Program_RowRange_ultra(u8 RowStart, u8 RowEnd,
if(XilSKey_EfusePl_IsVectorAllZeros(RowData) != if(XilSKey_EfusePl_IsVectorAllZeros(RowData) !=
XST_SUCCESS) { XST_SUCCESS) {
return (XSK_EFUSEPL_ERROR_AES_ROW_NOT_EMPTY + return (XSK_EFUSEPL_ERROR_PRGRMG_ROWS_NOT_EMPTY +
ErrorCode); ErrorCode);
} }
} }
@ -2573,14 +2574,14 @@ static inline u32 XilSKey_EfusePl_Program_RowRange_ultra(u8 RowStart, u8 RowEnd,
if(XilSKey_EfusePl_ProgramRow_Ultra(Row, RowPtr, if(XilSKey_EfusePl_ProgramRow_Ultra(Row, RowPtr,
XSK_EFUSEPL_NORMAL_ULTRA, Page) != XSK_EFUSEPL_NORMAL_ULTRA, Page) !=
XST_SUCCESS) { XST_SUCCESS) {
return (XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_AES_ROW + return (XSK_EFUSEPL_ERROR_IN_PROGRAMMING_ROW +
ErrorCode); ErrorCode);
} }
/* Programming redundancy bits */ /* Programming redundancy bits */
if(XilSKey_EfusePl_ProgramRow_Ultra(Row, RowPtr, if(XilSKey_EfusePl_ProgramRow_Ultra(Row, RowPtr,
XSK_EFUSEPL_REDUNDANT_ULTRA, Page) != XSK_EFUSEPL_REDUNDANT_ULTRA, Page) !=
XST_SUCCESS) { XST_SUCCESS) {
return (XSK_EFUSEPL_ERROR_PROGRAMMING_FUSE_AES_ROW + return (XSK_EFUSEPL_ERROR_IN_PROGRAMMING_ROW +
ErrorCode); ErrorCode);
} }
} }