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v_tpg: Initial driver for tpg v7.0

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This is a new driver for updated tpg ip in the catalogue

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This commit is contained in:
Rohit Consul 2015-07-16 17:04:54 -07:00 • committed by Nava kishore Manne
parent 0a1c15f45c
commit 0f6fa4e9cd
9 changed files with 1247 additions and 0 deletions
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18
XilinxProcessorIPLib/drivers/v_tpg/data/v_tpg.mdd Executable file
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# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.3
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
#
# ==============================================================
OPTION psf_version = 2.1;
BEGIN driver v_tpg
OPTION supported_peripherals = (v_tpg_v7_0 );
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION name = v_tpg;
OPTION version = 7.0;
END driver

65
XilinxProcessorIPLib/drivers/v_tpg/data/v_tpg.tcl Executable file
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##############################################################################
#
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XV_tpg" \
"NUM_INSTANCES" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"HAS_AXI4S_SLAVE" \
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH"
xdefine_config_file $drv_handle "xv_tpg_g.c" "XV_tpg" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"HAS_AXI4S_SLAVE" \
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_tpg" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"HAS_AXI4S_SLAVE" \
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH"
}

34
XilinxProcessorIPLib/drivers/v_tpg/src/Makefile Normal file
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# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.3
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
#
# ==============================================================
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling v_tpg"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

517
XilinxProcessorIPLib/drivers/v_tpg/src/xv_tpg.c Normal file
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
/***************************** Include Files *********************************/
#include "xv_tpg.h"
#include "string.h"
/************************** Function Implementation *************************/
#ifndef __linux__
int XV_tpg_CfgInitialize(XV_tpg *InstancePtr,
XV_tpg_Config *ConfigPtr,
u32 EffectiveAddr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XV_tpg));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr,
sizeof(XV_tpg_Config));
InstancePtr->Config.BaseAddress = EffectiveAddr;
/* Set the flag to indicate the driver is ready */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
#endif
void XV_tpg_Start(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL) & 0x80;
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, Data | 0x01);
}
u32 XV_tpg_IsDone(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL);
return (Data >> 1) & 0x1;
}
u32 XV_tpg_IsIdle(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL);
return (Data >> 2) & 0x1;
}
u32 XV_tpg_IsReady(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL);
// check ap_start to see if the pcore is ready for next input
return !(Data & 0x1);
}
void XV_tpg_EnableAutoRestart(XV_tpg *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, 0x80);
}
void XV_tpg_DisableAutoRestart(XV_tpg *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, 0);
}
void XV_tpg_Set_height(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_HEIGHT_DATA, Data);
}
u32 XV_tpg_Get_height(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_HEIGHT_DATA);
return Data;
}
void XV_tpg_Set_width(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_WIDTH_DATA, Data);
}
u32 XV_tpg_Get_width(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_WIDTH_DATA);
return Data;
}
void XV_tpg_Set_bckgndId(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BCKGNDID_DATA, Data);
}
u32 XV_tpg_Get_bckgndId(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BCKGNDID_DATA);
return Data;
}
void XV_tpg_Set_ovrlayId(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_OVRLAYID_DATA, Data);
}
u32 XV_tpg_Get_ovrlayId(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_OVRLAYID_DATA);
return Data;
}
void XV_tpg_Set_maskId(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_MASKID_DATA, Data);
}
u32 XV_tpg_Get_maskId(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_MASKID_DATA);
return Data;
}
void XV_tpg_Set_motionSpeed(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_MOTIONSPEED_DATA, Data);
}
u32 XV_tpg_Get_motionSpeed(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_MOTIONSPEED_DATA);
return Data;
}
void XV_tpg_Set_colorFormat(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_COLORFORMAT_DATA, Data);
}
u32 XV_tpg_Get_colorFormat(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_COLORFORMAT_DATA);
return Data;
}
void XV_tpg_Set_crossHairX(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_CROSSHAIRX_DATA, Data);
}
u32 XV_tpg_Get_crossHairX(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_CROSSHAIRX_DATA);
return Data;
}
void XV_tpg_Set_crossHairY(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_CROSSHAIRY_DATA, Data);
}
u32 XV_tpg_Get_crossHairY(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_CROSSHAIRY_DATA);
return Data;
}
void XV_tpg_Set_ZplateHorContStart(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEHORCONTSTART_DATA, Data);
}
u32 XV_tpg_Get_ZplateHorContStart(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEHORCONTSTART_DATA);
return Data;
}
void XV_tpg_Set_ZplateHorContDelta(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEHORCONTDELTA_DATA, Data);
}
u32 XV_tpg_Get_ZplateHorContDelta(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEHORCONTDELTA_DATA);
return Data;
}
void XV_tpg_Set_ZplateVerContStart(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEVERCONTSTART_DATA, Data);
}
u32 XV_tpg_Get_ZplateVerContStart(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEVERCONTSTART_DATA);
return Data;
}
void XV_tpg_Set_ZplateVerContDelta(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEVERCONTDELTA_DATA, Data);
}
u32 XV_tpg_Get_ZplateVerContDelta(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ZPLATEVERCONTDELTA_DATA);
return Data;
}
void XV_tpg_Set_boxSize(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXSIZE_DATA, Data);
}
u32 XV_tpg_Get_boxSize(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXSIZE_DATA);
return Data;
}
void XV_tpg_Set_boxColorR(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORR_DATA, Data);
}
u32 XV_tpg_Get_boxColorR(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORR_DATA);
return Data;
}
void XV_tpg_Set_boxColorG(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORG_DATA, Data);
}
u32 XV_tpg_Get_boxColorG(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORG_DATA);
return Data;
}
void XV_tpg_Set_boxColorB(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORB_DATA, Data);
}
u32 XV_tpg_Get_boxColorB(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_BOXCOLORB_DATA);
return Data;
}
void XV_tpg_Set_enableInput(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ENABLEINPUT_DATA, Data);
}
u32 XV_tpg_Get_enableInput(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ENABLEINPUT_DATA);
return Data;
}
void XV_tpg_Set_passthruStartX(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUSTARTX_DATA, Data);
}
u32 XV_tpg_Get_passthruStartX(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUSTARTX_DATA);
return Data;
}
void XV_tpg_Set_passthruStartY(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUSTARTY_DATA, Data);
}
u32 XV_tpg_Get_passthruStartY(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUSTARTY_DATA);
return Data;
}
void XV_tpg_Set_passthruEndX(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUENDX_DATA, Data);
}
u32 XV_tpg_Get_passthruEndX(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUENDX_DATA);
return Data;
}
void XV_tpg_Set_passthruEndY(XV_tpg *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUENDY_DATA, Data);
}
u32 XV_tpg_Get_passthruEndY(XV_tpg *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_PASSTHRUENDY_DATA);
return Data;
}
void XV_tpg_InterruptGlobalEnable(XV_tpg *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_GIE, 1);
}
void XV_tpg_InterruptGlobalDisable(XV_tpg *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_GIE, 0);
}
void XV_tpg_InterruptEnable(XV_tpg *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_IER);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_IER, Register | Mask);
}
void XV_tpg_InterruptDisable(XV_tpg *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_IER);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_IER, Register & (~Mask));
}
void XV_tpg_InterruptClear(XV_tpg *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_tpg_WriteReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ISR, Mask);
}
u32 XV_tpg_InterruptGetEnabled(XV_tpg *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_IER);
}
u32 XV_tpg_InterruptGetStatus(XV_tpg *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_tpg_ReadReg(InstancePtr->Config.BaseAddress, XV_TPG_CTRL_ADDR_ISR);
}

187
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
#ifndef XV_TPG_H
#define XV_TPG_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#ifndef __linux__
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_io.h"
#else
#include <stdint.h>
#include <assert.h>
#include <dirent.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <stddef.h>
#endif
#include "xv_tpg_hw.h"
/**************************** Type Definitions ******************************/
#ifdef __linux__
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
#else
/**
* This typedef enumerates the different patterns supported by TPG
*/
typedef enum
{
XTPG_BKGND_H_RAMP = 1,
XTPG_BKGND_V_RAMP,
XTPG_BKGND_TEMPORAL_RAMP,
XTPG_BKGND_SOLID_RED,
XTPG_BKGND_SOLID_GREEN,
XTPG_BKGND_SOLID_BLUE,
XTPG_BKGND_SOLID_BLACK,
XTPG_BKGND_SOLID_WHITE,
XTPG_BKGND_COLOR_BARS,
XTPG_BKGND_ZONE_PLATE,
XTPG_BKGND_TARTAN_COLOR_BARS,
XTPG_BKGND_CROSS_HATCH,
XTPG_BKGND_RAINBOW_COLOR,
XTPG_BKGND_HV_RAMP,
XTPG_BKGND_CHECKER_BOARD,
XTPG_BKGND_PBRS,
XTPG_BKGND_LAST
}XTpg_PatternId;
/**
* This typedef contains configuration information for the tpg core
* Each core instance should have a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< The base address of the core instance. */
u16 HasAxi4sSlave; /**< Axi4s Slave capability indicator */
u16 PixPerClk; /**< Samples Per Clock supported by core instance */
u16 NumVidComponents; /**< Number of Video Components */
u16 MaxWidth; /**< Maximum columns supported by core instance */
u16 MaxHeight; /**< Maximum rows supported by core instance */
u16 MaxDataWidth; /**< Maximum Data width of each channel */
} XV_tpg_Config;
#endif
/**
* Driver instance data. An instance must be allocated for each core in use.
*/
typedef struct {
XV_tpg_Config Config; /**< Hardware Configuration */
u32 IsReady; /**< Device is initialized and ready */
} XV_tpg;
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef __linux__
#define XV_tpg_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
#define XV_tpg_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
#else
#define XV_tpg_WriteReg(BaseAddress, RegOffset, Data) \
*(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
#define XV_tpg_ReadReg(BaseAddress, RegOffset) \
*(volatile u32*)((BaseAddress) + (RegOffset))
#define Xil_AssertVoid(expr) assert(expr)
#define Xil_AssertNonvoid(expr) assert(expr)
#define XST_SUCCESS 0
#define XST_DEVICE_NOT_FOUND 2
#define XST_OPEN_DEVICE_FAILED 3
#define XIL_COMPONENT_IS_READY 1
#endif
/************************** Function Prototypes *****************************/
#ifndef __linux__
int XV_tpg_Initialize(XV_tpg *InstancePtr, u16 DeviceId);
XV_tpg_Config* XV_tpg_LookupConfig(u16 DeviceId);
int XV_tpg_CfgInitialize(XV_tpg *InstancePtr,
XV_tpg_Config *ConfigPtr,
u32 EffectiveAddr);
#else
int XV_tpg_Initialize(XV_tpg *InstancePtr, const char* InstanceName);
int XV_tpg_Release(XV_tpg *InstancePtr);
#endif
void XV_tpg_Start(XV_tpg *InstancePtr);
u32 XV_tpg_IsDone(XV_tpg *InstancePtr);
u32 XV_tpg_IsIdle(XV_tpg *InstancePtr);
u32 XV_tpg_IsReady(XV_tpg *InstancePtr);
void XV_tpg_EnableAutoRestart(XV_tpg *InstancePtr);
void XV_tpg_DisableAutoRestart(XV_tpg *InstancePtr);
void XV_tpg_Set_height(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_height(XV_tpg *InstancePtr);
void XV_tpg_Set_width(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_width(XV_tpg *InstancePtr);
void XV_tpg_Set_bckgndId(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_bckgndId(XV_tpg *InstancePtr);
void XV_tpg_Set_ovrlayId(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_ovrlayId(XV_tpg *InstancePtr);
void XV_tpg_Set_maskId(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_maskId(XV_tpg *InstancePtr);
void XV_tpg_Set_motionSpeed(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_motionSpeed(XV_tpg *InstancePtr);
void XV_tpg_Set_colorFormat(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_colorFormat(XV_tpg *InstancePtr);
void XV_tpg_Set_crossHairX(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_crossHairX(XV_tpg *InstancePtr);
void XV_tpg_Set_crossHairY(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_crossHairY(XV_tpg *InstancePtr);
void XV_tpg_Set_ZplateHorContStart(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_ZplateHorContStart(XV_tpg *InstancePtr);
void XV_tpg_Set_ZplateHorContDelta(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_ZplateHorContDelta(XV_tpg *InstancePtr);
void XV_tpg_Set_ZplateVerContStart(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_ZplateVerContStart(XV_tpg *InstancePtr);
void XV_tpg_Set_ZplateVerContDelta(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_ZplateVerContDelta(XV_tpg *InstancePtr);
void XV_tpg_Set_boxSize(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_boxSize(XV_tpg *InstancePtr);
void XV_tpg_Set_boxColorR(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_boxColorR(XV_tpg *InstancePtr);
void XV_tpg_Set_boxColorG(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_boxColorG(XV_tpg *InstancePtr);
void XV_tpg_Set_boxColorB(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_boxColorB(XV_tpg *InstancePtr);
void XV_tpg_Set_enableInput(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_enableInput(XV_tpg *InstancePtr);
void XV_tpg_Set_passthruStartX(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_passthruStartX(XV_tpg *InstancePtr);
void XV_tpg_Set_passthruStartY(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_passthruStartY(XV_tpg *InstancePtr);
void XV_tpg_Set_passthruEndX(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_passthruEndX(XV_tpg *InstancePtr);
void XV_tpg_Set_passthruEndY(XV_tpg *InstancePtr, u32 Data);
u32 XV_tpg_Get_passthruEndY(XV_tpg *InstancePtr);
void XV_tpg_InterruptGlobalEnable(XV_tpg *InstancePtr);
void XV_tpg_InterruptGlobalDisable(XV_tpg *InstancePtr);
void XV_tpg_InterruptEnable(XV_tpg *InstancePtr, u32 Mask);
void XV_tpg_InterruptDisable(XV_tpg *InstancePtr, u32 Mask);
void XV_tpg_InterruptClear(XV_tpg *InstancePtr, u32 Mask);
u32 XV_tpg_InterruptGetEnabled(XV_tpg *InstancePtr);
u32 XV_tpg_InterruptGetStatus(XV_tpg *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif

61
XilinxProcessorIPLib/drivers/v_tpg/src/xv_tpg_g.c Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xv_tpg.h"
/*
* The configuration table for devices
*/
XV_tpg_Config XV_tpg_ConfigTable[] =
{
{
#ifdef XPAR_XV_TPG_NUM_INSTANCES
XPAR_V_TPG_0_DEVICE_ID,
XPAR_V_TPG_0_S_AXI_CTRL_BASEADDR,
XPAR_V_TPG_0_HAS_AXI4S_SLAVE,
XPAR_V_TPG_0_SAMPLES_PER_CLOCK,
XPAR_V_TPG_0_NUM_VIDEO_COMPONENTS,
XPAR_V_TPG_0_MAX_COLS,
XPAR_V_TPG_0_MAX_ROWS,
XPAR_V_TPG_0_MAX_DATA_WIDTH
#endif
}
};

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XilinxProcessorIPLib/drivers/v_tpg/src/xv_tpg_hw.h Normal file
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
// CTRL
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of height
// bit 15~0 - height[15:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of width
// bit 15~0 - width[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// 0x20 : Data signal of bckgndId
// bit 7~0 - bckgndId[7:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// 0x28 : Data signal of ovrlayId
// bit 7~0 - ovrlayId[7:0] (Read/Write)
// others - reserved
// 0x2c : reserved
// 0x30 : Data signal of maskId
// bit 7~0 - maskId[7:0] (Read/Write)
// others - reserved
// 0x34 : reserved
// 0x38 : Data signal of motionSpeed
// bit 7~0 - motionSpeed[7:0] (Read/Write)
// others - reserved
// 0x3c : reserved
// 0x40 : Data signal of colorFormat
// bit 7~0 - colorFormat[7:0] (Read/Write)
// others - reserved
// 0x44 : reserved
// 0x48 : Data signal of crossHairX
// bit 15~0 - crossHairX[15:0] (Read/Write)
// others - reserved
// 0x4c : reserved
// 0x50 : Data signal of crossHairY
// bit 15~0 - crossHairY[15:0] (Read/Write)
// others - reserved
// 0x54 : reserved
// 0x58 : Data signal of ZplateHorContStart
// bit 15~0 - ZplateHorContStart[15:0] (Read/Write)
// others - reserved
// 0x5c : reserved
// 0x60 : Data signal of ZplateHorContDelta
// bit 15~0 - ZplateHorContDelta[15:0] (Read/Write)
// others - reserved
// 0x64 : reserved
// 0x68 : Data signal of ZplateVerContStart
// bit 15~0 - ZplateVerContStart[15:0] (Read/Write)
// others - reserved
// 0x6c : reserved
// 0x70 : Data signal of ZplateVerContDelta
// bit 15~0 - ZplateVerContDelta[15:0] (Read/Write)
// others - reserved
// 0x74 : reserved
// 0x78 : Data signal of boxSize
// bit 15~0 - boxSize[15:0] (Read/Write)
// others - reserved
// 0x7c : reserved
// 0x80 : Data signal of boxColorR
// bit 15~0 - boxColorR[15:0] (Read/Write)
// others - reserved
// 0x84 : reserved
// 0x88 : Data signal of boxColorG
// bit 15~0 - boxColorG[15:0] (Read/Write)
// others - reserved
// 0x8c : reserved
// 0x90 : Data signal of boxColorB
// bit 15~0 - boxColorB[15:0] (Read/Write)
// others - reserved
// 0x94 : reserved
// 0x98 : Data signal of enableInput
// bit 7~0 - enableInput[7:0] (Read/Write)
// others - reserved
// 0x9c : reserved
// 0xa0 : Data signal of passthruStartX
// bit 15~0 - passthruStartX[15:0] (Read/Write)
// others - reserved
// 0xa4 : reserved
// 0xa8 : Data signal of passthruStartY
// bit 15~0 - passthruStartY[15:0] (Read/Write)
// others - reserved
// 0xac : reserved
// 0xb0 : Data signal of passthruEndX
// bit 15~0 - passthruEndX[15:0] (Read/Write)
// others - reserved
// 0xb4 : reserved
// 0xb8 : Data signal of passthruEndY
// bit 15~0 - passthruEndY[15:0] (Read/Write)
// others - reserved
// 0xbc : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XV_TPG_CTRL_ADDR_AP_CTRL 0x00
#define XV_TPG_CTRL_ADDR_GIE 0x04
#define XV_TPG_CTRL_ADDR_IER 0x08
#define XV_TPG_CTRL_ADDR_ISR 0x0c
#define XV_TPG_CTRL_ADDR_HEIGHT_DATA 0x10
#define XV_TPG_CTRL_BITS_HEIGHT_DATA 16
#define XV_TPG_CTRL_ADDR_WIDTH_DATA 0x18
#define XV_TPG_CTRL_BITS_WIDTH_DATA 16
#define XV_TPG_CTRL_ADDR_BCKGNDID_DATA 0x20
#define XV_TPG_CTRL_BITS_BCKGNDID_DATA 8
#define XV_TPG_CTRL_ADDR_OVRLAYID_DATA 0x28
#define XV_TPG_CTRL_BITS_OVRLAYID_DATA 8
#define XV_TPG_CTRL_ADDR_MASKID_DATA 0x30
#define XV_TPG_CTRL_BITS_MASKID_DATA 8
#define XV_TPG_CTRL_ADDR_MOTIONSPEED_DATA 0x38
#define XV_TPG_CTRL_BITS_MOTIONSPEED_DATA 8
#define XV_TPG_CTRL_ADDR_COLORFORMAT_DATA 0x40
#define XV_TPG_CTRL_BITS_COLORFORMAT_DATA 8
#define XV_TPG_CTRL_ADDR_CROSSHAIRX_DATA 0x48
#define XV_TPG_CTRL_BITS_CROSSHAIRX_DATA 16
#define XV_TPG_CTRL_ADDR_CROSSHAIRY_DATA 0x50
#define XV_TPG_CTRL_BITS_CROSSHAIRY_DATA 16
#define XV_TPG_CTRL_ADDR_ZPLATEHORCONTSTART_DATA 0x58
#define XV_TPG_CTRL_BITS_ZPLATEHORCONTSTART_DATA 16
#define XV_TPG_CTRL_ADDR_ZPLATEHORCONTDELTA_DATA 0x60
#define XV_TPG_CTRL_BITS_ZPLATEHORCONTDELTA_DATA 16
#define XV_TPG_CTRL_ADDR_ZPLATEVERCONTSTART_DATA 0x68
#define XV_TPG_CTRL_BITS_ZPLATEVERCONTSTART_DATA 16
#define XV_TPG_CTRL_ADDR_ZPLATEVERCONTDELTA_DATA 0x70
#define XV_TPG_CTRL_BITS_ZPLATEVERCONTDELTA_DATA 16
#define XV_TPG_CTRL_ADDR_BOXSIZE_DATA 0x78
#define XV_TPG_CTRL_BITS_BOXSIZE_DATA 16
#define XV_TPG_CTRL_ADDR_BOXCOLORR_DATA 0x80
#define XV_TPG_CTRL_BITS_BOXCOLORR_DATA 16
#define XV_TPG_CTRL_ADDR_BOXCOLORG_DATA 0x88
#define XV_TPG_CTRL_BITS_BOXCOLORG_DATA 16
#define XV_TPG_CTRL_ADDR_BOXCOLORB_DATA 0x90
#define XV_TPG_CTRL_BITS_BOXCOLORB_DATA 16
#define XV_TPG_CTRL_ADDR_ENABLEINPUT_DATA 0x98
#define XV_TPG_CTRL_BITS_ENABLEINPUT_DATA 8
#define XV_TPG_CTRL_ADDR_PASSTHRUSTARTX_DATA 0xa0
#define XV_TPG_CTRL_BITS_PASSTHRUSTARTX_DATA 16
#define XV_TPG_CTRL_ADDR_PASSTHRUSTARTY_DATA 0xa8
#define XV_TPG_CTRL_BITS_PASSTHRUSTARTY_DATA 16
#define XV_TPG_CTRL_ADDR_PASSTHRUENDX_DATA 0xb0
#define XV_TPG_CTRL_BITS_PASSTHRUENDX_DATA 16
#define XV_TPG_CTRL_ADDR_PASSTHRUENDY_DATA 0xb8
#define XV_TPG_CTRL_BITS_PASSTHRUENDY_DATA 16

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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
#ifdef __linux__
/***************************** Include Files *********************************/
#include "xv_tpg.h"
/***************** Macros (Inline Functions) Definitions *********************/
#define MAX_UIO_PATH_SIZE 256
#define MAX_UIO_NAME_SIZE 64
#define MAX_UIO_MAPS 5
#define UIO_INVALID_ADDR 0
/**************************** Type Definitions ******************************/
typedef struct {
u32 addr;
u32 size;
} XV_tpg_uio_map;
typedef struct {
int uio_fd;
int uio_num;
char name[ MAX_UIO_NAME_SIZE ];
char version[ MAX_UIO_NAME_SIZE ];
XV_tpg_uio_map maps[ MAX_UIO_MAPS ];
} XV_tpg_uio_info;
/***************** Variable Definitions **************************************/
static XV_tpg_uio_info uio_info;
/************************** Function Implementation *************************/
static int line_from_file(char* filename, char* linebuf) {
char* s;
int i;
FILE* fp = fopen(filename, "r");
if (!fp) return -1;
s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
fclose(fp);
if (!s) return -2;
for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
if (*s == '\n') *s = 0;
s++;
}
return 0;
}
static int uio_info_read_name(XV_tpg_uio_info* info) {
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
return line_from_file(file, info->name);
}
static int uio_info_read_version(XV_tpg_uio_info* info) {
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
return line_from_file(file, info->version);
}
static int uio_info_read_map_addr(XV_tpg_uio_info* info, int n) {
int ret;
char file[ MAX_UIO_PATH_SIZE ];
info->maps[n].addr = UIO_INVALID_ADDR;
sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
FILE* fp = fopen(file, "r");
if (!fp) return -1;
ret = fscanf(fp, "0x%x", &info->maps[n].addr);
fclose(fp);
if (ret < 0) return -2;
return 0;
}
static int uio_info_read_map_size(XV_tpg_uio_info* info, int n) {
int ret;
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
FILE* fp = fopen(file, "r");
if (!fp) return -1;
ret = fscanf(fp, "0x%x", &info->maps[n].size);
fclose(fp);
if (ret < 0) return -2;
return 0;
}
int XV_tpg_Initialize(XV_tpg *InstancePtr, const char* InstanceName) {
XV_tpg_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
int i, n;
char* s;
char file[ MAX_UIO_PATH_SIZE ];
char name[ MAX_UIO_NAME_SIZE ];
int flag = 0;
assert(InstancePtr != NULL);
n = scandir("/sys/class/uio", &namelist, 0, alphasort);
if (n < 0) return XST_DEVICE_NOT_FOUND;
for (i = 0; i < n; i++) {
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
flag = 1;
s = namelist[i]->d_name;
s += 3; // "uio"
InfoPtr->uio_num = atoi(s);
break;
}
}
if (flag == 0) return XST_DEVICE_NOT_FOUND;
uio_info_read_name(InfoPtr);
uio_info_read_version(InfoPtr);
for (n = 0; n < MAX_UIO_MAPS; ++n) {
uio_info_read_map_addr(InfoPtr, n);
uio_info_read_map_size(InfoPtr, n);
}
sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
return XST_OPEN_DEVICE_FAILED;
}
// NOTE: slave interface 'Ctrl' should be mapped to uioX/map0
InstancePtr->Config.BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Config.BaseAddress);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
int XV_tpg_Release(XV_tpg *InstancePtr) {
XV_tpg_uio_info *InfoPtr = &uio_info;
assert(InstancePtr != NULL);
assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
munmap((void*)InstancePtr->Config.BaseAddress, InfoPtr->maps[0].size);
close(InfoPtr->uio_fd);
return XST_SUCCESS;
}
#endif

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XilinxProcessorIPLib/drivers/v_tpg/src/xv_tpg_sinit.c Normal file
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
#ifndef __linux__
#include "xstatus.h"
#include "xparameters.h"
#include "xv_tpg.h"
#ifndef XPAR_XV_TPG_NUM_INSTANCES
#define XPAR_XV_TPG_NUM_INSTANCES 0
#endif
extern XV_tpg_Config XV_tpg_ConfigTable[];
XV_tpg_Config *XV_tpg_LookupConfig(u16 DeviceId) {
XV_tpg_Config *ConfigPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XV_TPG_NUM_INSTANCES; Index++) {
if (XV_tpg_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XV_tpg_ConfigTable[Index];
break;
}
}
return ConfigPtr;
}
int XV_tpg_Initialize(XV_tpg *InstancePtr, u16 DeviceId) {
XV_tpg_Config *ConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
ConfigPtr = XV_tpg_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XV_tpg_CfgInitialize(InstancePtr,
ConfigPtr,
ConfigPtr->BaseAddress);
}
#endif