dptx: Multi-stream transport (MST) addition.
Main chunk of MST code added. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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c4154510b8
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3 changed files with 1470 additions and 11 deletions
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@ -127,7 +127,7 @@
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* either the HPD event handler function or the HPD pulse handler function,
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* depending on whether a an HPD event on an HPD pulse event occurred.
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*
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* The DisplayPort Tx's XDPTX_INTERRUPT_STATUS register indicates the type of
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* The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of
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* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
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* information to decide which handler to call. An HPD event is identified if
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* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
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@ -182,6 +182,32 @@
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#include "xil_assert.h"
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#include "xil_types.h"
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/* Need to reorganize this... */
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/* To add to xstatus.h. */
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#define XST_CRC_ERROR 30L
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#define XDPTX_SBMSG_LINK_ADDRESS 0x01
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#define XDPTX_SBMSG_ENUM_PATH_RESOURCES 0x10
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#define XDPTX_SBMSG_ALLOCATE_PAYLOAD 0x11
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#define XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE 0x14
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#define XDPTX_SBMSG_REMOTE_DPCD_READ 0x20
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#define XDPTX_SBMSG_REMOTE_DPCD_WRITE 0x21
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#define XDPTX_SBMSG_REMOTE_I2C_READ 0x22
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/* When returning the reason for NACK reply, XST_SBREPLY_NACK is added in order
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* to differentiate between the return codes in xstatus.h. */
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#define XST_SBREPLY_NACK 1452L
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#define XDPTX_SBREPLY_NACK_WRITE_FAILURE 0x01
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#define XDPTX_SBREPLY_NACK_INVALID_RAD 0x02
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#define XDPTX_SBREPLY_NACK_CRC_FAILURE 0x03
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#define XDPTX_SBREPLY_NACK_BAD_PARAM 0x04
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#define XDPTX_SBREPLY_NACK_DEFER 0x05
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#define XDPTX_SBREPLY_NACK_LINK_FAILURE 0x06
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#define XDPTX_SBREPLY_NACK_NO_RESOURCES 0x07
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#define XDPTX_SBREPLY_NACK_DPCD_FAIL 0x08
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#define XDPTX_SBREPLY_NACK_I2C_NAK 0x09
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#define XDPTX_SBREPLY_NACK_ALLOCATE_FAIL 0x0A
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/******************* Macros (Inline Functions) Definitions ********************/
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/******************************************************************************/
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@ -462,13 +488,46 @@ typedef struct {
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use by the video stream. */
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u8 SynchronousClockMode; /**< Synchronous clock mode is currently
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in use by the video stream. */
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} XDptx_MainStreamAttributes;
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typedef struct {
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u8 LinkCountTotal; /** The total number of DisplayPort
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links from the DisplayPort TX
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to the sink device that this MST
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stream is targeting.*/
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u8 RelativeAddress[15]; /** The relative address from the
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DisplayPort TX to the sink
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device that this MST stream is
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targeting.*/
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u16 MstPbn; /**< Payload bandwidth number used to
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allocate bandwidth in MST
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mode. */
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allocate bandwidth for the MST
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stream. */
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u8 MstStreamEnable; /**< In MST mode, enables the
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corresponding stream for this
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MSA configuration. */
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} XDptx_MainStreamAttributes;
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} XDptx_MstStream;
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typedef struct {
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u8 InputPort;
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u8 PeerDeviceType;
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u8 PortNum;
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u8 MsgCapStatus;
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u8 DpDevPlugStatus;
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u8 LegacyDevPlugStatus;
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u8 DpcdRev;
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u32 Guid[4];
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u8 NumSdpStreams;
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u8 NumSdpStreamSinks;
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} XDptx_SbMsgLinkAddressReplyPortDetail;
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typedef struct {
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u8 ReplyType;
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u8 RequestId;
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u32 Guid[4];
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u8 NumPorts;
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XDptx_SbMsgLinkAddressReplyPortDetail PortDetails[16];
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} XDptx_SbMsgLinkAddressReplyDeviceInfo;
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/******************************************************************************/
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/**
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@ -512,6 +571,22 @@ typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
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*******************************************************************************/
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typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
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typedef struct {
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u32 Guid[4];
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u8 RelativeAddress[15];
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u8 DeviceType;
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u8 LinkCountTotal;
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u8 DpcdRev;
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u8 MsgCapStatus;
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} XDptx_TopologyNode;
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typedef struct {
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u8 NodeTotal;
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XDptx_TopologyNode NodeTable[63];
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u8 SinkTotal;
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XDptx_TopologyNode *SinkList[63];
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} XDptx_Topology;
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/**
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* The XDptx driver instance data. The user is required to allocate a variable
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* of this type for every XDptx device in the system. A pointer to a variable of
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@ -546,6 +621,11 @@ typedef struct {
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of attributes. When MST
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mode is disabled, only
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MsaConfig[0] is used. */
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XDptx_MstStream MstStreamConfig[4]; /**< Configuration structure
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for a multi-stream
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transport (MST)
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stream. */
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XDptx_Topology Topology;
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XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
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delay/sleep. */
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void *UserTimerPtr; /**< Pointer to a timer instance
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@ -616,6 +696,7 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream);
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void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
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XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
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void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor);
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void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable);
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void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream);
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void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream);
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void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream);
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@ -633,4 +714,30 @@ u32 XDptx_SelfTest(XDptx *InstancePtr);
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/* xdptx_sinit.c: Configuration extraction function.*/
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XDptx_Config *XDptx_LookupConfig(u16 DeviceId);
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/* xdptx_mst.c: Multi-stream transport (MST) functions. */
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void XDptx_MstCfgModeEnable(XDptx *InstancePtr);
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void XDptx_MstCfgModeDisable(XDptx *InstancePtr);
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void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream);
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void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream);
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u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream);
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u32 XDptx_MstEnable(XDptx *InstancePtr);
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u32 XDptx_MstDisable(XDptx *InstancePtr);
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u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr);
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void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 SinkNum);
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void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress);
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u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr);
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void XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress);
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void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4]);
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void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid);
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/* Sideband messages. */
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u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u8 BytesToWrite, u8 *WriteData);
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u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u8 BytesToRead, u8 *ReadData);
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u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 IicDeviceId, u8 BytesToRead, u8 *ReadData);
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u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *FormatReply);
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u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn);
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u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn);
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u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr);
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#endif /* XDPTX_H_ */
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1325
XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c
Normal file
1325
XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -185,9 +185,6 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream)
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(MsaConfig->SynchronousClockMode);
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MsaConfig->Misc1 = 0;
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MsaConfig->DataPerLane = (MsaConfig->Dmt.HResolution *
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MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
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/* Determine the number of bits per pixel for the specified color
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* component format. */
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if (MsaConfig->ComponentFormat ==
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if (InstancePtr->MstEnable == 1) {
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MsaConfig->DataPerLane = (MsaConfig->Dmt.HResolution *
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MsaConfig->BitsPerColor * 3 / 16) - 4;
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/* Do time slot (and payload bandwidth number) calculations for
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* MST. */
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XDptx_CalculateTs(InstancePtr, Stream, BitsPerPixel);
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MsaConfig->InitWait = 0;
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}
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else {
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MsaConfig->DataPerLane = (MsaConfig->Dmt.HResolution *
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MsaConfig->BitsPerColor * 3 / 16) -
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LinkConfig->LaneCount;
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/* Allocate a fixed size for single-stream transport (SST)
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* operation. */
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MsaConfig->TransferUnitSize = 64;
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XDptx_CfgMsaRecalculate(InstancePtr, Stream);
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}
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void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable)
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{
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XDptx_MainStreamAttributes *MsaConfig =
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&InstancePtr->MsaConfig[Stream - 1];
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Enable == 0) || (Enable == 1));
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MsaConfig->SynchronousClockMode = Enable;
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if (Enable == 1) {
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MsaConfig->Misc0 |= (1 <<
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XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT);
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}
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else {
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MsaConfig->Misc0 &= ~(1 <<
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XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT);
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}
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}
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/******************************************************************************/
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/**
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* This function clears the main stream attributes registers of the DisplayPort
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XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID +
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StreamOffset[Stream - 1], 0);
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XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream - 1) * 4, 0);
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XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE +
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StreamOffset[Stream - 1], 0);
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LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27);
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/* Calculate the payload bandiwdth number (PBN). */
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MsaConfig->MstPbn = ceil(1.006 * PeakPixelBw * ((double)64 / 54));
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InstancePtr->MstStreamConfig[Stream - 1].MstPbn =
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ceil(1.006 * PeakPixelBw * ((double)64 / 54));
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/* Calculate the average stream symbol time slots per MTP. */
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Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw);
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MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 *
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((double)MsaConfig->MstPbn / LinkBw));
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((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn /
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LinkBw));
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/* The target value to be found needs to follow the condition:
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* Average_StreamSymbolTimeSlotsPerMTP <=
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}
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/* Determine the PBN for the stream. */
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MsaConfig->MstPbn = MsaConfig->TransferUnitSize *
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InstancePtr->MstStreamConfig[Stream - 1].MstPbn =
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MsaConfig->TransferUnitSize *
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(LinkConfig->LaneCount * LinkConfig->LinkRate / 2);
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}
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