stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

dp: rx: Added assertions on function arguments.

Browse source 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-20 14:12:30 -08:00 • committed by Nava kishore Manne
parent 835c8acbab
commit 178a11326e
4 changed files with 53 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
XilinxProcessorIPLib/drivers/dp/src/xdp.h
View file

@ -136,7 +136,9 @@
/******************************* Include Files ********************************/
#include "xil_assert.h"
#include "xil_types.h"
#include "xvidc.h"
/* xdprx.h and xdptx.h are included. They require some type definitions. */
/****************************** Type Definitions ******************************/

36
XilinxProcessorIPLib/drivers/dp/src/xdprx.c
View file

@ -139,6 +139,10 @@ u32 XDprx_InitializeRx(XDprx *InstancePtr)
{
u32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Disable the main link. */
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x00);
@ -214,6 +218,10 @@ u32 XDprx_CheckLinkStatus(XDprx *InstancePtr)
u8 LaneCount;
u8 LaneStatus[2];
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
LaneCount = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
XDPRX_DPCD_LANE_COUNT_SET);
@ -253,6 +261,10 @@ u32 XDprx_CheckLinkStatus(XDprx *InstancePtr)
*******************************************************************************/
void XDprx_DtgEn(XDprx *InstancePtr)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x01);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x00);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x01);
@ -271,6 +283,10 @@ void XDprx_DtgEn(XDprx *InstancePtr)
*******************************************************************************/
void XDprx_DtgDis(XDprx *InstancePtr)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x00);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x01);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x00);
@ -295,6 +311,13 @@ void XDprx_DtgDis(XDprx *InstancePtr)
*******************************************************************************/
void XDprx_SetLinkRate(XDprx *InstancePtr, u8 LinkRate)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((LinkRate == XDPRX_LINK_BW_SET_162GBPS) ||
(LinkRate == XDPRX_LINK_BW_SET_270GBPS) ||
(LinkRate == XDPRX_LINK_BW_SET_540GBPS));
InstancePtr->LinkConfig.LinkRate = LinkRate;
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
@ -322,6 +345,13 @@ void XDprx_SetLinkRate(XDprx *InstancePtr, u8 LinkRate)
*******************************************************************************/
void XDprx_SetLaneCount(XDprx *InstancePtr, u8 LaneCount)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((LaneCount == XDPRX_LANE_COUNT_SET_1) ||
(LaneCount == XDPRX_LANE_COUNT_SET_2) ||
(LaneCount == XDPRX_LANE_COUNT_SET_4));
InstancePtr->LinkConfig.LaneCount = LaneCount;
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
@ -349,6 +379,12 @@ void XDprx_SetLaneCount(XDprx *InstancePtr, u8 LaneCount)
*******************************************************************************/
void XDprx_SetUserPixelWidth(XDprx *InstancePtr, u8 UserPixelWidth)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((UserPixelWidth == 1) || (UserPixelWidth == 2) ||
(UserPixelWidth == 4));
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_USER_PIXEL_WIDTH,
UserPixelWidth);

15
XilinxProcessorIPLib/drivers/dp/src/xdprx_intr.c
View file

@ -75,6 +75,9 @@ void XDprx_InterruptHandler(XDprx *InstancePtr)
IntrTrainingLost, IntrVideo, IntrTrainingDone, IntrBwChange,
IntrTp1, IntrTp2, IntrTp3;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Determine what kind of interrupt(s) occurred.
* Note: XDPRX_INTERRUPT_CAUSE is an RC (read-clear) register. */
IntrStatus = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
@ -168,6 +171,10 @@ void XDprx_InterruptHandler(XDprx *InstancePtr)
*******************************************************************************/
void XDprx_GenerateHpdInterrupt(XDprx *InstancePtr, u16 DurationUs)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_HPD_INTERRUPT,
(DurationUs << 16) | 0x1);
}
@ -189,6 +196,10 @@ void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask)
{
u32 MaskVal;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
MaskVal = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
XDPRX_INTERRUPT_CAUSE);
MaskVal &= ~Mask;
@ -213,6 +224,10 @@ void XDprx_InterruptDisable(XDprx *InstancePtr, u32 Mask)
{
u32 MaskVal;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
MaskVal = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
XDPRX_INTERRUPT_CAUSE);
MaskVal |= Mask;

3
XilinxProcessorIPLib/drivers/dp/src/xdptx.h
View file

@ -173,9 +173,6 @@
#include "xdp.h"
#include "xdptx_hw.h"
#include "xil_assert.h"
#include "xil_types.h"
#include "xvidc.h"
/****************************** Type Definitions ******************************/