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emacps: modification has been done with respect to versioin id register

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This patch has modified source code  of emacps driver on
Zynq and Zynq ultrascale MP

Signed-off-by: Om Mishra <omprakas@xilinx.com>
This commit is contained in:
Om Mishra 2015-01-13 14:34:22 +05:30 • committed by Nava kishore Manne
parent 8333590e2d
commit 1a70cab8c3
2 changed files with 7 additions and 7 deletions
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8
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
View file

@ -198,7 +198,7 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
(u32)XEMACPS_IXR_TXCOMPL_MASK)); (u32)XEMACPS_IXR_TXCOMPL_MASK));
/* Enable TX Q1 Interrupts */ /* Enable TX Q1 Interrupts */
if (InstancePtr->Version == 7) if (InstancePtr->Version > 2)
XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
/* Mark as started */ /* Mark as started */
@ -317,7 +317,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
((u32)XEMACPS_NWCFG_100_MASK | ((u32)XEMACPS_NWCFG_100_MASK |
(u32)XEMACPS_NWCFG_FDEN_MASK | (u32)XEMACPS_NWCFG_FDEN_MASK |
(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK)); (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK));
if (InstancePtr->Version == 7) { if (InstancePtr->Version > 2) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
XEMACPS_NWCFG_DWIDTH_64_MASK)); XEMACPS_NWCFG_DWIDTH_64_MASK));
@ -336,7 +336,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
/* Single bursts */ /* Single bursts */
/* FIXME: Why Single bursts? */ /* FIXME: Why Single bursts? */
if (InstancePtr->Version == 7) { if (InstancePtr->Version > 2) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
(u32)XEMACPS_DMACR_INCR4_AHB_BURST)); (u32)XEMACPS_DMACR_INCR4_AHB_BURST));
@ -352,7 +352,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
XEMACPS_TXSR_OFFSET, 0x0U); XEMACPS_TXSR_OFFSET, 0x0U);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
if (InstancePtr->Version == 7) if (InstancePtr->Version > 2)
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);

6
XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c
View file

@ -162,7 +162,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
/* Read Transmit Q1 ISR */ /* Read Transmit Q1 ISR */
if (InstancePtr->Version == 7) if (InstancePtr->Version > 2)
RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET); XEMACPS_INTQ1_STS_OFFSET);
@ -182,7 +182,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
} }
/* Transmit Q1 complete interrupt */ /* Transmit Q1 complete interrupt */
if ((InstancePtr->Version == 7) && if ((InstancePtr->Version > 2) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) { ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register TX complete indication but preserve /* Clear TX status register TX complete indication but preserve
* error bits if there is any */ * error bits if there is any */
@ -235,7 +235,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
* Have to distinguish this bit to handle the real error condition. * Have to distinguish this bit to handle the real error condition.
*/ */
/* Transmit Q1 error conditions interrupt */ /* Transmit Q1 error conditions interrupt */
if ((InstancePtr->Version == 7) && if ((InstancePtr->Version > 2) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) && ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) { ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear Interrupt Q1 status register */ /* Clear Interrupt Q1 status register */