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tpg: Deprecated tpg_v2_0.

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Added new active driver tpg_v3_0.

Signed-off-by: Durga challa <vnsldurg@xilinx.com>
This commit is contained in:
Durga challa 2014-07-08 12:53:46 +05:30 • committed by Jagannadha Sutradharudu Teki
parent 05efb502f0
commit 1d84de041d
7 changed files with 620 additions and 0 deletions
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44
XilinxProcessorIPLib/drivers/tpg/data/tpg.mdd Executable file
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##############################################################################
#
# Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
##############################################################################
OPTION psf_version = 2.1;
BEGIN driver tpg
OPTION supported_peripherals = (v_tpg);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 3.0;
OPTION NAME = tpg;
END driver

42
XilinxProcessorIPLib/drivers/tpg/data/tpg.tcl Executable file
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##############################################################################
#
# Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
##############################################################################
#
# MODIFICATION HISTORY:
# Ver Who Date Changes
# -------- ------ -------- ------------------------------------
# 2.0 adk 12/10/13 Updated as per the New Tcl API's
###############################################################
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "tpg" "C_BASEADDR" "C_HIGHADDR"
xdefine_canonical_xpars $drv_handle "xparameters.h" "tpg" "C_BASEADDR" "C_HIGHADDR"
}

86
XilinxProcessorIPLib/drivers/tpg/examples/example.c Executable file
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/*****************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*****************************************************************************/
/**
*
* @file example.c
*
* This file demonstrates how to use Xilinx Test Pattern Generator (TPG)
* ore pcore driver functions.
*
*
* ***************************************************************************
*/
#include "tpg.h"
#include "xparameters.h"
/***************************************************************************/
// Test Pattern Generator Register Reading Example
// This function provides an example of how to read the current configuration
// settings of the TPG core.
/***************************************************************************/
void report_tpg_settings(u32 BaseAddress) {
u32 status, reg_val;
unsigned char inchar=0;
xil_printf("Test Pattern Generator Core Configuration:\r\n");
xil_printf(" Enable Bit: %1d\r\n", TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_CTL_EN_MASK);
xil_printf(" Register Update Bit: %1d\r\n", (TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_CTL_RUE_MASK) >> 1);
xil_printf(" Reset Bit: %1d\r\n", TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_RST_RESET);
status = TPG_ReadReg(BaseAddress, TPG_STATUS);
xil_printf(" TPG Status: %08x \r\n", status);
xil_printf(" Core Version: %1d.%1d\r\n", TPG_ReadReg(BaseAddress, TPG_VERSION));
reg_val = TPG_ReadReg(BaseAddress, TPG_CONTROL );
xil_printf("TPG_CONTROL : %8x\r\n", reg_val);
reg_val = TPG_ReadReg(BaseAddress, TPG_IRQ_EN );
xil_printf("TPG_IRQ_EN : %8x\r\n", reg_val);
reg_val = (TPG_ReadReg(BaseAddress, TPG_ACTIVE_SIZE ) && 0x1FFF);
xil_printf("Active Rows : %8d\r\n", reg_val);
reg_val = (TPG_ReadReg(BaseAddress, TPG_ACTIVE_SIZE) >> 16);
xil_printf("Active Columns : %8d\r\n", reg_val);
xil_printf("Press Space to continue!\r\n", reg_val);
while (inchar != ' ') inchar = inbyte();
}
/*****************************************************************************/
//
// This is the main function for the TPG example.
//
/*****************************************************************************/
int main(void)
{
// Print the current settings for the TPG core
report_tpg_settings(XPAR_TPG_0_BASEADDR);
return 0;
}

17
XilinxProcessorIPLib/drivers/tpg/examples/index.html Executable file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<html>
<head>
<meta http-equiv="Content-Language" content="en-us">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Driver example applications</title>
<link rel="stylesheet" type="text/css" href="../help.css">
</head>
<body bgcolor="#FFFFFF">
<h1> Example Applications for the driver tpg_v2_0 </h1>
<HR>
<ul>
<li>example.c <a href="example.c">(source)</a> </li>
</ul>
<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
</body>
</html>

29
XilinxProcessorIPLib/drivers/tpg/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling tpg"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

53
XilinxProcessorIPLib/drivers/tpg/src/tpg.c Executable file
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/*****************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*****************************************************************************/
/**
*
* @file tpg.c
*
* This is the body of the Xilinx Test Pattern Generator
* (tpg) core driver. Most of the driver functionality is implemented as
* macros in the tpg.h header file.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a se 10/01/12 Initial creation
* 2.0 se 01/24/13 Cleaned up comments
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "tpg.h"
#include "xenv.h"

349
XilinxProcessorIPLib/drivers/tpg/src/tpg.h Executable file
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/*****************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*****************************************************************************/
/**
*
* @file tpg.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx Test Pattern Generator
* (TPG) core instance.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a se 10/01/12 Initial creation
* 2.0a se 02/12/14 Cleaned up comments, updated masks and registers
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/
#ifndef TPG_DRIVER_H /* prevent circular inclusions */
#define TPG_DRIVER_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
* Register Offsets
*/
/* General Control Registers */
#define TPG_CONTROL 0x000 /**< Control (R/W) */
#define TPG_STATUS 0x004 /**< Status (R/W) */
#define TPG_ERROR 0x008 /**< Error (R/W) */
#define TPG_IRQ_EN 0x00C /**< IRQ Enable */
#define TPG_VERSION 0x010 /**< Version */
/* Timing Control Registers */
#define TPG_ACTIVE_SIZE 0x020 /**< Active Size (V x H) */
/* Core Specific Registers */
#define TPG_PATTERN_CONTROL 0x100
#define TPG_MOTION_SPEED 0x104
#define TPG_CROSS_HAIRS 0x108
#define TPG_ZPLATE_HOR_CONTROL 0x10C
#define TPG_ZPLATE_VER_CONTROL 0x110
#define TPG_BOX_SIZE 0x114
#define TPG_BOX_COLOR 0x118
#define TPG_STUCK_PIXEL_THRESH 0x11C
#define TPG_NOISE_GAIN 0x120
#define TPG_BAYER_PHASE 0x124
/**
* TPG Control Register bit definition
*/
#define TPG_CTL_EN_MASK 0x00000001 /**< TPG Enable */
#define TPG_CTL_RUE_MASK 0x00000002 /**< TPG Register Update */
#define TPG_CTL_CS_MASK 0x00000004 /**< TPG Register Clear Status */
/**
* TPG Reset Register bit definition
*/
#define TPG_RST_RESET 0x80000000 /**< Software Reset - Instantaneous */
#define TPG_RST_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */
/**
* TPG Pattern Control Register bit definition
*/
#define TPG_PASS_THROUGH 0x00000000
#define TPG_HOR_RAMP 0x00000001
#define TPG_VER_RAMP 0x00000002
#define TPG_TEMP_RAMP 0x00000003
#define TPG_SOLID_RED 0x00000004
#define TPG_SOLID_GREEN 0x00000005
#define TPG_SOLID_BLUE 0x00000006
#define TPG_SOILD_BLACK 0x00000007
#define TPG_SOLID_WHITE 0x00000008
#define TPG_COLOR_BARS 0x00000009
#define TPG_ZONE_PLATE 0x0000000A
#define TPG_TARTAN_BARS 0x0000000B
#define TPG_CROSS_HATCH 0x0000000C
#define TPG_VER_HOR_RAMP 0x0000000E
#define TPG_CHECKER_BOARD 0x0000000F
#define TPG_CROSS_HAIRS 0x00000010
#define TPG_MOVING_BOX 0x00000020
#define TPG_MASK_RED_CR 0x00000040
#define TPG_MASK_GREEN_Y 0x00000080
#define TPG_MASK_BLUE_CB 0x00000100
#define TPG_ENABLE_STUCK 0x00000200
#define TPG_ENABLE_NOISE 0x00000400
#define TPG_ENABLE_MOTION 0x00001000
/***************** Macros (Inline Functions) Definitions *********************/
#define TPG_In32 Xil_In32
#define TPG_Out32 Xil_Out32
/**
*
* Read the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 TPG_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define TPG_ReadReg(BaseAddress, RegOffset) \
TPG_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void TPG_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define TPG_WriteReg(BaseAddress, RegOffset, Data) \
TPG_Out32((BaseAddress) + (RegOffset), (Data))
/*****************************************************************************/
/**
*
* This macro enables a TPG core instance.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Enable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Enable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) | \
TPG_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro disables a TPG core instance.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Disable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Disable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) & \
~TPG_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro commits all the register value changes made so far by the software
* to the TPG core instance. The registers will be automatically updated
* on the next rising-edge of the VBlank_in signal on the core.
* It is up to the user to manually disable the register update after a sufficient
* amount if time.
*
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_RegUpdateEnable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_RegUpdateEnable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) | \
TPG_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro prevents the TPG core instance from committing recent changes made
* so far by the software. When disabled, changes to other configuration registers
* are stored, but do not effect the behavior of the core.
*
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_RegUpdateDisable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_RegUpdateDisable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) & \
~TPG_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro clears the status register of the TPG instance, by first asserting then
* deasserting the CLEAR_STATUS flag of TPG_CONTROL.
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_ClearStatus(u32 BaseAddress);
*
******************************************************************************/
#define TPG_ClearStatus(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_ReadReg(BaseAddress, TPG_CONTROL) | TPG_CTL_CS_MASK); \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_ReadReg(BaseAddress, TPG_CONTROL) & ~TPG_CTL_CS_MASK)
/*****************************************************************************/
/**
*
* This macro resets a TPG core instance. This reset effects the core immediately,
* and may cause image tearing.
*
* This reset resets the TPG's configuration registers, and holds the core's outputs
* in their reset state until TPG_ClearReset() is called.
*
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Reset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Reset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_RST_RESET) \
/*****************************************************************************/
/**
*
* This macro clears the TPG's reset flag (which is set using TPG_Reset(), and
* returns it to normal operation. This ClearReset effects the core immediately,
* and may cause image tearing.
*
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_ClearReset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_ClearReset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, 0) \
/*****************************************************************************/
/**
*
* This macro resets a TPG instance, but differs from TPG_Reset() in that it
* automatically synchronizes to the SOF of the core to prevent tearing.
*
* On the next rising-edge of SOF following a call to TPG_AutoSyncReset(),
* all of the core's configuration registers and outputs will be reset, then the
* reset flag will be immediately released, allowing the core to immediately resume
* default operation.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_FSyncReset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_FSyncReset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_RST_AUTORESET) \
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */