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ttcps : Modified ttcps driver for MISRA-C:2012

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This patch modifies ttcps driver for misrac rules.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2014-12-10 16:30:37 +05:30 • committed by Nava kishore Manne
parent 24e482ef1a
commit 1f7ca1df87
7 changed files with 166 additions and 149 deletions
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117
XilinxProcessorIPLib/drivers/ttcps/src/xttcps.c
View file

@ -101,9 +101,11 @@
* initialize it. * initialize it.
* *
******************************************************************************/ ******************************************************************************/
int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
u32 EffectiveAddr) u32 EffectiveAddr)
{ {
s32 Status;
u32 IsStartResult;
/* /*
* Assert to validate input arguments. * Assert to validate input arguments.
*/ */
@ -117,47 +119,48 @@ int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
InstancePtr->Config.BaseAddress = EffectiveAddr; InstancePtr->Config.BaseAddress = EffectiveAddr;
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
IsStartResult = XTtcPs_IsStarted(InstancePtr);
/* /*
* If the timer counter has already started, return an error * If the timer counter has already started, return an error
* Device should be stopped first. * Device should be stopped first.
*/ */
if(XTtcPs_IsStarted(InstancePtr)) { if(IsStartResult == (u32)TRUE) {
return XST_DEVICE_IS_STARTED; Status = XST_DEVICE_IS_STARTED;
} else {
/*
* Reset the count control register to it's default value.
*/
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_CNT_CNTRL_OFFSET,
XTTCPS_CNT_CNTRL_RESET_VALUE);
/*
* Reset the rest of the registers to the default values.
*/
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_1_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_2_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_2_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_IER_OFFSET, 0x00U);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
/*
* Reset the counter value
*/
XTtcPs_ResetCounterValue(InstancePtr);
Status = XST_SUCCESS;
} }
return Status;
/*
* Reset the count control register to it's default value.
*/
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_CNT_CNTRL_OFFSET,
XTTCPS_CNT_CNTRL_RESET_VALUE);
/*
* Reset the rest of the registers to the default values.
*/
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_CLK_CNTRL_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_INTERVAL_VAL_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_1_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_2_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_MATCH_2_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_IER_OFFSET, 0x00);
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
/*
* Reset the counter value
*/
XTtcPs_ResetCounterValue(InstancePtr);
return XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -188,7 +191,7 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(MatchIndex < XTTCPS_NUM_MATCH_REG); Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
/* /*
* Write the value to the correct match register with MatchIndex * Write the value to the correct match register with MatchIndex
@ -275,9 +278,9 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
/* /*
* Set the prescaler value and enable prescaler * Set the prescaler value and enable prescaler
*/ */
ClockReg |= (PrescalerValue << XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) & ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
XTTCPS_CLK_CNTRL_PS_VAL_MASK; (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
ClockReg |= XTTCPS_CLK_CNTRL_PS_EN_MASK; ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
} }
/* /*
@ -311,6 +314,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
****************************************************************************/ ****************************************************************************/
u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr) u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
{ {
u8 Status;
u32 ClockReg; u32 ClockReg;
/* /*
@ -329,11 +333,14 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
/* /*
* Prescaler is disabled. Return the correct flag value * Prescaler is disabled. Return the correct flag value
*/ */
return XTTCPS_CLK_CNTRL_PS_DISABLE; Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
} }
else {
return ((ClockReg & XTTCPS_CLK_CNTRL_PS_VAL_MASK) >> Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
XTTCPS_CLK_CNTRL_PS_VAL_SHIFT); (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
}
return Status;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -374,41 +381,41 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
*/ */
TempValue = InputClock/ Freq; TempValue = InputClock/ Freq;
if (TempValue < 4) { if (TempValue < 4U) {
/* /*
* The frequency is too high, it is too close to the input * The frequency is too high, it is too close to the input
* clock value. Use maximum values to signal caller. * clock value. Use maximum values to signal caller.
*/ */
*Interval = 0xFFFF; *Interval = 0xFFFFU;
*Prescaler = 0xFF; *Prescaler = 0xFFU;
return; return;
} }
/* /*
* First, do we need a prescaler or not? * First, do we need a prescaler or not?
*/ */
if (65536 > TempValue) { if (((u32)65536U) > TempValue) {
/* /*
* We do not need a prescaler, so set the values appropriately * We do not need a prescaler, so set the values appropriately
*/ */
*Interval = TempValue; *Interval = (u16)TempValue;
*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE; *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
return; return;
} }
for (TmpPrescaler = 0; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE; for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
TmpPrescaler++) { TmpPrescaler++) {
TempValue = InputClock/ (Freq * (1 << (TmpPrescaler + 1))); TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
/* /*
* The first value less than 2^16 is the best bet * The first value less than 2^16 is the best bet
*/ */
if (65536 > TempValue) { if (((u32)65536U) > TempValue) {
/* /*
* Set the values appropriately * Set the values appropriately
*/ */
*Interval = TempValue; *Interval = (u16)TempValue;
*Prescaler = TmpPrescaler; *Prescaler = TmpPrescaler;
return; return;
} }
@ -417,8 +424,8 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/* Can not find interval values that work for the given frequency. /* Can not find interval values that work for the given frequency.
* Return maximum values to signal caller. * Return maximum values to signal caller.
*/ */
*Interval = 0XFFFF; *Interval = 0XFFFFU;
*Prescaler = 0XFF; *Prescaler = 0XFFU;
return; return;
} }

30
XilinxProcessorIPLib/drivers/ttcps/src/xttcps.h
View file

@ -112,14 +112,14 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XTTCPS_OPTION_EXTERNAL_CLK 0x0001 /**< External clock source */ #define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
#define XTTCPS_OPTION_CLK_EDGE_NEG 0x0002 /**< Clock on trailing edge for #define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
external clock*/ external clock*/
#define XTTCPS_OPTION_INTERVAL_MODE 0x0004 /**< Interval mode */ #define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
#define XTTCPS_OPTION_DECREMENT 0x0008 /**< Decrement the counter */ #define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
#define XTTCPS_OPTION_MATCH_MODE 0x0010 /**< Match mode */ #define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
#define XTTCPS_OPTION_WAVE_DISABLE 0x0020 /**< No waveform output */ #define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
#define XTTCPS_OPTION_WAVE_POLARITY 0x0040 /**< Waveform polarity */ #define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
/*@}*/ /*@}*/
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@ -151,10 +151,10 @@ typedef struct {
* Internal helper macros * Internal helper macros
*/ */
#define InstReadReg(InstancePtr, RegOffset) \ #define InstReadReg(InstancePtr, RegOffset) \
(Xil_In32(((InstancePtr)->Config.BaseAddress) + (RegOffset))) (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
#define InstWriteReg(InstancePtr, RegOffset, Data) \ #define InstWriteReg(InstancePtr, RegOffset, Data) \
(Xil_Out32(((InstancePtr)->Config.BaseAddress) + (RegOffset), (Data))) (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -208,8 +208,8 @@ typedef struct {
* *
****************************************************************************/ ****************************************************************************/
#define XTtcPs_IsStarted(InstancePtr) \ #define XTtcPs_IsStarted(InstancePtr) \
(int)((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
XTTCPS_CNT_CNTRL_DIS_MASK) == 0) XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -280,7 +280,7 @@ typedef struct {
#define XTtcPs_ResetCounterValue(InstancePtr) \ #define XTtcPs_ResetCounterValue(InstancePtr) \
InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
XTTCPS_CNT_CNTRL_RST_MASK)) (u32)XTTCPS_CNT_CNTRL_RST_MASK))
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -377,7 +377,7 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
/* /*
* Required functions, in xttcps.c * Required functions, in xttcps.c
*/ */
int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
@ -392,13 +392,13 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/* /*
* Functions for options, in file xttcps_options.c * Functions for options, in file xttcps_options.c
*/ */
int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options); s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
u32 XTtcPs_GetOptions(XTtcPs *InstancePtr); u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
/* /*
* Function for self-test, in file xttcps_selftest.c * Function for self-test, in file xttcps_selftest.c
*/ */
int XTtcPs_SelfTest(XTtcPs *InstancePtr); s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
#ifdef __cplusplus #ifdef __cplusplus
} }

36
XilinxProcessorIPLib/drivers/ttcps/src/xttcps_g.c
View file

@ -73,47 +73,47 @@
*/ */
XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES] = { XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES] = {
{ {
XPAR_XTTCPS_0_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_0_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_0_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_0_BASEADDR, /* Device base address */
XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ /* Device input clock frequency */
}, },
#ifdef XPAR_XTTCPS_1_DEVICE_ID #ifdef XPAR_XTTCPS_1_DEVICE_ID
{ {
XPAR_XTTCPS_1_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_1_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_1_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_1_BASEADDR, /* Device base address */
XPAR_XTTCPS_1_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_1_CLOCK_HZ /* Device input clock frequency */
}, },
#endif #endif
#ifdef XPAR_XTTCPS_2_DEVICE_ID #ifdef XPAR_XTTCPS_2_DEVICE_ID
{ {
XPAR_XTTCPS_2_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_2_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_2_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_2_BASEADDR, /* Device base address */
XPAR_XTTCPS_2_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_2_CLOCK_HZ /* Device input clock frequency */
}, },
#endif #endif
#ifdef XPAR_XTTCPS_3_DEVICE_ID #ifdef XPAR_XTTCPS_3_DEVICE_ID
{ {
XPAR_XTTCPS_3_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_3_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_3_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_3_BASEADDR, /* Device base address */
XPAR_XTTCPS_3_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_3_CLOCK_HZ /* Device input clock frequency */
}, },
#endif #endif
#ifdef XPAR_XTTCPS_4_DEVICE_ID #ifdef XPAR_XTTCPS_4_DEVICE_ID
{ {
XPAR_XTTCPS_4_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_4_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_4_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_4_BASEADDR, /* Device base address */
XPAR_XTTCPS_4_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_4_CLOCK_HZ /* Device input clock frequency */
}, },
#endif #endif
#ifdef XPAR_XTTCPS_5_DEVICE_ID #ifdef XPAR_XTTCPS_5_DEVICE_ID
{ {
XPAR_XTTCPS_5_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XTTCPS_5_DEVICE_ID, /* Device ID for instance */
XPAR_XTTCPS_5_BASEADDR, /* Device base address */ (u32)XPAR_XTTCPS_5_BASEADDR, /* Device base address */
XPAR_XTTCPS_5_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XTTCPS_5_CLOCK_HZ /* Device input clock frequency */
}, },
#endif #endif
}; };

72
XilinxProcessorIPLib/drivers/ttcps/src/xttcps_hw.h
View file

@ -70,48 +70,48 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000 /**< Clock Control Register */ #define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000C /**< Counter Control Register*/ #define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018 /**< Current Counter Value */ #define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024 /**< Interval Count Value */ #define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
#define XTTCPS_MATCH_0_OFFSET 0x00000030 /**< Match 1 value */ #define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
#define XTTCPS_MATCH_1_OFFSET 0x0000003C /**< Match 2 value */ #define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
#define XTTCPS_MATCH_2_OFFSET 0x00000048 /**< Match 3 value */ #define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
#define XTTCPS_ISR_OFFSET 0x00000054 /**< Interrupt Status Register */ #define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
#define XTTCPS_IER_OFFSET 0x00000060 /**< Interrupt Enable Register */ #define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
/* @} */ /* @} */
/** @name Clock Control Register /** @name Clock Control Register
* Clock Control Register definitions * Clock Control Register definitions
* @{ * @{
*/ */
#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */ #define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */ #define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */ #define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
#define XTTCPS_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */ #define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */ #define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */ #define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
/* @} */ /* @} */
/** @name Counter Control Register /** @name Counter Control Register
* Counter Control Register definitions * Counter Control Register definitions
* @{ * @{
*/ */
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */ #define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002 /**< Interval mode */ #define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */ #define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */ #define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */ #define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */ #define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */ #define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */ #define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
/* @} */ /* @} */
/** @name Current Counter Value Register /** @name Current Counter Value Register
* Current Counter Value Register definitions * Current Counter Value Register definitions
* @{ * @{
*/ */
#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFF /**< 16-bit counter value */ #define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
/* @} */ /* @} */
/** @name Interval Value Register /** @name Interval Value Register
@ -119,7 +119,7 @@ extern "C" {
* down to. * down to.
* @{ * @{
*/ */
#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFF /**< 16-bit Interval value*/ #define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
/* @} */ /* @} */
/** @name Match Registers /** @name Match Registers
@ -127,8 +127,8 @@ extern "C" {
* registers. * registers.
* @{ * @{
*/ */
#define XTTCPS_MATCH_MASK 0x0000FFFF /**< 16-bit Match value */ #define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
#define XTTCPS_NUM_MATCH_REG 3 /**< Num of Match reg */ #define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
/* @} */ /* @} */
/** @name Interrupt Registers /** @name Interrupt Registers
@ -136,12 +136,12 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001 /**< Interval Interrupt */ #define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */ #define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */ #define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */ #define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */ #define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
#define XTTCPS_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */ #define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
/* @} */ /* @} */
@ -162,7 +162,7 @@ extern "C" {
* *
*****************************************************************************/ *****************************************************************************/
#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ #define XTtcPs_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset))) (Xil_In32((BaseAddress) + (u32)(RegOffset)))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -181,7 +181,7 @@ extern "C" {
* *
*****************************************************************************/ *****************************************************************************/
#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ #define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data))) (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -197,7 +197,7 @@ extern "C" {
* *
*****************************************************************************/ *****************************************************************************/
#define XTtcPs_Match_N_Offset(MatchIndex) \ #define XTtcPs_Match_N_Offset(MatchIndex) \
(XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex))) ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/

37
XilinxProcessorIPLib/drivers/ttcps/src/xttcps_options.c
View file

@ -116,11 +116,12 @@ static OptionsMap TmrCtrOptionsTable[] = {
* @note None * @note None
* *
******************************************************************************/ ******************************************************************************/
int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options) s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
{ {
u32 CountReg; u32 CountReg;
u32 ClockReg; u32 ClockReg;
unsigned Index; u32 Index;
s32 Status = XST_SUCCESS;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -134,8 +135,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
* Loop through the options table, turning the option on or off * Loop through the options table, turning the option on or off
* depending on whether the bit is set in the incoming options flag. * depending on whether the bit is set in the incoming options flag.
*/ */
for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) { for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
if (Options & TmrCtrOptionsTable[Index].Option) { if(Status != (s32)XST_FAILURE) {
if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
switch (TmrCtrOptionsTable[Index].Register) { switch (TmrCtrOptionsTable[Index].Register) {
@ -150,7 +152,8 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
break; break;
default: default:
return XST_FAILURE; Status = XST_FAILURE;
break;
} }
} }
else { else {
@ -167,7 +170,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
break; break;
default: default:
return XST_FAILURE; Status = XST_FAILURE;
break;
}
} }
} }
} }
@ -176,12 +181,14 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
* Now write the registers. Leave it to the upper layers to restart the * Now write the registers. Leave it to the upper layers to restart the
* device. * device.
*/ */
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, if (Status != (s32)XST_FAILURE ) {
XTTCPS_CLK_CNTRL_OFFSET, ClockReg); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
XTTCPS_CNT_CNTRL_OFFSET, CountReg); XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
XTTCPS_CNT_CNTRL_OFFSET, CountReg);
}
return XST_SUCCESS; return Status;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -203,9 +210,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
******************************************************************************/ ******************************************************************************/
u32 XTtcPs_GetOptions(XTtcPs *InstancePtr) u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
{ {
u32 OptionsFlag = 0; u32 OptionsFlag = 0U;
u32 Register; u32 Register;
unsigned Index; u32 Index;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -214,7 +221,7 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
/* /*
* Loop through the options table to determine which options are set * Loop through the options table to determine which options are set
*/ */
for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) { for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
/* /*
* Get the control register to determine which options are * Get the control register to determine which options are
* currently set. * currently set.
@ -223,7 +230,7 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
TmrCtrOptionsTable[Index]. TmrCtrOptionsTable[Index].
Register); Register);
if (Register & TmrCtrOptionsTable[Index].Mask) { if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
OptionsFlag |= TmrCtrOptionsTable[Index].Option; OptionsFlag |= TmrCtrOptionsTable[Index].Option;
} }
} }

13
XilinxProcessorIPLib/drivers/ttcps/src/xttcps_selftest.c
View file

@ -82,8 +82,9 @@
* @note This test fails if it is not called right after initialization. * @note This test fails if it is not called right after initialization.
* *
******************************************************************************/ ******************************************************************************/
int XTtcPs_SelfTest(XTtcPs *InstancePtr) s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
{ {
s32 Status;
u32 TempReg; u32 TempReg;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
@ -94,9 +95,11 @@ int XTtcPs_SelfTest(XTtcPs *InstancePtr)
*/ */
TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
XTTCPS_CNT_CNTRL_OFFSET); XTTCPS_CNT_CNTRL_OFFSET);
if (XTTCPS_CNT_CNTRL_RESET_VALUE != TempReg) { if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
return XST_FAILURE; Status = XST_FAILURE;
} }
else {
return XST_SUCCESS; Status = XST_SUCCESS;
}
return Status;
} }

10
XilinxProcessorIPLib/drivers/ttcps/src/xttcps_sinit.c
View file

@ -48,8 +48,8 @@
/***************************** Include Files *********************************/ /***************************** Include Files *********************************/
#include "xparameters.h"
#include "xttcps.h" #include "xttcps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/ /************************** Constant Definitions *****************************/
@ -60,7 +60,7 @@
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/ /************************** Variable Definitions *****************************/
extern XTtcPs_Config XTtcPs_ConfigTable[]; extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -81,14 +81,14 @@ extern XTtcPs_Config XTtcPs_ConfigTable[];
XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId) XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
{ {
XTtcPs_Config *CfgPtr = NULL; XTtcPs_Config *CfgPtr = NULL;
unsigned Index; u32 Index;
for (Index = 0; Index < XPAR_XTTCPS_NUM_INSTANCES; Index++) { for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) { if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XTtcPs_ConfigTable[Index]; CfgPtr = &XTtcPs_ConfigTable[Index];
break; break;
} }
} }
return CfgPtr; return (XTtcPs_Config *)CfgPtr;
} }