dp: rx: Added file header documentation.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion
Nava kishore Manne
parent
ff3f15acbb
commit
249af540c6
5 changed files with 85 additions and 157 deletions
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@ -34,9 +34,9 @@
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*
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* @file xdp.h
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*
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* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
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* DisplayPort 1.2a specification.
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* The Xilinx DisplayPort transmitter (DP) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in both transmit/source (TX) and receive/sink
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* (RX) modes of operation.
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*
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* The Xilinx DisplayPort soft IP supports the following features:
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* - 1, 2, or 4 lanes.
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@ -73,94 +73,42 @@
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* DisplayPort connection exists between the DisplayPort TX connector and
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* an RX device. It is serves as an interrupt request by the RX device.
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*
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* <b>Driver description</b>
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*
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* The device driver enables higher-level software (e.g., an application) to
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* configure and control a DisplayPort TX soft IP, communicate and control an
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* RX device/sink monitor over the AUX channel, and to initialize and transmit
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* data streams over the main link.
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*
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* This driver implements link layer functionality: a Link Policy Maker (LPM)
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* and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
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* - The LPM manages the main link and is responsible for keeping the link
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* synchronized. It will establish a link with a downstream RX device by
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* undergoing a link training sequence which consists of:
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* - Clock recovery: The clock needs to be recovered and PLLs need to be
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* locked for all lanes.
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* - Channel equalization: All lanes need to achieve channel equalization
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* and and symbol lock, as well as for interlane alignment to take place.
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* - The SPM manages transportation of an isochronous stream. That is, it will
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* initialize and maintain a video stream, establish a virtual channel to a
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* sink monitor, and transmit the stream.
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*
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* Using AUX transactions to read/write from/to the sink's DisplayPort
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* Configuration Data (DPCD) address space, the LPM obtains the link
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* capabilities, obtains link configuration and link and sink status, and
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* configures and controls the link and sink. The main link is trained this way.
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*
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* I2C-over-AUX transactions are used to obtain the sink's Extended Display
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* Identification Data (EDID) which give information on the display capabilities
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* of the monitor. The SPM may use this information to determine what available
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* screen resolutions and video timing are possible.
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*
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* <b>Device configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xdptx_g.c file which is
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* process. Configuration parameters are stored in the xdp_g.c file which is
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* generated when compiling the board support package (BSP). A table is defined
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* where each entry contains configuration information for the DisplayPort
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* instances present in the system. This information includes parameters that
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* are defined in the driver's data/dptx.tcl file such as the base address of
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* the memory-mapped device and the maximum number of lanes, maximum link rate,
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* and video interface that the DisplayPort instance supports, among others.
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* are defined in the driver's data/dp.tcl file such as the base address of the
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* memory-mapped device and the maximum number of lanes, maximum link rate, and
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* video interface that the DisplayPort instance supports, among others.
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*
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* <b>Interrupt processing</b>
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* The DisplayPort core may be configured in both transmitter (TX) or receiver
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* (RX) modes of operation. Depending on which mode of operation the hardware is
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* configured for, the set of registers associated with the core will be
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* different.
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*
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* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
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* cable is connected/disconnected or when the RX device sends a pulse. The user
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* hardware design must contain an interrupt controller which the DisplayPort
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* TX instance's interrupt signal is connected to. The user application must
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* enable interrupts in the system and set up the interrupt controller such that
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* the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
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* When the XDptx_HpdInterruptHandler function is invoked, the handler will
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* identify what type of DisplayPort interrupt has occurred, and will call
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* either the HPD event handler function or the HPD pulse handler function,
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* depending on whether a an HPD event on an HPD pulse event occurred.
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* <b>Driver description</b>
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*
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* The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of
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* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
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* information to decide which handler to call. An HPD event is identified if
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* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
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* identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
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* The DisplayPort (DP) driver consists of functions, structures, and
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* definitions:
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* 1) Specific to the DisplayPort TX mode of operation.
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* - Prefix: XDptx_* and XDPTX_*
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* 2) Specific to the DisplayPort RX mode of operation.
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* - Prefix: XDprx_* and XDPRX_*
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* 3) Common to both DisplayPort modes of operation.
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* - Prefix: XDp_* and XDP_*
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*
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* The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
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* function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
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* function.
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*
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* <b>Multi-stream transport (MST) mode</b>
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*
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* The driver handles MST mode functionality, including sideband messaging,
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* topology discovery, virtual channel payload ID table management, and
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* directing streams to different sinks.
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*
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* MST testing has been done at all possible link rate/lane count/topology/
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* resolution/color depth combinations with each setting using following values:
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* - Link rate: 1.62, 2.70, and 5.40Gbps per lane.
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* - Lane count: 1, 2, and 4 lanes.
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* - Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain
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* configuration and in a configuration using a combination of a 1-to-3 hub
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* and daisy-chain. Each stream was using the same resolution.
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* - Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024,
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* 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.
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* - Color depths: 18, 24, 30, 36, and 48 bits per pixel.
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*
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* <b>Audio</b>
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*
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* The driver does not handle audio. For an example as to how to configure and
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* transmit audio, examples/xdptx_audio_example.c illustrates the required
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* sequence. The user will need to configure the audio source connected to the
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* Displayport TX instance and set up the audio info frame as per user
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* requirements.
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* Depending on whether the DisplayPort core is configured for TX or RX mode of
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* operation, the set of registers and required functionality will be entirely
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* different.
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* - A detailed description of the DisplayPort TX functionality and
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* associated functions may be found in xdptx.h. xdptx_hw.h contains
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* definitions of the TX register space.
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* - A detailed description of the DisplayPort RX functionality and
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* associated functions may be found in xdprx.h. xdprx_hw.h contains
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* definitions of the RX register space.
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*
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* <b>Asserts</b>
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*
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@ -170,23 +118,6 @@
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* it is recommended that application developers leave asserts on during
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* development.
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*
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* <b>Limitations</b>
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*
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* - For MST mode to correctly display, the current version of the driver
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* requires that each of the DisplayPort TX streams be allocated without
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* skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems
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* were experienced if skipping stream 2 and assigning stream 4 instead).
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* skipping monitors in a daisy chain is OK as long as they are assigned to
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* streams in order.
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* - In MST mode, the current version of the driver does not support removal of
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* an allocated stream from the virtual channel payload ID table without
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* clearing the entire table.
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* - Some sideband messages have not been implemented in the current version of
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* the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY
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* sideband message.
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* - The driver does not handle audio. See the audio example in the driver
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* examples directory for the required sequence for enabling audio.
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*
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* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
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* required with a speed grade of -2 or -3.
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*
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@ -211,7 +142,7 @@
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/****************************** Type Definitions ******************************/
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/**
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* This typedef contains configuration information for the DisplayPort TX core.
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* This typedef contains configuration information for the DisplayPort core.
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*/
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typedef struct {
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u16 DeviceId; /**< Device instance ID. */
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@ -258,7 +189,7 @@ typedef struct {
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* used, the user may implement their own wait implementation using a hardware
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* timer (see example/) for better accuracy.
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*
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* @param InstancePtr is a pointer to the XDptx instance.
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* @param InstancePtr is a pointer to the XDp instance.
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* @param MicroSeconds is the number of microseconds to be passed to the
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* timer function.
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*
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@ -34,6 +34,10 @@
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*
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* @file xdprx.c
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*
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* Contains a minimal set of functions for the XDprx driver that allow access
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* to all of the DisplayPort RX core's functionality. See xdprx.h for a detailed
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* description of the driver.
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*
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* @note None.
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*
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* <pre>
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@ -34,6 +34,54 @@
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*
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* @file xdprx.h
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*
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* The Xilinx DisplayPort receiver (DPRX) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in receive (RX) mode.
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*
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* <b>Driver description</b>
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*
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* The device driver enables higher-level software (e.g., an application) to
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* configure and control a DisplayPort RX soft IP.
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*
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* This driver gives applications the ability to configure the RX using various
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* settings, handle and issue interrupts, and modify a subset of its DisplayPort
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* Configuration Data (DPCD) fields.
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*
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* <b>Interrupt processing</b>
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*
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* The DisplayPort RX driver may generate a pulse on the hot-plug-detect (HPD)
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* signal line using the XDprx_GenerateHpdInterrupt function. This allows the RX
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* to send an interrupt to the upstream TX device, useful for signaling the TX
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* that it needs to do some checks for changes in downstream devices or a loss
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* of link training.
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*
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* For RX interrupt handling of HPD events or events that happen internal to the
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* RX, the user hardware design must contain an interrupt controller which the
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* DisplayPort RX instance's interrupt signal is connected to. The user
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* application must enable interrupts in the system and set up the interrupt
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* controller such that the XDprx_InterruptHandler handler will service
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* interrupts. When the XDprx_InterruptHandler function is invoked, the handler
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* will identify what type of interrupt has occurred, and will call the
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* appropriate interrupt handler.
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*
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* The DisplayPort RX's XDPRX_INTERRUPT_CAUSE register indicates the type of
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* interrupt that has occured, and the XDprx_InterruptHandler will use this
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* information to decide which handler to call.
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*
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* The handlers are set up using the XDprx_SetIntr* functions.
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*
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* Specific interrupts may be enabled or disabled using the
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* XDprx_InterruptEnable and XDprx_InterruptDisable functions.
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*
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* <b>Multi-stream transport (MST) mode</b>
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*
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* The DisplayPort RX driver does not support MST functionality in 2015.1.
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*
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* <b>Audio</b>
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*
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* The driver does not handle audio.
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*
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* @note None.
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*
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* <pre>
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* MODIFICATION HISTORY:
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* </pre>
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@ -75,7 +75,7 @@ void XDprx_InterruptHandler(XDprx *InstancePtr)
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IntrTp1, IntrTp2, IntrTp3;
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/* Determine what kind of interrupt(s) occurred.
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* Note: XDPRX_INTERRUPT_STATUS is an RC (read-clear) register. */
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* Note: XDPRX_INTERRUPT_CAUSE is an RC (read-clear) register. */
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IntrStatus = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
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XDPRX_INTERRUPT_CAUSE);
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IntrVmChange = (IntrStatus & 0x00001);
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@ -38,41 +38,6 @@
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* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
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* DisplayPort 1.2a specification.
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*
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* The Xilinx DisplayPort soft IP supports the following features:
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* - 1, 2, or 4 lanes.
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* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
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* - 1, 2, or 4 pixel-wide video interfaces.
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* - RGB and YCbCr color space.
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* - Up to 16 bits per component.
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* - Up to 4Kx2K monitor resolution.
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* - Auto lane rate and width negotiation.
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* - I2C over a 1Mb/s AUX channel.
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* - Secondary channel audio support (2 channels).
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* - 4 independent video multi-streams.
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*
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* The Xilinx DisplayPort soft IP does not support the following features:
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* - The automated test feature.
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* - Audio (3-8 channel).
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* - FAUX.
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* - Bridging function.
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* - MST audio.
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* - eDP optional features.
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* - iDP.
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* - GTC.
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*
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* <b>DisplayPort overview</b>
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*
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* A DisplayPort link consists of:
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* - A unidirectional main link which is used to transport isochronous data
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* streams such as video and audio. The main link may use 1, 2, or 4
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* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
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* needs to be trained prior to sending streams.
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* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
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* link training, link management, and device control.
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* - A hot-plug-detect (HPD) signal line is used to determine whether a
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* DisplayPort connection exists between the DisplayPort TX connector and
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* an RX device. It is serves as an interrupt request by the RX device.
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*
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* <b>Driver description</b>
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*
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* The device driver enables higher-level software (e.g., an application) to
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@ -103,17 +68,6 @@
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* of the monitor. The SPM may use this information to determine what available
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* screen resolutions and video timing are possible.
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*
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* <b>Device configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xdptx_g.c file which is
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* generated when compiling the board support package (BSP). A table is defined
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* where each entry contains configuration information for the DisplayPort
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* instances present in the system. This information includes parameters that
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* are defined in the driver's data/dptx.tcl file such as the base address of
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* the memory-mapped device and the maximum number of lanes, maximum link rate,
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* and video interface that the DisplayPort instance supports, among others.
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*
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* <b>Interrupt processing</b>
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*
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* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
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@ -162,14 +116,6 @@
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* Displayport TX instance and set up the audio info frame as per user
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* requirements.
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*
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* <b>Asserts</b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and
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* it is recommended that application developers leave asserts on during
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* development.
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*
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* <b>Limitations</b>
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*
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* - For MST mode to correctly display, the current version of the driver
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@ -187,8 +133,7 @@
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* - The driver does not handle audio. See the audio example in the driver
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* examples directory for the required sequence for enabling audio.
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*
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* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
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* required with a speed grade of -2 or -3.
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* @note None.
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*
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* <pre>
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* MODIFICATION HISTORY:
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