dp: tx: Added PHY polarity inversion option.
Both for all lanes and for individual lane PHY polarity setting. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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2a662e6f48
3 changed files with 120 additions and 1 deletions
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@ -1282,6 +1282,106 @@ void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset)
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1);
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}
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/******************************************************************************/
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/**
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* This function sets the PHY polarity on all lanes.
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*
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* @param InstancePtr is a pointer to the XDp instance.
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* @param Polarity is the value to set for the polarity (0 or 1).
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*
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* @return None.
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*
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* @note The individual PHY polarity option will be disabled if set.
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*
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*******************************************************************************/
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void XDp_TxSetPhyPolarityAll(XDp *InstancePtr, u8 Polarity)
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{
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u32 RegVal;
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertVoid((Polarity == 0) || (Polarity == 1));
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/* Preserve current settings. */
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RegVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG);
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/* Set the polarity. */
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if (Polarity) {
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RegVal |= XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK;
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}
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else {
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RegVal &= ~XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK;
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}
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/* Disable individual polarity setting. */
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RegVal &= ~XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK;
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/* Write the new settings. */
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, RegVal);
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}
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/******************************************************************************/
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/**
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* This function sets the PHY polarity on a specified lane.
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*
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* @param InstancePtr is a pointer to the XDp instance.
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* @param Lane is the lane number (0-3) to set the polarity for.
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* @param Polarity is the value to set for the polarity (0 or 1).
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*
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* @return None.
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*
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* @note If individual lane polarity is used, it is recommended that this
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* function is called for every lane in use.
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*
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*******************************************************************************/
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void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity)
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{
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u32 RegVal;
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u32 MaskVal;
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertVoid((Lane >= 0) && (Lane <= 3));
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Xil_AssertVoid((Polarity == 0) || (Polarity == 1));
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/* Preserve current settings. */
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RegVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG);
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/* Determine bit mask to use. */
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switch (Lane) {
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case 0:
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MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK;
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break;
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case 1:
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MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK;
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break;
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case 2:
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MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK;
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break;
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case 3:
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MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK;
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break;
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default:
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break;
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}
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/* Set the polarity. */
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if (Polarity) {
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RegVal |= MaskVal;
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}
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else {
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RegVal &= ~MaskVal;
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}
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/* Enable individual polarity setting. */
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RegVal |= XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK;
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/* Write the new settings. */
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, RegVal);
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}
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/******************************************************************************/
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/**
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* This function checks if the reciever's internal registers indicate that link
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@ -800,6 +800,8 @@ u32 XDp_TxIsConnected(XDp *InstancePtr);
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void XDp_TxEnableMainLink(XDp *InstancePtr);
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void XDp_TxDisableMainLink(XDp *InstancePtr);
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void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset);
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void XDp_TxSetPhyPolarityAll(XDp *InstancePtr, u8 Polarity);
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void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity);
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u32 XDp_RxCheckLinkStatus(XDp *InstancePtr);
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void XDp_RxDtgEn(XDp *InstancePtr);
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void XDp_RxDtgDis(XDp *InstancePtr);
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@ -629,11 +629,28 @@
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#define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \
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0x0000200 /**< Hold TX_PHY_PCS reset. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK \
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0x0000400 /**< Set TX_PHY_POLARITY. */
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0x0000800 /**< Set TX_PHY_POLARITY. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \
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0x0001000 /**< Set TX_PHY_PRBSFORCEERR. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \
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0x000E000 /**< Set TX_PHY_LOOPBACK. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 /**< Shift bits for
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TX_PHY_LOOPBACK. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK \
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0x0010000 /**< Set to enable individual
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lane polarity. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK \
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0x0020000 /**< Set TX_PHY_POLARITY for
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lane 0. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK \
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0x0040000 /**< Set TX_PHY_POLARITY for
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lane 1. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK \
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0x0080000 /**< Set TX_PHY_POLARITY for
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lane 2. */
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#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK \
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0x0100000 /**< Set TX_PHY_POLARITY for
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lane 3. */
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#define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK \
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0x0000003 /**< Rest GT and PHY. */
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/* 0x234: PHY_CLOCK_SELECT */
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