dp: tx: Added PHY polarity inversion option.

Both for all lanes and for individual lane PHY polarity setting.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>

XilinxProcessorIPLib/drivers/dp/src/xdp.c

@@ -1282,6 +1282,106 @@ void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset)
 	XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1);
 }
 
+/******************************************************************************/
+/**
+ * This function sets the PHY polarity on all lanes.
+ *
+ * @param	InstancePtr is a pointer to the XDp instance.
+ * @param	Polarity is the value to set for the polarity (0 or 1).
+ *
+ * @return	None.
+ *
+ * @note	The individual PHY polarity option will be disabled if set.
+ *
+*******************************************************************************/
+void XDp_TxSetPhyPolarityAll(XDp *InstancePtr, u8 Polarity)
+{
+	u32 RegVal;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Polarity == 0) || (Polarity == 1));
+
+	/* Preserve current settings. */
+	RegVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG);
+
+	/* Set the polarity. */
+	if (Polarity) {
+		RegVal |= XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK;
+	}
+	else {
+		RegVal &= ~XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK;
+	}
+
+	/* Disable individual polarity setting. */
+	RegVal &= ~XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK;
+
+	/* Write the new settings. */
+	XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, RegVal);
+}
+
+/******************************************************************************/
+/**
+ * This function sets the PHY polarity on a specified lane.
+ *
+ * @param	InstancePtr is a pointer to the XDp instance.
+ * @param	Lane is the lane number (0-3) to set the polarity for.
+ * @param	Polarity is the value to set for the polarity (0 or 1).
+ *
+ * @return	None.
+ *
+ * @note	If individual lane polarity is used, it is recommended that this
+ *		function is called for every lane in use.
+ *
+*******************************************************************************/
+void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity)
+{
+	u32 RegVal;
+	u32 MaskVal;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Lane >= 0) && (Lane <= 3));
+	Xil_AssertVoid((Polarity == 0) || (Polarity == 1));
+
+	/* Preserve current settings. */
+	RegVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG);
+
+	/* Determine bit mask to use. */
+	switch (Lane) {
+	case 0:
+		MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK;
+		break;
+	case 1:
+		MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK;
+		break;
+	case 2:
+		MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK;
+		break;
+	case 3:
+		MaskVal = XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK;
+		break;
+	default:
+		break;
+	}
+
+	/* Set the polarity. */
+	if (Polarity) {
+		RegVal |= MaskVal;
+	}
+	else {
+		RegVal &= ~MaskVal;
+	}
+
+	/* Enable individual polarity setting. */
+	RegVal |= XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK;
+
+	/* Write the new settings. */
+	XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, RegVal);
+}
+
 /******************************************************************************/
 /**
  * This function checks if the reciever's internal registers indicate that link

XilinxProcessorIPLib/drivers/dp/src/xdp.h

@@ -800,6 +800,8 @@ u32 XDp_TxIsConnected(XDp *InstancePtr);
 void XDp_TxEnableMainLink(XDp *InstancePtr);
 void XDp_TxDisableMainLink(XDp *InstancePtr);
 void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset);
+void XDp_TxSetPhyPolarityAll(XDp *InstancePtr, u8 Polarity);
+void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity);
 u32 XDp_RxCheckLinkStatus(XDp *InstancePtr);
 void XDp_RxDtgEn(XDp *InstancePtr);
 void XDp_RxDtgDis(XDp *InstancePtr);

XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h

@@ -629,11 +629,28 @@
 #define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \
 				0x0000200	/**< Hold TX_PHY_PCS reset. */
 #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK \
-				0x0000400	/**< Set TX_PHY_POLARITY. */
+				0x0000800	/**< Set TX_PHY_POLARITY. */
 #define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \
 				0x0001000	/**< Set TX_PHY_PRBSFORCEERR. */
 #define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \
 				0x000E000	/**< Set TX_PHY_LOOPBACK. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 /**< Shift bits for
+							TX_PHY_LOOPBACK. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK \
+				0x0010000	/**< Set to enable individual
+							lane polarity. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK \
+				0x0020000	/**< Set TX_PHY_POLARITY for
+							lane 0. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK \
+				0x0040000	/**< Set TX_PHY_POLARITY for
+							lane 1. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK \
+				0x0080000	/**< Set TX_PHY_POLARITY for
+							lane 2. */
+#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK \
+				0x0100000	/**< Set TX_PHY_POLARITY for
+							lane 3. */
 #define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK \
 				0x0000003	/**< Rest GT and PHY. */
 /* 0x234: PHY_CLOCK_SELECT */