sw_apps: openamp_matrix_multiply: modified the code and license information

This patch modifies the code as per the opensource git changes and
updates the license information

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-03-25 15:01:46 +05:30 committed by Nava kishore Manne
parent 0a34042255
commit 2eff0eedbb
6 changed files with 20 additions and 24 deletions

View file

@ -31,13 +31,11 @@
#include <stdio.h>
#include <string.h>
#include "xparameters.h"
#include "baremetal.h"
#include "xil_exception.h"
#include "xscugic.h"
#include "xil_cache.h"
#include "xil_mmu.h"
#include "baremetal.h"
#include "platform.h"
XScuGic InterruptController;
@ -198,12 +196,12 @@ void ipi_isr(int vect_id, void *data) {
unsigned int ipi_intr_status = (unsigned int)Xil_In32(ipi_base_addr + IPI_ISR_OFFSET);
int i = 0;
do {
Xil_Out32((ipi_base_addr + IPI_ISR_OFFSET), ipi_intr_status);
for (i = 0; i < IPI_TOTAL; i++) {
if (ipi_base_addr != ipi_handler_table[i].ipi_base_addr)
continue;
if (!(ipi_intr_status && (ipi_handler_table[i].intr_mask)))
continue;
Xil_Out32((ipi_base_addr + IPI_ISR_OFFSET), ipi_handler_table[i].intr_mask);
ipi_handler_table[i].ipi_handler(ipi_base_addr, ipi_handler_table[i].intr_mask, ipi_handler_table[i].data);
}
ipi_intr_status = (unsigned int)Xil_In32(ipi_base_addr + IPI_ISR_OFFSET);

View file

@ -39,6 +39,16 @@
#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
#define VRING1_IPI_INTR_VECT 65
/* IPI REGs OFFSET */
#define IPI_TRIG_OFFSET 0x00000000 /* IPI trigger register offset */
#define IPI_OBS_OFFSET 0x00000004 /* IPI observation register offset */
#define IPI_ISR_OFFSET 0x00000010 /* IPI interrupt status register offset */
#define IPI_IMR_OFFSET 0x00000014 /* IPI interrupt mask register offset */
#define IPI_IER_OFFSET 0x00000018 /* IPI interrupt enable register offset */
#define IPI_IDR_OFFSET 0x0000001C /* IPI interrupt disable register offset */
#define platform_dcache_all_flush() { Xil_DCacheFlush(); }
#define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); }

View file

@ -122,6 +122,8 @@ extern const struct remote_resource_table resources;
/* Application entry point */
int main() {
int status = 0;
/* Initialize HW system components */
init_system();
@ -129,8 +131,11 @@ int main() {
rsc_info.size = sizeof(resources);
/* Initialize RPMSG framework */
remoteproc_resource_init(&rsc_info, rpmsg_channel_created, rpmsg_channel_deleted,
status = remoteproc_resource_init(&rsc_info, rpmsg_channel_created, rpmsg_channel_deleted,
rpmsg_read_cb ,&proc);
if (status < 0) {
return -1;
}
while (1) {
__asm__ ( "wfi\n\t" );

View file

@ -1,8 +1,5 @@
/*
* Copyright (c) 2014, Mentor Graphics Corporation
* All rights reserved.
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
* Copyright (c) 2015 Xilinx, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:

View file

@ -1,8 +1,5 @@
/*
* Copyright (c) 2014, Mentor Graphics Corporation
* All rights reserved.
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
* Copyright (c) 2015 Xilinx, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -47,14 +44,6 @@ struct ipi_info {
uint32_t ipi_chn_mask;
};
/* IPI REGs OFFSET */
#define IPI_TRIG_OFFSET 0x00000000 /* IPI trigger register offset */
#define IPI_OBS_OFFSET 0x00000004 /* IPI observation register offset */
#define IPI_ISR_OFFSET 0x00000010 /* IPI interrupt status register offset */
#define IPI_IMR_OFFSET 0x00000014 /* IPI interrupt mask register offset */
#define IPI_IER_OFFSET 0x00000018 /* IPI interrupt enable register offset */
#define IPI_IDR_OFFSET 0x0000001C /* IPI interrupt disable register offset */
/* IPC Device parameters */
#define SHM_ADDR (void *)0x3ED08000
#define SHM_SIZE 0x00200000

View file

@ -1,8 +1,5 @@
/*
* Copyright (c) 2014, Mentor Graphics Corporation
* All rights reserved.
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
* Copyright (c) 2015 Xilinx, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: