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sw_apps:zynqmp_fsbl: Load address configuration in DDR for PL

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Changed the location of temporary ddr address definition.
This address is for storing PL bitstream temporarily.
User can change this address till support is provided in bootgen
(for load address configuration for PL).

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This commit is contained in:
Sarat Chand Savitala 2015-07-13 19:52:07 +05:30 • committed by Nava kishore Manne
parent 487abcb1b4
commit 2f7303ed76
2 changed files with 2 additions and 1 deletions
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2
lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h
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@ -60,6 +60,8 @@ extern "C" {
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/* This is the address in DDR where bitstream will be copied temporarily */
#define XFSBL_DDR_TEMP_ADDRESS (0x100000U)
/**************************** Type Definitions *******************************/

1
lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
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@ -480,7 +480,6 @@ extern "C" {
* Other FSBL defines
* this can defined in xfsbl_main.h
*/
#define XFSBL_DDR_TEMP_ADDRESS (0x100000U)
#define XFSBL_R5_0 (0x1U)
#define XFSBL_R5_L (0x2U)