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video_common: XVid->XVidC and adherence to Xilinx coding guidelines.

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Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Shadul Shaikh 2015-01-14 21:25:03 +05:30 • committed by Nava kishore Manne
parent 9c570b85fa
commit 325b946207
8 changed files with 1451 additions and 1316 deletions
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432
XilinxProcessorIPLib/drivers/video_common/src/xedid.c
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@ -1,432 +0,0 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xedid.c
*
* Contains function definitions related to the Extended Display Identification
* Data (EDID) structure which is present in all monitors. All content in this
* file is agnostic of communication interface protocol.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 als 11/09/14 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xedid.h"
/**************************** Function Prototypes *****************************/
static u32 XEdid_IsVideoTimingSupportedPreferredTiming(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode);
static u32 XEdid_IsVideoTimingSupportedEstablishedTimings(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode);
static u32 XEdid_IsVideoTimingSupportedStandardTimings(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode);
static float XVid_CalculatePower(float Base, u8 Power);
static float XVid_CalculateBinaryFraction(u16 Val, u8 DecPtIndex);
/**************************** Function Definitions ****************************/
void XEDID_GET_VPI_ID_MAN_NAME(u8 *EdidRaw, char ManName[4])
{
ManName[0] = 0x40 + ((EdidRaw[XEDID_VPI_ID_MAN_NAME0] &
XEDID_VPI_ID_MAN_NAME0_CHAR0_MASK) >>
XEDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT);
ManName[1] = 0x40 + (((EdidRaw[XEDID_VPI_ID_MAN_NAME0] &
XEDID_VPI_ID_MAN_NAME0_CHAR1_MASK) <<
XEDID_VPI_ID_MAN_NAME0_CHAR1_POS) |
(EdidRaw[XEDID_VPI_ID_MAN_NAME1] >>
XEDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT));
ManName[2] = 0x40 + (EdidRaw[XEDID_VPI_ID_MAN_NAME1] &
XEDID_VPI_ID_MAN_NAME1_CHAR2_MASK);
ManName[3] = '\0';
}
u8 XEDID_GET_BDISP_VID_DIG_BPC(u8 *EdidRaw)
{
u8 Bpc;
switch (((EdidRaw[XEDID_BDISP_VID] & XEDID_BDISP_VID_DIG_BPC_MASK) >>
XEDID_BDISP_VID_DIG_BPC_SHIFT)) {
case XEDID_BDISP_VID_DIG_BPC_6:
Bpc = 6;
break;
case XEDID_BDISP_VID_DIG_BPC_8:
Bpc = 8;
break;
case XEDID_BDISP_VID_DIG_BPC_10:
Bpc = 10;
break;
case XEDID_BDISP_VID_DIG_BPC_12:
Bpc = 12;
break;
case XEDID_BDISP_VID_DIG_BPC_14:
Bpc = 14;
break;
case XEDID_BDISP_VID_DIG_BPC_16:
Bpc = 16;
break;
default:
Bpc = XEDID_BDISP_VID_DIG_BPC_UNDEF;
break;
}
return Bpc;
}
float XEDID_GET_CC_REDX(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_REDX_HIGH] <<
XEDID_CC_HIGH_SHIFT) | (EdidRaw[XEDID_CC_RG_LOW] >>
XEDID_CC_RBX_LOW_SHIFT), 9);
}
float XEDID_GET_CC_REDY(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_REDY_HIGH] <<
XEDID_CC_HIGH_SHIFT) | ((EdidRaw[XEDID_CC_RG_LOW] &
XEDID_CC_RBY_LOW_MASK) >> XEDID_CC_RBY_LOW_SHIFT), 9);
}
float XEDID_GET_CC_GREENX(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_GREENX_HIGH] <<
XEDID_CC_HIGH_SHIFT) | ((EdidRaw[XEDID_CC_RG_LOW] &
XEDID_CC_GWX_LOW_MASK) >> XEDID_CC_GWX_LOW_SHIFT), 9);
}
float XEDID_GET_CC_GREENY(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_GREENY_HIGH] <<
XEDID_CC_HIGH_SHIFT) | (EdidRaw[XEDID_CC_RG_LOW] &
XEDID_CC_GWY_LOW_MASK), 9);
}
float XEDID_GET_CC_BLUEX(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_BLUEX_HIGH] <<
XEDID_CC_HIGH_SHIFT) | (EdidRaw[XEDID_CC_BW_LOW] >>
XEDID_CC_RBX_LOW_SHIFT), 9);
}
float XEDID_GET_CC_BLUEY(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_BLUEY_HIGH] <<
XEDID_CC_HIGH_SHIFT) | ((EdidRaw[XEDID_CC_BW_LOW] &
XEDID_CC_RBY_LOW_MASK) >> XEDID_CC_RBY_LOW_SHIFT), 9);
}
float XEDID_GET_CC_WHITEX(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_WHITEX_HIGH] <<
XEDID_CC_HIGH_SHIFT) | ((EdidRaw[XEDID_CC_BW_LOW] &
XEDID_CC_GWX_LOW_MASK) >> XEDID_CC_GWX_LOW_SHIFT), 9);
}
float XEDID_GET_CC_WHITEY(u8 *EdidRaw)
{
return XVid_CalculateBinaryFraction((EdidRaw[XEDID_CC_WHITEY_HIGH] <<
XEDID_CC_HIGH_SHIFT) | (EdidRaw[XEDID_CC_BW_LOW] &
XEDID_CC_GWY_LOW_MASK), 9);
}
u16 XEDID_GET_STD_TIMINGS_V(u8 *EdidRaw, u8 StdTimingsNum)
{
u16 V;
switch (XEDID_GET_STD_TIMINGS_AR(EdidRaw, StdTimingsNum)) {
case XEDID_STD_TIMINGS_AR_16_10:
V = (10 * XEDID_GET_STD_TIMINGS_H(EdidRaw, StdTimingsNum)) / 16;
break;
case XEDID_STD_TIMINGS_AR_4_3:
V = (3 * XEDID_GET_STD_TIMINGS_H(EdidRaw, StdTimingsNum)) / 4;
break;
case XEDID_STD_TIMINGS_AR_5_4:
V = (4 * XEDID_GET_STD_TIMINGS_H(EdidRaw, StdTimingsNum)) / 5;
break;
default:
V = (9 * XEDID_GET_STD_TIMINGS_H(EdidRaw, StdTimingsNum)) / 16;
break;
}
return V;
}
u32 XEdid_IsVideoTimingSupported(u8 *EdidRaw, XVid_VideoTimingMode *VtMode)
{
u32 Status;
/* Check if the video mode is the preferred timing. */
Status = XEdid_IsVideoTimingSupportedPreferredTiming(EdidRaw, VtMode);
if (Status == XST_SUCCESS) {
return Status;
}
/* Check established timings I, II, and III. */
Status = XEdid_IsVideoTimingSupportedEstablishedTimings(EdidRaw, VtMode);
if (Status == XST_SUCCESS) {
return Status;
}
/* Check in standard timings support. */
Status = XEdid_IsVideoTimingSupportedStandardTimings(EdidRaw, VtMode);
return Status;
}
static u32 XEdid_IsVideoTimingSupportedPreferredTiming(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode)
{
u8 *Ptm;
Ptm = &EdidRaw[XEDID_PTM];
u32 HActive =
(((Ptm[XEDID_DTD_PTM_HRES_HBLANK_U4] &
XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >>
XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XEDID_DTD_PTM_HRES_LSB];
u32 VActive =
(((Ptm[XEDID_DTD_PTM_VRES_VBLANK_U4] &
XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >>
XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XEDID_DTD_PTM_VRES_LSB];
if (VtMode->Timing.F1VTotal != XEDID_IS_DTD_PTM_INTERLACED(EdidRaw)) {
return XST_FAILURE;
}
else if ((VtMode->Timing.HActive == HActive) &&
(VtMode->Timing.VActive == VActive)) {
return XST_SUCCESS;
}
return XST_FAILURE;
}
static u32 XEdid_IsVideoTimingSupportedEstablishedTimings(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode)
{
u32 Status = XST_FAILURE;
/* First, check established timings I, II, and III. */
if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 640) &&
(VtMode->FrameRate == XVID_FR_56HZ) &&
XEDID_SUPP_EST_TIMINGS_800x600_56(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVID_FR_60HZ) &&
XEDID_SUPP_EST_TIMINGS_640x480_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVID_FR_60HZ) &&
XEDID_SUPP_EST_TIMINGS_800x600_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVID_FR_60HZ) &&
XEDID_SUPP_EST_TIMINGS_1024x768_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVID_FR_67HZ) &&
XEDID_SUPP_EST_TIMINGS_640x480_67(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 720) &&
(VtMode->Timing.VActive == 400) &&
(VtMode->FrameRate == XVID_FR_70HZ) &&
XEDID_SUPP_EST_TIMINGS_720x400_70(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVID_FR_70HZ) &&
XEDID_SUPP_EST_TIMINGS_1024x768_70(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVID_FR_72HZ) &&
XEDID_SUPP_EST_TIMINGS_640x480_72(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVID_FR_72HZ) &&
XEDID_SUPP_EST_TIMINGS_800x600_72(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_640x480_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_800x600_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 832) &&
(VtMode->Timing.VActive == 624) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_832x624_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_1024x768_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1152) &&
(VtMode->Timing.VActive == 870) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_1152x870_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1280) &&
(VtMode->Timing.VActive == 1024) &&
(VtMode->FrameRate == XVID_FR_75HZ) &&
XEDID_SUPP_EST_TIMINGS_1280x1024_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVID_FR_87HZ) &&
XEDID_SUPP_EST_TIMINGS_1024x768_87(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 720) &&
(VtMode->Timing.VActive == 400) &&
(VtMode->FrameRate == XVID_FR_88HZ) &&
XEDID_SUPP_EST_TIMINGS_720x400_88(EdidRaw)) {
Status = XST_SUCCESS;
}
return Status;
}
static u32 XEdid_IsVideoTimingSupportedStandardTimings(u8 *EdidRaw,
XVid_VideoTimingMode *VtMode)
{
u8 Index;
for (Index = 0; Index < 8; Index++) {
if ((VtMode->Timing.HActive == XEDID_GET_STD_TIMINGS_H(EdidRaw,
Index + 1)) &&
(VtMode->Timing.VActive == XEDID_GET_STD_TIMINGS_V(EdidRaw,
Index + 1)) &&
(VtMode->FrameRate == XEDID_GET_STD_TIMINGS_FRR(EdidRaw,
Index + 1))) {
return XST_SUCCESS;
}
}
return XST_FAILURE;
}
/******************************************************************************/
/**
* Perform a power operation.
*
* @param Base is b in the power operation, b^n.
* @param Power is n in the power operation, b^n.
*
* @return Base^Power (Base to the power of Power).
*
* @note None.
*
*******************************************************************************/
static float XVid_CalculatePower(float Base, u8 Power)
{
u8 Index;
float Res = 1.0;
for (Index = 0; Index < Power; Index++) {
Res *= Base;
}
return Res;
}
/******************************************************************************/
/**
* Convert a fractional binary number into a decimal number. Binary digits to
* the right of the decimal point represent 2^-1 to 2^-(DecPtIndex+1). Binary
* digits to the left of the decimal point represent 2^0, 2^1, etc.
*
* @param Val is the binary representation of the fraction.
* @param DecPtIndex is the index of the decimal point in the binary
* number. The decimal point is between the binary digits at Val's
* indices (DecPtIndex) and (DecPtIndex + 1).
*
* @return Base^Power (Base to the power of Power).
*
* @note None.
*
*******************************************************************************/
static float XVid_CalculateBinaryFraction(u16 Val, u8 DecPtIndex)
{
int Index;
float Res;
for (Index = DecPtIndex, Res = 0; Index >= 0; Index--) {
if (((Val >> Index) & 0x1) == 1) {
Res += XVid_CalculatePower(0.5, DecPtIndex - Index + 1);
}
}
return (Val >> (DecPtIndex + 1)) + Res;
}

427
XilinxProcessorIPLib/drivers/video_common/src/xedid.h
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@ -1,427 +0,0 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xedid.h
*
* Contains macros, definitions, and function declarations related to the
* Extended Display Identification Data (EDID) structure which is present in all
* monitors. All content in this file is agnostic of communication interface
* protocol.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 als 11/09/14 Initial release.
* </pre>
*
*******************************************************************************/
#ifndef XEDID_H_
/* Prevent circular inclusions by using protection macros. */
#define XEDID_H_
/******************************* Include Files ********************************/
#include "xstatus.h"
#include "xvid.h"
/************************** Constant Definitions ******************************/
/** @name Address mapping for the base EDID block.
* @{
*/
#define XEDID_HEADER 0x00
/* Vendor and product identification. */
#define XEDID_VPI_ID_MAN_NAME0 0x08
#define XEDID_VPI_ID_MAN_NAME1 0x09
#define XEDID_VPI_ID_PROD_CODE_LSB 0x0A
#define XEDID_VPI_ID_PROD_CODE_MSB 0x0B
#define XEDID_VPI_ID_SN0 0x0C
#define XEDID_VPI_ID_SN1 0x0D
#define XEDID_VPI_ID_SN2 0x0E
#define XEDID_VPI_ID_SN3 0x0F
#define XEDID_VPI_WEEK_MAN 0x10
#define XEDID_VPI_YEAR 0x11
/* EDID structure version and revision. */
#define XEDID_STRUCT_VER 0x12
#define XEDID_STRUCT_REV 0x13
/* Basic display parameters and features. */
#define XEDID_BDISP_VID 0x14
#define XEDID_BDISP_H_SSAR 0x15
#define XEDID_BDISP_V_SSAR 0x16
#define XEDID_BDISP_GAMMA 0x17
#define XEDID_BDISP_FEATURE 0x18
/* Color characterisitics (display x,y chromaticity coordinates). */
#define XEDID_CC_RG_LOW 0x19
#define XEDID_CC_BW_LOW 0x1A
#define XEDID_CC_REDX_HIGH 0x1B
#define XEDID_CC_REDY_HIGH 0x1C
#define XEDID_CC_GREENX_HIGH 0x1D
#define XEDID_CC_GREENY_HIGH 0x1E
#define XEDID_CC_BLUEX_HIGH 0x1F
#define XEDID_CC_BLUEY_HIGH 0x20
#define XEDID_CC_WHITEX_HIGH 0x21
#define XEDID_CC_WHITEY_HIGH 0x22
/* Established timings. */
#define XEDID_EST_TIMINGS_I 0x23
#define XEDID_EST_TIMINGS_II 0x24
#define XEDID_EST_TIMINGS_MAN 0x25
/* Standard timings. */
#define XEDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1))
#define XEDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1))
/* 18 byte descriptors. */
#define XEDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1))
#define XEDID_PTM (XEDID_18BYTE_DESCRIPTOR(1))
/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XEDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00
#define XEDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01
#define XEDID_DTD_PTM_HRES_LSB 0x02
#define XEDID_DTD_PTM_HBLANK_LSB 0x03
#define XEDID_DTD_PTM_HRES_HBLANK_U4 0x04
#define XEDID_DTD_PTM_VRES_LSB 0x05
#define XEDID_DTD_PTM_VBLANK_LSB 0x06
#define XEDID_DTD_PTM_VRES_VBLANK_U4 0x07
#define XEDID_DTD_PTM_HFPORCH_LSB 0x08
#define XEDID_DTD_PTM_HSPW_LSB 0x09
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B
#define XEDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C
#define XEDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E
#define XEDID_DTD_PTM_HBORDER 0x0F
#define XEDID_DTD_PTM_VBORDER 0x10
#define XEDID_DTD_PTM_SIGNAL 0x11
/* Extension block count. */
#define XEDID_EXT_BLK_COUNT 0x7E
/* Checksum. */
#define XEDID_CHECKSUM 0x7F
/* @} */
/******************************************************************************/
/** @name Extended Display Identification Data: Masks, shifts, and values.
* @{
*/
#define XEDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2
#define XEDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2)
#define XEDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03
#define XEDID_VPI_ID_MAN_NAME0_CHAR1_POS 3
#define XEDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5
#define XEDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F
/* Basic display parameters and features: Video input definition. */
#define XEDID_BDISP_VID_VSI_SHIFT 7
#define XEDID_BDISP_VID_VSI_MASK (0x01 << 7)
#define XEDID_BDISP_VID_ANA_SLS_SHIFT 5
#define XEDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5)
#define XEDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0
#define XEDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1
#define XEDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2
#define XEDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3
#define XEDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4)
#define XEDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3)
#define XEDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2)
#define XEDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1)
#define XEDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01)
#define XEDID_BDISP_VID_DIG_BPC_SHIFT 4
#define XEDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4)
#define XEDID_BDISP_VID_DIG_BPC_UNDEF 0x0
#define XEDID_BDISP_VID_DIG_BPC_6 0x1
#define XEDID_BDISP_VID_DIG_BPC_8 0x2
#define XEDID_BDISP_VID_DIG_BPC_10 0x3
#define XEDID_BDISP_VID_DIG_BPC_12 0x4
#define XEDID_BDISP_VID_DIG_BPC_14 0x5
#define XEDID_BDISP_VID_DIG_BPC_16 0x6
#define XEDID_BDISP_VID_DIG_VIS_MASK 0xF
#define XEDID_BDISP_VID_DIG_VIS_UNDEF 0x0
#define XEDID_BDISP_VID_DIG_VIS_DVI 0x1
#define XEDID_BDISP_VID_DIG_VIS_HDMIA 0x2
#define XEDID_BDISP_VID_DIG_VIS_HDMIB 0x3
#define XEDID_BDISP_VID_DIG_VIS_MDDI 0x4
#define XEDID_BDISP_VID_DIG_VIS_DP 0x5
/* Basic display parameters and features: Feature support. */
#define XEDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7)
#define XEDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6)
#define XEDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5)
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3)
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2
#define XEDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3
#define XEDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3)
#define XEDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4)
#define XEDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2)
#define XEDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1)
#define XEDID_BDISP_FEATURE_CONTFREQ_MASK (0x1)
/* Color characterisitics (display x,y chromaticity coordinates). */
#define XEDID_CC_HIGH_SHIFT 2
#define XEDID_CC_RBX_LOW_SHIFT 6
#define XEDID_CC_RBY_LOW_SHIFT 4
#define XEDID_CC_RBY_LOW_MASK (0x3 << 4)
#define XEDID_CC_GWX_LOW_SHIFT 2
#define XEDID_CC_GWX_LOW_MASK (0x3 << 2)
#define XEDID_CC_GWY_LOW_MASK (0x3)
#define XEDID_CC_GREENY_HIGH 0x1E
#define XEDID_CC_BLUEX_HIGH 0x1F
#define XEDID_CC_BLUEY_HIGH 0x20
#define XEDID_CC_WHITEX_HIGH 0x21
#define XEDID_CC_WHITEY_HIGH 0x22
/* Established timings. */
#define XEDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7)
#define XEDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6)
#define XEDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5)
#define XEDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4)
#define XEDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3)
#define XEDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2)
#define XEDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1)
#define XEDID_EST_TIMINGS_I_800x600_60_MASK (0x1)
#define XEDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7)
#define XEDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6)
#define XEDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5)
#define XEDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4)
#define XEDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3)
#define XEDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2)
#define XEDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1)
#define XEDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1)
#define XEDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7)
#define XEDID_EST_TIMINGS_MAN_MASK (0x7F)
/* Standard timings. */
#define XEDID_STD_TIMINGS_AR_SHIFT 6
#define XEDID_STD_TIMINGS_AR_16_10 0x0
#define XEDID_STD_TIMINGS_AR_4_3 0x1
#define XEDID_STD_TIMINGS_AR_5_4 0x2
#define XEDID_STD_TIMINGS_AR_16_9 0x3
#define XEDID_STD_TIMINGS_FRR_MASK (0x3F)
/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4
#define XEDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80
#define XEDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7
#define XEDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02
#define XEDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04
#define XEDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1
#define XEDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2
/* @} */
/******************* Macros (Inline Functions) Definitions ********************/
#define XEDID_IS_HEADER_VALID(E) \
!memcmp(E, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)
/* Vendor and product identification: ID manufacturer name. */
void XEDID_GET_VPI_ID_MAN_NAME(u8 *EdidRaw, char ManName[4]);
/* Vendor and product identification: ID product code. */
#define XEDID_GET_VPI_ID_PROD_CODE(E) \
((u16)((E[XEDID_VPI_ID_PROD_CODE_MSB] << 8) | \
E[XEDID_VPI_ID_PROD_CODE_LSB]))
/* Vendor and product identification: ID serial number. */
#define XEDID_GET_VPI_SN(E) \
((u32)((E[XEDID_VPI_ID_SN3] << 24) | (E[XEDID_VPI_ID_SN2] << 16) | \
(E[XEDID_VPI_ID_SN1] << 8) | E[XEDID_VPI_ID_SN0]))
/* Vendor and product identification: Week and year of manufacture or model
* year. */
#define XEDID_GET_VPI_WEEK_MAN(E) (E[XEDID_VPI_WEEK_MAN])
#define XEDID_GET_VPI_YEAR(E) (E[XEDID_VPI_YEAR] + 1990)
#define XEDID_IS_VPI_YEAR_MODEL(E) (XEDID_GET_VPI_WEEK_MAN(E) == 0xFF)
#define XEDID_IS_VPI_YEAR_MAN(E) (XEDID_GET_VPI_WEEK_MAN(E) != 0xFF)
/* EDID structure version and revision. */
#define XEDID_GET_STRUCT_VER(E) (E[XEDID_STRUCT_VER])
#define XEDID_GET_STRUCT_REV(E) (E[XEDID_STRUCT_REV])
/* Basic display parameters and features: Video input definition. */
#define XEDID_IS_BDISP_VID_VSI_DIGITAL(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_VSI_MASK) != 0)
#define XEDID_IS_BDISP_VID_VSI_ANALOG(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_VSI_MASK) == 0)
#define XEDID_GET_BDISP_VID_ANA_SLS(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_SLS_MASK) >> \
XEDID_BDISP_VID_ANA_SLS_SHIFT)
#define XEDID_SUPP_BDISP_VID_ANA_VID_SETUP(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_VID_SETUP_MASK) != 0)
#define XEDID_SUPP_BDISP_VID_ANA_SEP_SYNC_HV(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK) != 0)
#define XEDID_SUPP_BDISP_VID_ANA_COMP_SYNC_H(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_COMP_SYNC_H_MASK) != 0)
#define XEDID_SUPP_BDISP_VID_ANA_COMP_SYNC_G(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_COMP_SYNC_G_MASK) != 0)
#define XEDID_SUPP_BDISP_VID_ANA_SERR_V_SYNC(E) \
((E[XEDID_BDISP_VID] & XEDID_BDISP_VID_ANA_SERR_V_SYNC_MASK) != 0)
u8 XEDID_GET_BDISP_VID_DIG_BPC(u8 *EdidRaw);
#define XEDID_GET_BDISP_VID_DIG_VIS(E) \
(E[XEDID_BDISP_VID] & XEDID_BDISP_VID_DIG_VIS_MASK)
/* Basic display parameters and features: Horizontal and vertical screen size or
* aspect ratio. */
#define XEDID_IS_BDISP_SSAR_DEFINED(E) \
((E[XEDID_BDISP_H_SSAR] | E[XEDID_BDISP_V_SSAR]) != 0)
#define XEDID_GET_BDISP_SSAR_H(E) E[XEDID_BDISP_H_SSAR]
#define XEDID_GET_BDISP_SSAR_V(E) E[XEDID_BDISP_V_SSAR]
#define XEDID_IS_BDISP_SSAR_SS(E) \
((XEDID_GET_BDISP_SSAR_H(E) != 0) && (XEDID_GET_BDISP_SSAR_V(E) != 0))
#define XEDID_IS_BDISP_SSAR_AR_L(E) \
((XEDID_GET_BDISP_SSAR_H(E) != 0) && (XEDID_GET_BDISP_SSAR_V(E) == 0))
#define XEDID_IS_BDISP_SSAR_AR_P(E) \
((XEDID_GET_BDISP_SSAR_H(E) == 0) && (XEDID_GET_BDISP_SSAR_V(E) != 0))
#define XEDID_GET_BDISP_SSAR_AR_L(E) \
((float)((XEDID_GET_BDISP_SSAR_H(E) + 99.0) / 100.0))
#define XEDID_GET_BDISP_SSAR_AR_P(E) \
((float)(100.0 / (XEDID_GET_BDISP_SSAR_V(E) + 99.0)))
/* Basic display parameters and features: Gamma. */
#define XEDID_IS_BDISP_GAMMA_IN_EXT(E) (E[XEDID_BDISP_GAMMA] == 0xFF)
#define XEDID_GET_BDISP_GAMMA(E) \
((float)((E[XEDID_BDISP_GAMMA] + 100.0) / 100.0))
/* Basic display parameters and features: Feature support. */
#define XEDID_SUPP_BDISP_FEATURE_PM_STANDBY(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_PM_STANDBY_MASK) != 0)
#define XEDID_SUPP_BDISP_FEATURE_PM_SUSPEND(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_PM_SUSPEND_MASK) != 0)
#define XEDID_SUPP_BDISP_FEATURE_PM_OFF_VLP(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_PM_OFF_VLP_MASK) != 0)
#define XEDID_GET_BDISP_FEATURE_ANA_COLORTYPE(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_ANA_COLORTYPE_MASK) >> \
XEDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT)
#define XEDID_SUPP_BDISP_FEATURE_DIG_COLORENC_YCRCB444(E) \
((E[XEDID_BDISP_FEATURE] & \
XEDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK) != 0)
#define XEDID_SUPP_BDISP_FEATURE_DIG_COLORENC_YCRCB422(E) \
((E[XEDID_BDISP_FEATURE] & \
XEDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK) != 0)
#define XEDID_IS_BDISP_FEATURE_SRGB_DEF(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_SRGB_DEF_MASK) != 0)
#define XEDID_IS_BDISP_FEATURE_PTM_INC(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_PTM_INC_MASK) != 0)
#define XEDID_IS_BDISP_FEATURE_CONTFREQ(E) \
((E[XEDID_BDISP_FEATURE] & XEDID_BDISP_FEATURE_CONTFREQ_MASK) != 0)
/* Color characterisitics (display x,y chromaticity coordinates). */
float XEDID_GET_CC_REDX(u8 *EdidRaw);
float XEDID_GET_CC_REDY(u8 *EdidRaw);
float XEDID_GET_CC_GREENX(u8 *EdidRaw);
float XEDID_GET_CC_GREENY(u8 *EdidRaw);
float XEDID_GET_CC_BLUEX(u8 *EdidRaw);
float XEDID_GET_CC_BLUEY(u8 *EdidRaw);
float XEDID_GET_CC_WHITEX(u8 *EdidRaw);
float XEDID_GET_CC_WHITEY(u8 *EdidRaw);
/* Established timings. */
#define XEDID_SUPP_EST_TIMINGS_720x400_70(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_720x400_70_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_720x400_88(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_720x400_88_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_640x480_60(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_640x480_60_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_640x480_67(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_640x480_67_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_640x480_72(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_640x480_72_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_640x480_75(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_640x480_75_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_800x600_56(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_800x600_56_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_800x600_60(E) \
((E[XEDID_EST_TIMINGS_I] & XEDID_EST_TIMINGS_I_800x600_60_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_800x600_72(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_800x600_72_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_800x600_75(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_800x600_75_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_832x624_75(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_832x624_75_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1024x768_87(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_1024x768_87_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1024x768_60(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_1024x768_60_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1024x768_70(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_1024x768_70_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1024x768_75(E) \
((E[XEDID_EST_TIMINGS_II] & XEDID_EST_TIMINGS_II_1024x768_75_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1280x1024_75(E) \
((E[XEDID_EST_TIMINGS_II] & \
XEDID_EST_TIMINGS_II_1280x1024_75_MASK) != 0)
#define XEDID_SUPP_EST_TIMINGS_1152x870_75(E) \
((E[XEDID_EST_TIMINGS_MAN] & \
XEDID_EST_TIMINGS_MAN_1152x870_75_MASK) != 0)
#define XEDID_GET_TIMINGS_MAN(E) \
(E[XEDID_EST_TIMINGS_MAN] & XEDID_EST_TIMINGS_MAN_MASK)
/* Standard timings. */
#define XEDID_GET_STD_TIMINGS_H(E, N) ((E[XEDID_STD_TIMINGS_H(N)] + 31) * 8)
#define XEDID_GET_STD_TIMINGS_AR(E, N) \
(E[XEDID_STD_TIMINGS_AR_FRR(N)] >> XEDID_STD_TIMINGS_AR_SHIFT)
#define XEDID_GET_STD_TIMINGS_FRR(E, N) \
((E[XEDID_STD_TIMINGS_AR_FRR(N)] & XEDID_STD_TIMINGS_FRR_MASK) + 60)
u16 XEDID_GET_STD_TIMINGS_V(u8 *EdidRaw, u8 StdTimingsNum);
#define XEDID_IS_DTD_PTM_INTERLACED(E) \
((E[XEDID_PTM + XEDID_DTD_PTM_SIGNAL] & \
XEDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \
XEDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT)
/* Extension block count. */
#define XEDID_GET_EXT_BLK_COUNT(E) (E[XEDID_EXT_BLK_COUNT])
/* Checksum. */
#define XEDID_GET_CHECKSUM(E) (E[XEDID_CHECKSUM])
/* Utility functions. */
u32 XEdid_IsVideoTimingSupported(u8 *EdidRaw, XVid_VideoTimingMode *VtMode);
#endif /* XEDID_H_ */

345
XilinxProcessorIPLib/drivers/video_common/src/xvid.h
View file

@ -1,345 +0,0 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xvid.h
*
* Contains common structures, definitions, macros, and utility functions that
* are typically used by video-related drivers and applications.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 rc, 01/10/15 Initial release.
* als
* </pre>
*
*******************************************************************************/
#ifndef XVID_H_
/* Prevent circular inclusions by using protection macros. */
#define XVID_H_
/******************************* Include Files ********************************/
#include "xil_types.h"
/************************** Constant Definitions ******************************/
/**
* This typedef enumerates the list of available standard display monitor
* timings as specified in the xvid_timings_table.c file. The naming format is:
*
* XVID_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|I>(_RB)
*
* Where RB stands for reduced blanking.
*/
typedef enum {
/* Interlaced modes. */
XVID_VM_480_30_I = 0,
XVID_VM_576_25_I,
XVID_VM_1080_25_I,
XVID_VM_1080_30_I,
/* Progressive modes. */
XVID_VM_640x350_85_P,
XVID_VM_640x480_60_P,
XVID_VM_640x480_72_P,
XVID_VM_640x480_75_P,
XVID_VM_640x480_85_P,
XVID_VM_720x400_85_P,
XVID_VM_720x480_60_P,
XVID_VM_800x600_56_P,
XVID_VM_800x600_60_P,
XVID_VM_800x600_72_P,
XVID_VM_800x600_75_P,
XVID_VM_800x600_85_P,
XVID_VM_800x600_120_P_RB,
XVID_VM_848x480_60_P,
XVID_VM_1024x768_60_P,
XVID_VM_1024x768_70_P,
XVID_VM_1024x768_75_P,
XVID_VM_1024x768_85_P,
XVID_VM_1024x768_120_P_RB,
XVID_VM_1152x864_75_P,
XVID_VM_1280x720_50_P,
XVID_VM_1280x720_60_P,
XVID_VM_1280x768_60_P_RB,
XVID_VM_1280x768_60_P,
XVID_VM_1280x768_75_P,
XVID_VM_1280x768_85_P,
XVID_VM_1280x768_120_P_RB,
XVID_VM_1280x800_60_P_RB,
XVID_VM_1280x800_60_P,
XVID_VM_1280x800_75_P,
XVID_VM_1280x800_85_P,
XVID_VM_1280x800_120_P_RB,
XVID_VM_1280x960_60_P,
XVID_VM_1280x960_85_P,
XVID_VM_1280x960_120_P_RB,
XVID_VM_1280x1024_60_P,
XVID_VM_1280x1024_75_P,
XVID_VM_1280x1024_85_P,
XVID_VM_1280x1024_120_P_RB,
XVID_VM_1360x768_60_P,
XVID_VM_1360x768_120_P_RB,
XVID_VM_1366x768_60_P,
XVID_VM_1400x1050_60_P_RB,
XVID_VM_1400x1050_60_P,
XVID_VM_1400x1050_75_P,
XVID_VM_1400x1050_85_P,
XVID_VM_1400x1050_120_P_RB,
XVID_VM_1440x900_60_P_RB,
XVID_VM_1440x900_60_P,
XVID_VM_1440x900_75_P,
XVID_VM_1440x900_85_P,
XVID_VM_1440x900_120_P_RB,
XVID_VM_1600x1200_60_P,
XVID_VM_1600x1200_65_P,
XVID_VM_1600x1200_70_P,
XVID_VM_1600x1200_75_P,
XVID_VM_1600x1200_85_P,
XVID_VM_1600x1200_120_P_RB,
XVID_VM_1680x1050_60_P_RB,
XVID_VM_1680x1050_60_P,
XVID_VM_1680x1050_75_P,
XVID_VM_1680x1050_85_P,
XVID_VM_1680x1050_120_P_RB,
XVID_VM_1792x1344_60_P,
XVID_VM_1792x1344_75_P,
XVID_VM_1792x1344_120_P_RB,
XVID_VM_1856x1392_60_P,
XVID_VM_1856x1392_75_P,
XVID_VM_1856x1392_120_P_RB,
XVID_VM_1920x1080_24_P,
XVID_VM_1920x1080_25_P,
XVID_VM_1920x1080_30_P,
XVID_VM_1920x1080_50_P,
XVID_VM_1920x1080_60_P,
XVID_VM_1920x1200_60_P_RB,
XVID_VM_1920x1200_60_P,
XVID_VM_1920x1200_75_P,
XVID_VM_1920x1200_85_P,
XVID_VM_1920x1200_120_P_RB,
XVID_VM_1920x1440_60_P,
XVID_VM_1920x1440_75_P,
XVID_VM_1920x1440_120_P_RB,
XVID_VM_1920x2160_60_P,
XVID_VM_2560x1600_60_P_RB,
XVID_VM_2560x1600_60_P,
XVID_VM_2560x1600_75_P,
XVID_VM_2560x1600_85_P,
XVID_VM_2560x1600_120_P_RB,
XVID_VM_3840x2160_24_P,
XVID_VM_3840x2160_25_P,
XVID_VM_3840x2160_30_P,
XVID_VM_3840x2160_60_P,
XVID_VM_NUM_SUPPORTED,
XVID_VM_USE_EDID_PREFERRED,
XVID_VM_NO_INPUT,
XVID_VM_NOT_SUPPORTED,
/* Marks beginning/end of interlaced/progressive modes in the table. */
XVID_VM_INTL_START = XVID_VM_480_30_I,
XVID_VM_PROG_START = XVID_VM_640x350_85_P,
XVID_VM_INTL_END = (XVID_VM_PROG_START - 1),
XVID_VM_PROG_END = (XVID_VM_NUM_SUPPORTED - 1),
/* Common naming. */
XVID_VM_480_60_P = XVID_VM_720x480_60_P,
XVID_VM_720_50_P = XVID_VM_1280x720_50_P,
XVID_VM_720_60_P = XVID_VM_1280x720_60_P,
XVID_VM_WXGA_60_P = XVID_VM_1366x768_60_P,
XVID_VM_UXGA_60_P = XVID_VM_1600x1200_60_P,
XVID_VM_WSXGA_60_P = XVID_VM_1680x1050_60_P,
XVID_VM_1080_24_P = XVID_VM_1920x1080_24_P,
XVID_VM_1080_25_P = XVID_VM_1920x1080_25_P,
XVID_VM_1080_30_P = XVID_VM_1920x1080_30_P,
XVID_VM_1080_50_P = XVID_VM_1920x1080_50_P,
XVID_VM_1080_60_P = XVID_VM_1920x1080_60_P,
XVID_VM_WUXGA_60_P = XVID_VM_1920x1200_60_P,
XVID_VM_UHD2_60_P = XVID_VM_1920x2160_60_P,
XVID_VM_UHD_24_P = XVID_VM_3840x2160_24_P,
XVID_VM_UHD_25_P = XVID_VM_3840x2160_25_P,
XVID_VM_UHD_30_P = XVID_VM_3840x2160_30_P,
XVID_VM_UHD_60_P = XVID_VM_3840x2160_60_P
} XVid_VideoMode;
/* Progressive/interlaced video format. */
typedef enum {
XVID_VM_PROGRESSIVE = 0,
XVID_VM_INTERLACED
} XVid_VideoFormat;
/* Frame rate. */
typedef enum {
XVID_FR_24HZ = 24,
XVID_FR_25HZ = 25,
XVID_FR_30HZ = 30,
XVID_FR_50HZ = 50,
XVID_FR_56HZ = 56,
XVID_FR_60HZ = 60,
XVID_FR_65HZ = 65,
XVID_FR_67HZ = 67,
XVID_FR_70HZ = 70,
XVID_FR_72HZ = 72,
XVID_FR_75HZ = 75,
XVID_FR_85HZ = 85,
XVID_FR_87HZ = 87,
XVID_FR_88HZ = 88,
XVID_FR_100HZ = 100,
XVID_FR_120HZ = 120,
XVID_FR_NUM_SUPPORTED = 16,
XVID_FR_UNKNOWN
} XVid_FrameRate;
/* Color depth - bits per color component. */
typedef enum {
XVID_BPC_6 = 6,
XVID_BPC_8 = 8,
XVID_BPC_10 = 10,
XVID_BPC_12 = 12,
XVID_BPC_16 = 16,
XVID_BPC_NUM_SUPPORTED = 5,
XVID_BPC_UNKNOWN
} XVid_ColorDepth;
/* Pixels per clock. */
typedef enum {
XVID_PPC_1 = 1,
XVID_PPC_2 = 2,
XVID_PPC_4 = 4,
XVID_PPC_NUM_SUPPORTED = 3,
} XVid_PixelsPerClock;
/* Color space and chroma format. */
typedef enum {
XVID_CS_RGB = 0,
XVID_CS_YCRCB_444,
XVID_CS_YCRCB_422,
XVID_CS_YCRCB_420,
XVID_CS_NUM_SUPPORTED,
XVID_CS_UNKNOWN
} XVid_ColorFormat;
/* Color space conversion standard. */
typedef enum {
XVID_BT_2020 = 0,
XVID_BT_709,
XVID_BT_601,
XVID_BT_NUM_SUPPORTED,
XVID_BT_UNKNOWN
} XVid_ColorConversionStd;
/* Color conversion output range. */
typedef enum {
XVID_CR_16_235 = 0,
XVID_CR_16_240,
XVID_CR_0_255,
XVID_CR_NUM_SUPPORTED,
XVID_CR_UNKNOWN_RANGE
} XVid_ColorRange;
/****************************** Type Definitions ******************************/
/**
* Video timing structure.
*/
typedef struct {
u16 HActive;
u16 HFrontPorch;
u16 HSyncWidth;
u16 HBackPorch;
u16 HTotal;
u8 HSyncPolarity;
u16 VActive;
u16 F0PVFrontPorch;
u16 F0PVSyncWidth;
u16 F0PVBackPorch;
u16 F0PVTotal;
u16 F1VFrontPorch;
u16 F1VSyncWidth;
u16 F1VBackPorch;
u16 F1VTotal;
u8 VSyncPolarity;
} XVid_VideoTiming;
/**
* Video stream structure.
*/
typedef struct {
XVid_ColorFormat ColorFormatId;
XVid_ColorDepth ColorDepth;
XVid_PixelsPerClock PixPerClk;
XVid_FrameRate FrameRate;
u8 IsInterlaced;
XVid_VideoMode VmId;
XVid_VideoTiming Timing;
} XVid_VideoStream;
/**
* Video window structure.
*/
typedef struct {
u32 StartX;
u32 StartY;
u32 Width;
u32 Height;
} XVid_VideoWindow;
/**
* Video timing mode from the video timing table.
*/
typedef struct {
XVid_VideoMode VmId;
const char Name[21];
XVid_FrameRate FrameRate;
XVid_VideoTiming Timing;
} XVid_VideoTimingMode;
/*************************** Variable Declarations ****************************/
extern const XVid_VideoTimingMode XVid_VideoTimingModes[XVID_VM_NUM_SUPPORTED];
/**************************** Function Prototypes *****************************/
u32 XVid_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 Fr);
u32 XVid_GetPixelClockHzByVmId(XVid_VideoMode VmId);
XVid_VideoFormat XVid_IsVideoFormatInterlaced(XVid_VideoMode VmId);
#endif /* XVID_H_ */

64
XilinxProcessorIPLib/drivers/video_common/src/xvid.c → XilinxProcessorIPLib/drivers/video_common/src/xvidc.c
View file

@ -32,7 +32,7 @@
/******************************************************************************/
/**
*
* @file xvid.c
* @file xvidc.c
*
* Contains common utility functions that are typically used by video-related
* drivers and applications.
@ -51,19 +51,47 @@
/******************************* Include Files ********************************/
#include "xvid.h"
#include "xvidc.h"
u32 XVid_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 Fr)
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function calculates pixel clock based on the inputs.
*
* @param HTotal specifies horizontal total.
* @param VTotal specifies vertical total.
* @param FrameRate specifies rate at which frames are generated.
*
* @return Pixel clock in Hz.
*
* @note None.
*
******************************************************************************/
u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate)
{
return (HTotal * VTotal * Fr);
return (HTotal * VTotal * FrameRate);
}
u32 XVid_GetPixelClockHzByVmId(XVid_VideoMode VmId)
/*****************************************************************************/
/**
*
* This function calculates pixel clock from video mode.
*
* @param VmId specifies the resolution id.
*
* @return Pixel clock in Hz.
*
* @note None.
*
******************************************************************************/
u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId)
{
u32 ClkHz;
XVid_VideoTimingMode *VmPtr;
const XVidC_VideoTimingMode *VmPtr;
VmPtr = &XVid_VideoTimingModes[VmId];
VmPtr = &XVidC_VideoTimingModes[VmId];
/* For pixel clock calculation, use frame with the larger vertical
* total. This is useful for interlaced modes with frames that don't
@ -86,11 +114,25 @@ u32 XVid_GetPixelClockHzByVmId(XVid_VideoMode VmId)
return ClkHz;
}
XVid_VideoFormat XVid_IsVideoFormatInterlaced(XVid_VideoMode VmId)
/*****************************************************************************/
/**
*
* This function check input video mode is interlaced/progressive.
*
* @param VmId specifies the resolution id.
*
* @return Video format.
* - XVIDC_VF_PROGRESSIVE
* - XVIDC_VF_INTERLACED
*
* @note None.
*
******************************************************************************/
XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId)
{
if (XVid_VideoTimingModes[VmId].Timing.F1VTotal == 0) {
return XVID_VM_PROGRESSIVE;
if (XVidC_VideoTimingModes[VmId].Timing.F1VTotal == 0) {
return (XVIDC_VF_PROGRESSIVE);
}
return XVID_VM_INTERLACED;
return (XVIDC_VF_INTERLACED);
}

360
XilinxProcessorIPLib/drivers/video_common/src/xvidc.h Normal file
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@ -0,0 +1,360 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xvidc.h
*
* Contains common structures, definitions, macros, and utility functions that
* are typically used by video-related drivers and applications.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 rc, 01/10/15 Initial release.
* als
* </pre>
*
*******************************************************************************/
#ifndef XVIDC_H_
/* Prevent circular inclusions by using protection macros. */
#define XVIDC_H_
/******************************* Include Files ********************************/
#include "xil_types.h"
/************************** Constant Definitions ******************************/
/**
* This typedef enumerates the list of available standard display monitor
* timings as specified in the xvidc_timings_table.c file. The naming format is:
*
* XVIDC_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|I>(_RB)
*
* Where RB stands for reduced blanking.
*/
typedef enum {
/* Interlaced modes. */
XVIDC_VM_480_30_I = 0,
XVIDC_VM_576_25_I,
XVIDC_VM_1080_25_I,
XVIDC_VM_1080_30_I,
/* Progressive modes. */
XVIDC_VM_640x350_85_P,
XVIDC_VM_640x480_60_P,
XVIDC_VM_640x480_72_P,
XVIDC_VM_640x480_75_P,
XVIDC_VM_640x480_85_P,
XVIDC_VM_720x400_85_P,
XVIDC_VM_720x480_60_P,
XVIDC_VM_800x600_56_P,
XVIDC_VM_800x600_60_P,
XVIDC_VM_800x600_72_P,
XVIDC_VM_800x600_75_P,
XVIDC_VM_800x600_85_P,
XVIDC_VM_800x600_120_P_RB,
XVIDC_VM_848x480_60_P,
XVIDC_VM_1024x768_60_P,
XVIDC_VM_1024x768_70_P,
XVIDC_VM_1024x768_75_P,
XVIDC_VM_1024x768_85_P,
XVIDC_VM_1024x768_120_P_RB,
XVIDC_VM_1152x864_75_P,
XVIDC_VM_1280x720_50_P,
XVIDC_VM_1280x720_60_P,
XVIDC_VM_1280x768_60_P_RB,
XVIDC_VM_1280x768_60_P,
XVIDC_VM_1280x768_75_P,
XVIDC_VM_1280x768_85_P,
XVIDC_VM_1280x768_120_P_RB,
XVIDC_VM_1280x800_60_P_RB,
XVIDC_VM_1280x800_60_P,
XVIDC_VM_1280x800_75_P,
XVIDC_VM_1280x800_85_P,
XVIDC_VM_1280x800_120_P_RB,
XVIDC_VM_1280x960_60_P,
XVIDC_VM_1280x960_85_P,
XVIDC_VM_1280x960_120_P_RB,
XVIDC_VM_1280x1024_60_P,
XVIDC_VM_1280x1024_75_P,
XVIDC_VM_1280x1024_85_P,
XVIDC_VM_1280x1024_120_P_RB,
XVIDC_VM_1360x768_60_P,
XVIDC_VM_1360x768_120_P_RB,
XVIDC_VM_1366x768_60_P,
XVIDC_VM_1400x1050_60_P_RB,
XVIDC_VM_1400x1050_60_P,
XVIDC_VM_1400x1050_75_P,
XVIDC_VM_1400x1050_85_P,
XVIDC_VM_1400x1050_120_P_RB,
XVIDC_VM_1440x900_60_P_RB,
XVIDC_VM_1440x900_60_P,
XVIDC_VM_1440x900_75_P,
XVIDC_VM_1440x900_85_P,
XVIDC_VM_1440x900_120_P_RB,
XVIDC_VM_1600x1200_60_P,
XVIDC_VM_1600x1200_65_P,
XVIDC_VM_1600x1200_70_P,
XVIDC_VM_1600x1200_75_P,
XVIDC_VM_1600x1200_85_P,
XVIDC_VM_1600x1200_120_P_RB,
XVIDC_VM_1680x1050_60_P_RB,
XVIDC_VM_1680x1050_60_P,
XVIDC_VM_1680x1050_75_P,
XVIDC_VM_1680x1050_85_P,
XVIDC_VM_1680x1050_120_P_RB,
XVIDC_VM_1792x1344_60_P,
XVIDC_VM_1792x1344_75_P,
XVIDC_VM_1792x1344_120_P_RB,
XVIDC_VM_1856x1392_60_P,
XVIDC_VM_1856x1392_75_P,
XVIDC_VM_1856x1392_120_P_RB,
XVIDC_VM_1920x1080_24_P,
XVIDC_VM_1920x1080_25_P,
XVIDC_VM_1920x1080_30_P,
XVIDC_VM_1920x1080_50_P,
XVIDC_VM_1920x1080_60_P,
XVIDC_VM_1920x1200_60_P_RB,
XVIDC_VM_1920x1200_60_P,
XVIDC_VM_1920x1200_75_P,
XVIDC_VM_1920x1200_85_P,
XVIDC_VM_1920x1200_120_P_RB,
XVIDC_VM_1920x1440_60_P,
XVIDC_VM_1920x1440_75_P,
XVIDC_VM_1920x1440_120_P_RB,
XVIDC_VM_1920x2160_60_P,
XVIDC_VM_2560x1600_60_P_RB,
XVIDC_VM_2560x1600_60_P,
XVIDC_VM_2560x1600_75_P,
XVIDC_VM_2560x1600_85_P,
XVIDC_VM_2560x1600_120_P_RB,
XVIDC_VM_3840x2160_24_P,
XVIDC_VM_3840x2160_25_P,
XVIDC_VM_3840x2160_30_P,
XVIDC_VM_3840x2160_60_P,
XVIDC_VM_NUM_SUPPORTED,
XVIDC_VM_USE_EDID_PREFERRED,
XVIDC_VM_NO_INPUT,
XVIDC_VM_NOT_SUPPORTED,
/* Marks beginning/end of interlaced/progressive modes in the table. */
XVIDC_VM_INTL_START = XVIDC_VM_480_30_I,
XVIDC_VM_PROG_START = XVIDC_VM_640x350_85_P,
XVIDC_VM_INTL_END = (XVIDC_VM_PROG_START - 1),
XVIDC_VM_PROG_END = (XVIDC_VM_NUM_SUPPORTED - 1),
/* Common naming. */
XVIDC_VM_480_60_P = XVIDC_VM_720x480_60_P,
XVIDC_VM_720_50_P = XVIDC_VM_1280x720_50_P,
XVIDC_VM_720_60_P = XVIDC_VM_1280x720_60_P,
XVIDC_VM_WXGA_60_P = XVIDC_VM_1366x768_60_P,
XVIDC_VM_UXGA_60_P = XVIDC_VM_1600x1200_60_P,
XVIDC_VM_WSXGA_60_P = XVIDC_VM_1680x1050_60_P,
XVIDC_VM_1080_24_P = XVIDC_VM_1920x1080_24_P,
XVIDC_VM_1080_25_P = XVIDC_VM_1920x1080_25_P,
XVIDC_VM_1080_30_P = XVIDC_VM_1920x1080_30_P,
XVIDC_VM_1080_50_P = XVIDC_VM_1920x1080_50_P,
XVIDC_VM_1080_60_P = XVIDC_VM_1920x1080_60_P,
XVIDC_VM_WUXGA_60_P = XVIDC_VM_1920x1200_60_P,
XVIDC_VM_UHD2_60_P = XVIDC_VM_1920x2160_60_P,
XVIDC_VM_UHD_24_P = XVIDC_VM_3840x2160_24_P,
XVIDC_VM_UHD_25_P = XVIDC_VM_3840x2160_25_P,
XVIDC_VM_UHD_30_P = XVIDC_VM_3840x2160_30_P,
XVIDC_VM_UHD_60_P = XVIDC_VM_3840x2160_60_P
} XVidC_VideoMode;
/**
* Progressive/interlaced video format.
*/
typedef enum {
XVIDC_VF_PROGRESSIVE = 0,
XVIDC_VF_INTERLACED
} XVidC_VideoFormat;
/**
* Frame rate.
*/
typedef enum {
XVIDC_FR_24HZ = 24,
XVIDC_FR_25HZ = 25,
XVIDC_FR_30HZ = 30,
XVIDC_FR_50HZ = 50,
XVIDC_FR_56HZ = 56,
XVIDC_FR_60HZ = 60,
XVIDC_FR_65HZ = 65,
XVIDC_FR_67HZ = 67,
XVIDC_FR_70HZ = 70,
XVIDC_FR_72HZ = 72,
XVIDC_FR_75HZ = 75,
XVIDC_FR_85HZ = 85,
XVIDC_FR_87HZ = 87,
XVIDC_FR_88HZ = 88,
XVIDC_FR_100HZ = 100,
XVIDC_FR_120HZ = 120,
XVIDC_FR_NUM_SUPPORTED = 16,
XVIDC_FR_UNKNOWN
} XVidC_FrameRate;
/**
* Color depth - bits per color component.
*/
typedef enum {
XVIDC_BPC_6 = 6,
XVIDC_BPC_8 = 8,
XVIDC_BPC_10 = 10,
XVIDC_BPC_12 = 12,
XVIDC_BPC_16 = 16,
XVIDC_BPC_NUM_SUPPORTED = 5,
XVIDC_BPC_UNKNOWN
} XVidC_ColorDepth;
/**
* Pixels per clock.
*/
typedef enum {
XVIDC_PPC_1 = 1,
XVIDC_PPC_2 = 2,
XVIDC_PPC_4 = 4,
XVIDC_PPC_NUM_SUPPORTED = 3,
} XVidC_PixelsPerClock;
/**
* Color space format.
*/
typedef enum {
XVIDC_CSF_RGB = 0,
XVIDC_CSF_YCRCB_444,
XVIDC_CSF_YCRCB_422,
XVIDC_CSF_YCRCB_420,
XVIDC_CSF_NUM_SUPPORTED,
XVIDC_CSF_UNKNOWN
} XVidC_ColorSpace;
/**
* Color space conversion standard.
*/
typedef enum {
XVIDC_BT_2020 = 0,
XVIDC_BT_709,
XVIDC_BT_601,
XVIDC_BT_NUM_SUPPORTED,
XVIDC_BT_UNKNOWN
} XVidC_ColorConversionStd;
/**
* Color conversion output range.
*/
typedef enum {
XVIDC_CR_16_235 = 0,
XVIDC_CR_16_240,
XVIDC_CR_0_255,
XVIDC_CR_NUM_SUPPORTED,
XVIDC_CR_UNKNOWN_RANGE
} XVidC_ColorRange;
/****************************** Type Definitions ******************************/
/**
* Video timing structure.
*/
typedef struct {
u16 HActive;
u16 HFrontPorch;
u16 HSyncWidth;
u16 HBackPorch;
u16 HTotal;
u8 HSyncPolarity;
u16 VActive;
u16 F0PVFrontPorch;
u16 F0PVSyncWidth;
u16 F0PVBackPorch;
u16 F0PVTotal;
u16 F1VFrontPorch;
u16 F1VSyncWidth;
u16 F1VBackPorch;
u16 F1VTotal;
u8 VSyncPolarity;
} XVidC_VideoTiming;
/**
* Video stream structure.
*/
typedef struct {
XVidC_ColorSpace ColorSpaceId;
XVidC_ColorDepth ColorDepth;
XVidC_PixelsPerClock PixPerClk;
XVidC_FrameRate FrameRate;
u8 IsInterlaced;
XVidC_VideoMode VmId;
XVidC_VideoTiming Timing;
} XVidC_VideoStream;
/**
* Video window structure.
*/
typedef struct {
u32 StartX;
u32 StartY;
u32 Width;
u32 Height;
} XVidC_VideoWindow;
/**
* Video timing mode from the video timing table.
*/
typedef struct {
XVidC_VideoMode VmId;
const char Name[21];
XVidC_FrameRate FrameRate;
XVidC_VideoTiming Timing;
} XVidC_VideoTimingMode;
/**************************** Function Prototypes *****************************/
u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate);
u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId);
XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId);
/*************************** Variable Declarations ****************************/
extern const XVidC_VideoTimingMode
XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED];
#endif /* XVIDC_H_ */

458
XilinxProcessorIPLib/drivers/video_common/src/xvidc_edid.c Normal file
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@ -0,0 +1,458 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xvidc_edid.c
*
* Contains function definitions related to the Extended Display Identification
* Data (EDID) structure which is present in all monitors. All content in this
* file is agnostic of communication interface protocol.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 als 11/09/14 Initial release.
* </pre>
*
*******************************************************************************/
/******************************* Include Files ********************************/
#include "xvidc_edid.h"
/**************************** Function Prototypes *****************************/
static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode);
static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode);
static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode);
static float XVidC_CalculatePower(float Base, u8 Power);
static float XVidC_CalculateBinaryFraction(u16 Val, u8 DecPtIndex);
/**************************** Function Definitions ****************************/
void XVidC_EdidGetVpiIdManName(u8 *EdidRaw, char ManName[4])
{
ManName[0] = 0x40 + ((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] &
XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK) >>
XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT);
ManName[1] = 0x40 + (((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] &
XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK) <<
XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS) |
(EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] >>
XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT));
ManName[2] = 0x40 + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] &
XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK);
ManName[3] = '\0';
}
u8 XVidC_EdidGetBDispVidDigBpc(u8 *EdidRaw)
{
u8 Bpc;
switch (((EdidRaw[XVIDC_EDID_BDISP_VID] &
XVIDC_EDID_BDISP_VID_DIG_BPC_MASK) >>
XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT)) {
case XVIDC_EDID_BDISP_VID_DIG_BPC_6:
Bpc = 6;
break;
case XVIDC_EDID_BDISP_VID_DIG_BPC_8:
Bpc = 8;
break;
case XVIDC_EDID_BDISP_VID_DIG_BPC_10:
Bpc = 10;
break;
case XVIDC_EDID_BDISP_VID_DIG_BPC_12:
Bpc = 12;
break;
case XVIDC_EDID_BDISP_VID_DIG_BPC_14:
Bpc = 14;
break;
case XVIDC_EDID_BDISP_VID_DIG_BPC_16:
Bpc = 16;
break;
default:
Bpc = XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF;
break;
}
return Bpc;
}
float XVidC_EdidGetCcRedX(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_REDX_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] >>
XVIDC_EDID_CC_RBX_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcRedY(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_REDY_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] &
XVIDC_EDID_CC_RBY_LOW_MASK) >>
XVIDC_EDID_CC_RBY_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcGreenX(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_GREENX_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] &
XVIDC_EDID_CC_GWX_LOW_MASK) >>
XVIDC_EDID_CC_GWX_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcGreenY(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_GREENY_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] &
XVIDC_EDID_CC_GWY_LOW_MASK), 9);
}
float XVidC_EdidGetCcBlueX(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_BLUEX_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] >>
XVIDC_EDID_CC_RBX_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcBlueY(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_BLUEY_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] &
XVIDC_EDID_CC_RBY_LOW_MASK) >> XVIDC_EDID_CC_RBY_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcWhiteX(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_WHITEX_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] &
XVIDC_EDID_CC_GWX_LOW_MASK) >> XVIDC_EDID_CC_GWX_LOW_SHIFT), 9);
}
float XVidC_EdidGetCcWhiteY(u8 *EdidRaw)
{
return XVidC_CalculateBinaryFraction(
(EdidRaw[XVIDC_EDID_CC_WHITEY_HIGH] <<
XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] &
XVIDC_EDID_CC_GWY_LOW_MASK), 9);
}
u16 XVidC_EdidGetStdTimingsV(u8 *EdidRaw, u8 StdTimingsNum)
{
u16 V;
switch (XVidC_EdidGetStdTimingsAr(EdidRaw, StdTimingsNum)) {
case XVIDC_EDID_STD_TIMINGS_AR_16_10:
V = (10 * XVidC_EdidGetStdTimingsH(EdidRaw,
StdTimingsNum)) / 16;
break;
case XVIDC_EDID_STD_TIMINGS_AR_4_3:
V = (3 * XVidC_EdidGetStdTimingsH(EdidRaw,
StdTimingsNum)) / 4;
break;
case XVIDC_EDID_STD_TIMINGS_AR_5_4:
V = (4 * XVidC_EdidGetStdTimingsH(EdidRaw,
StdTimingsNum)) / 5;
break;
default:
V = (9 * XVidC_EdidGetStdTimingsH(EdidRaw,
StdTimingsNum)) / 16;
break;
}
return V;
}
u32 XVidC_EdidIsVideoTimingSupported(u8 *EdidRaw, XVidC_VideoTimingMode *VtMode)
{
u32 Status;
/* Check if the video mode is the preferred timing. */
Status = XVidC_EdidIsVideoTimingSupportedPreferredTiming(EdidRaw,
VtMode);
if (Status == XST_SUCCESS) {
return Status;
}
/* Check established timings I, II, and III. */
Status = XVidC_EdidIsVideoTimingSupportedEstablishedTimings(EdidRaw,
VtMode);
if (Status == XST_SUCCESS) {
return Status;
}
/* Check in standard timings support. */
Status = XVidC_EdidIsVideoTimingSupportedStandardTimings(EdidRaw,
VtMode);
return Status;
}
static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode)
{
u8 *Ptm;
Ptm = &EdidRaw[XVIDC_EDID_PTM];
u32 HActive =
(((Ptm[XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4] &
XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >>
XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XVIDC_EDID_DTD_PTM_HRES_LSB];
u32 VActive =
(((Ptm[XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4] &
XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >>
XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XVIDC_EDID_DTD_PTM_VRES_LSB];
if (VtMode->Timing.F1VTotal != XVidC_EdidIsDtdPtmInterlaced(EdidRaw)) {
return (XST_FAILURE);
}
else if ((VtMode->Timing.HActive == HActive) &&
(VtMode->Timing.VActive == VActive)) {
return (XST_SUCCESS);
}
return XST_FAILURE;
}
static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode)
{
u32 Status = XST_FAILURE;
/* First, check established timings I, II, and III. */
if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 640) &&
(VtMode->FrameRate == XVIDC_FR_56HZ) &&
XVidC_EdidSuppEstTimings800x600_56(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVIDC_FR_60HZ) &&
XVidC_EdidSuppEstTimings640x480_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVIDC_FR_60HZ) &&
XVidC_EdidSuppEstTimings800x600_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVIDC_FR_60HZ) &&
XVidC_EdidSuppEstTimings1024x768_60(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVIDC_FR_67HZ) &&
XVidC_EdidSuppEstTimings640x480_67(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 720) &&
(VtMode->Timing.VActive == 400) &&
(VtMode->FrameRate == XVIDC_FR_70HZ) &&
XVidC_EdidSuppEstTimings720x400_70(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVIDC_FR_70HZ) &&
XVidC_EdidSuppEstTimings1024x768_70(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVIDC_FR_72HZ) &&
XVidC_EdidSuppEstTimings640x480_72(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVIDC_FR_72HZ) &&
XVidC_EdidSuppEstTimings800x600_72(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 640) &&
(VtMode->Timing.VActive == 480) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings640x480_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 800) &&
(VtMode->Timing.VActive == 600) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings800x600_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 832) &&
(VtMode->Timing.VActive == 624) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings832x624_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings1024x768_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1152) &&
(VtMode->Timing.VActive == 870) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings1152x870_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1280) &&
(VtMode->Timing.VActive == 1024) &&
(VtMode->FrameRate == XVIDC_FR_75HZ) &&
XVidC_EdidSuppEstTimings1280x1024_75(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 1024) &&
(VtMode->Timing.VActive == 768) &&
(VtMode->FrameRate == XVIDC_FR_87HZ) &&
XVidC_EdidSuppEstTimings1024x768_87(EdidRaw)) {
Status = XST_SUCCESS;
}
else if ((VtMode->Timing.HActive == 720) &&
(VtMode->Timing.VActive == 400) &&
(VtMode->FrameRate == XVIDC_FR_88HZ) &&
XVidC_EdidSuppEstTimings720x400_88(EdidRaw)) {
Status = XST_SUCCESS;
}
return Status;
}
static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode)
{
u8 Index;
for (Index = 0; Index < 8; Index++) {
if ((VtMode->Timing.HActive ==
XVidC_EdidGetStdTimingsH(EdidRaw, Index + 1)) &&
(VtMode->Timing.VActive ==
XVidC_EdidGetStdTimingsV(EdidRaw, Index + 1)) &&
(VtMode->FrameRate == (u8)XVidC_EdidGetStdTimingsFrr(
EdidRaw, Index + 1))) {
return XST_SUCCESS;
}
}
return XST_FAILURE;
}
/******************************************************************************/
/**
* Perform a power operation.
*
* @param Base is b in the power operation, b^n.
* @param Power is n in the power operation, b^n.
*
* @return Base^Power (Base to the power of Power).
*
* @note None.
*
*******************************************************************************/
static float XVidC_CalculatePower(float Base, u8 Power)
{
u8 Index;
float Res = 1.0;
for (Index = 0; Index < Power; Index++) {
Res *= Base;
}
return Res;
}
/******************************************************************************/
/**
* Convert a fractional binary number into a decimal number. Binary digits to
* the right of the decimal point represent 2^-1 to 2^-(DecPtIndex+1). Binary
* digits to the left of the decimal point represent 2^0, 2^1, etc.
*
* @param Val is the binary representation of the fraction.
* @param DecPtIndex is the index of the decimal point in the binary
* number. The decimal point is between the binary digits at Val's
* indices (DecPtIndex) and (DecPtIndex + 1).
*
* @return Base^Power (Base to the power of Power).
*
* @note None.
*
*******************************************************************************/
static float XVidC_CalculateBinaryFraction(u16 Val, u8 DecPtIndex)
{
int Index;
float Res;
for (Index = DecPtIndex, Res = 0; Index >= 0; Index--) {
if (((Val >> Index) & 0x1) == 1) {
Res += XVidC_CalculatePower(
0.5, DecPtIndex - Index + 1);
}
}
return (Val >> (DecPtIndex + 1)) + Res;
}

479
XilinxProcessorIPLib/drivers/video_common/src/xvidc_edid.h Normal file
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@ -0,0 +1,479 @@
/*******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xvidc_edid.h
*
* Contains macros, definitions, and function declarations related to the
* Extended Display Identification Data (EDID) structure which is present in all
* monitors. All content in this file is agnostic of communication interface
* protocol.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 als 11/09/14 Initial release.
* </pre>
*
*******************************************************************************/
#ifndef XVIDC_EDID_H_
/* Prevent circular inclusions by using protection macros. */
#define XVIDC_EDID_H_
/******************************* Include Files ********************************/
#include "xstatus.h"
#include "xvidc.h"
/************************** Constant Definitions ******************************/
/** @name Address mapping for the base EDID block.
* @{
*/
#define XVIDC_EDID_HEADER 0x00
/* Vendor and product identification. */
#define XVIDC_EDID_VPI_ID_MAN_NAME0 0x08
#define XVIDC_EDID_VPI_ID_MAN_NAME1 0x09
#define XVIDC_EDID_VPI_ID_PROD_CODE_LSB 0x0A
#define XVIDC_EDID_VPI_ID_PROD_CODE_MSB 0x0B
#define XVIDC_EDID_VPI_ID_SN0 0x0C
#define XVIDC_EDID_VPI_ID_SN1 0x0D
#define XVIDC_EDID_VPI_ID_SN2 0x0E
#define XVIDC_EDID_VPI_ID_SN3 0x0F
#define XVIDC_EDID_VPI_WEEK_MAN 0x10
#define XVIDC_EDID_VPI_YEAR 0x11
/* EDID structure version and revision. */
#define XVIDC_EDID_STRUCT_VER 0x12
#define XVIDC_EDID_STRUCT_REV 0x13
/* Basic display parameters and features. */
#define XVIDC_EDID_BDISP_VID 0x14
#define XVIDC_EDID_BDISP_H_SSAR 0x15
#define XVIDC_EDID_BDISP_V_SSAR 0x16
#define XVIDC_EDID_BDISP_GAMMA 0x17
#define XVIDC_EDID_BDISP_FEATURE 0x18
/* Color characteristics (display x,y chromaticity coordinates). */
#define XVIDC_EDID_CC_RG_LOW 0x19
#define XVIDC_EDID_CC_BW_LOW 0x1A
#define XVIDC_EDID_CC_REDX_HIGH 0x1B
#define XVIDC_EDID_CC_REDY_HIGH 0x1C
#define XVIDC_EDID_CC_GREENX_HIGH 0x1D
#define XVIDC_EDID_CC_GREENY_HIGH 0x1E
#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F
#define XVIDC_EDID_CC_BLUEY_HIGH 0x20
#define XVIDC_EDID_CC_WHITEX_HIGH 0x21
#define XVIDC_EDID_CC_WHITEY_HIGH 0x22
/* Established timings. */
#define XVIDC_EDID_EST_TIMINGS_I 0x23
#define XVIDC_EDID_EST_TIMINGS_II 0x24
#define XVIDC_EDID_EST_TIMINGS_MAN 0x25
/* Standard timings. */
#define XVIDC_EDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1))
#define XVIDC_EDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1))
/* 18 byte descriptors. */
#define XVIDC_EDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1))
#define XVIDC_EDID_PTM (XVIDC_EDID_18BYTE_DESCRIPTOR(1))
/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00
#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01
#define XVIDC_EDID_DTD_PTM_HRES_LSB 0x02
#define XVIDC_EDID_DTD_PTM_HBLANK_LSB 0x03
#define XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4 0x04
#define XVIDC_EDID_DTD_PTM_VRES_LSB 0x05
#define XVIDC_EDID_DTD_PTM_VBLANK_LSB 0x06
#define XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4 0x07
#define XVIDC_EDID_DTD_PTM_HFPORCH_LSB 0x08
#define XVIDC_EDID_DTD_PTM_HSPW_LSB 0x09
#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B
#define XVIDC_EDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C
#define XVIDC_EDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D
#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E
#define XVIDC_EDID_DTD_PTM_HBORDER 0x0F
#define XVIDC_EDID_DTD_PTM_VBORDER 0x10
#define XVIDC_EDID_DTD_PTM_SIGNAL 0x11
/* Extension block count. */
#define XVIDC_EDID_EXT_BLK_COUNT 0x7E
/* Checksum. */
#define XVIDC_EDID_CHECKSUM 0x7F
/* @} */
/******************************************************************************/
/** @name Extended Display Identification Data: Masks, shifts, and values.
* @{
*/
#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2
#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2)
#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03
#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS 3
#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5
#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F
/* Basic display parameters and features: Video input definition. */
#define XVIDC_EDID_BDISP_VID_VSI_SHIFT 7
#define XVIDC_EDID_BDISP_VID_VSI_MASK (0x01 << 7)
#define XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT 5
#define XVIDC_EDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5)
#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0
#define XVIDC_EDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1
#define XVIDC_EDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2
#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3
#define XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4)
#define XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3)
#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2)
#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1)
#define XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01)
#define XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT 4
#define XVIDC_EDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4)
#define XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF 0x0
#define XVIDC_EDID_BDISP_VID_DIG_BPC_6 0x1
#define XVIDC_EDID_BDISP_VID_DIG_BPC_8 0x2
#define XVIDC_EDID_BDISP_VID_DIG_BPC_10 0x3
#define XVIDC_EDID_BDISP_VID_DIG_BPC_12 0x4
#define XVIDC_EDID_BDISP_VID_DIG_BPC_14 0x5
#define XVIDC_EDID_BDISP_VID_DIG_BPC_16 0x6
#define XVIDC_EDID_BDISP_VID_DIG_VIS_MASK 0xF
#define XVIDC_EDID_BDISP_VID_DIG_VIS_UNDEF 0x0
#define XVIDC_EDID_BDISP_VID_DIG_VIS_DVI 0x1
#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIA 0x2
#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIB 0x3
#define XVIDC_EDID_BDISP_VID_DIG_VIS_MDDI 0x4
#define XVIDC_EDID_BDISP_VID_DIG_VIS_DP 0x5
/* Basic display parameters and features: Feature support. */
#define XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7)
#define XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6)
#define XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5)
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3)
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2
#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3
#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3)
#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4)
#define XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2)
#define XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1)
#define XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK (0x1)
/* Color characteristics (display x,y chromaticity coordinates). */
#define XVIDC_EDID_CC_HIGH_SHIFT 2
#define XVIDC_EDID_CC_RBX_LOW_SHIFT 6
#define XVIDC_EDID_CC_RBY_LOW_SHIFT 4
#define XVIDC_EDID_CC_RBY_LOW_MASK (0x3 << 4)
#define XVIDC_EDID_CC_GWX_LOW_SHIFT 2
#define XVIDC_EDID_CC_GWX_LOW_MASK (0x3 << 2)
#define XVIDC_EDID_CC_GWY_LOW_MASK (0x3)
#define XVIDC_EDID_CC_GREENY_HIGH 0x1E
#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F
#define XVIDC_EDID_CC_BLUEY_HIGH 0x20
#define XVIDC_EDID_CC_WHITEX_HIGH 0x21
#define XVIDC_EDID_CC_WHITEY_HIGH 0x22
/* Established timings. */
#define XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7)
#define XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6)
#define XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5)
#define XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4)
#define XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3)
#define XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2)
#define XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1)
#define XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK (0x1)
#define XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7)
#define XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6)
#define XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5)
#define XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4)
#define XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3)
#define XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2)
#define XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1)
#define XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1)
#define XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7)
#define XVIDC_EDID_EST_TIMINGS_MAN_MASK (0x7F)
/* Standard timings. */
#define XVIDC_EDID_STD_TIMINGS_AR_SHIFT 6
#define XVIDC_EDID_STD_TIMINGS_AR_16_10 0x0
#define XVIDC_EDID_STD_TIMINGS_AR_4_3 0x1
#define XVIDC_EDID_STD_TIMINGS_AR_5_4 0x2
#define XVIDC_EDID_STD_TIMINGS_AR_16_9 0x3
#define XVIDC_EDID_STD_TIMINGS_FRR_MASK (0x3F)
/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F
#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0
#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4
#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F
#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0
#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4
#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2
#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F
#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0
#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4
#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80
#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7
#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02
#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04
#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1
#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2
/* @} */
/******************* Macros (Inline Functions) Definitions ********************/
#define XVidC_EdidIsHeaderValid(E) \
!memcmp(E, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)
/* Vendor and product identification: ID manufacturer name. */
/* void XVidC_EdidGetVpiIdManName(u8 *EdidRaw, char ManName[4]); */
/* Vendor and product identification: ID product code. */
#define XVidC_EdidGetVpiIdProdCode(E) \
((u16)((E[XVIDC_EDID_VPI_ID_PROD_CODE_MSB] << 8) | \
E[XVIDC_EDID_VPI_ID_PROD_CODE_LSB]))
/* Vendor and product identification: ID serial number. */
#define XVidC_EditGetVpiSn(E) \
((u32)((E[XVIDC_EDID_VPI_ID_SN3] << 24) | \
(E[XVIDC_EDID_VPI_ID_SN2] << 16) | (E[XVIDC_EDID_VPI_ID_SN1] << 8) | \
E[XVIDC_EDID_VPI_ID_SN0]))
/* Vendor and product identification: Week and year of manufacture or model
* year. */
#define XVidC_EdidGetVpiWeekMan(E) (E[XVIDC_EDID_VPI_WEEK_MAN])
#define XVidC_EdidGetVpiYear(E) (E[XVIDC_EDID_VPI_YEAR] + 1990)
#define XVidC_EdidIsVpiYearModel(E) (XVidC_EdidGetVpiWeekMan(E) == 0xFF)
#define XVidC_EdidIsVpiYearMab(E) (XVidC_EdidGetVpiWeekMan(E) != 0xFF)
/* EDID structure version and revision. */
#define XVidC_EdidGetStructVer(E) (E[XVIDC_EDID_STRUCT_VER])
#define XVidC_EdidGetStructRev(E) (E[XVIDC_EDID_STRUCT_REV])
/* Basic display parameters and features: Video input definition. */
#define XVidC_EdidIsBDispVidVsiDigital(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) != 0)
#define XVidC_EdidIsBDispVidVsiAnalog(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) == 0)
#define XVidC_EdidGetBDispVidAnaSls(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SLS_MASK) >> \
XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT)
#define XVidC_Edid_SuppBDispVidAnaVidSetup(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK) != 0)
#define XVidC_EdidSuppBDispVidAnaSepSyncHv(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK) != 0)
#define XVidC_EdidSuppBDispVidAnaCompSuncH(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK) != 0)
#define XVidC_EdidSupp_BDispVidAnaCompSyncG(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK) != 0)
#define XVidC_EdidSuppBDispVidAnaSerrVsync(E) \
((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK) != 0)
/* u8 XVidC_EdidGetBDispVidDigBpc(u8 *EdidRaw); */
#define XVidC_EdidGetBDispVidDigVis(E) \
(E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_DIG_VIS_MASK)
/* Basic display parameters and features: Horizontal and vertical screen size or
* aspect ratio. */
#define XVidC_EdidIBDispSsarDefined(E) \
((E[XVIDC_EDID_BDISP_H_SSAR] | E[XVIDC_EDID_BDISP_V_SSAR]) != 0)
#define XVidC_EdidGetBDispSsArH(E) E[XVIDC_EDID_BDISP_H_SSAR]
#define XVidC_EdidGetBDispSsArV(E) E[XVIDC_EDID_BDISP_V_SSAR]
#define XVidC_EdidIsBDispSsArSs(E) \
((XVIDC_EDID_GET_BDISP_SSAR_H(E) != 0) && \
(XVIDC_EDID_GET_BDISP_SSAR_V(E) != 0))
#define XVidC_EdidIsBDispSsArArL(E) \
((XVIDC_EDID_GET_BDISP_SSAR_H(E) != 0) && \
(XVIDC_EDID_GET_BDISP_SSAR_V(E) == 0))
#define XVidC_EdidIsBDispSsArArP(E) \
((XVIDC_EDID_GET_BDISP_SSAR_H(E) == 0) && \
(XVIDC_EDID_GET_BDISP_SSAR_V(E) != 0))
#define XVidC_Edid_GetBDispSsArArL(E) \
((float)((XVIDC_EDID_GET_BDISP_SSAR_H(E) + 99.0) / 100.0))
#define XVidC_Edid_GetBDispSsArArP(E) \
((float)(100.0 / (XVIDC_EDID_GET_BDISP_SSAR_V(E) + 99.0)))
/* Basic display parameters and features: Gamma. */
#define XVidC_EdidIsBDispGammaInExt(E) (E[XVIDC_EDID_BDISP_GAMMA] == 0xFF)
#define XVidC_EdidGetBDispGamma(E) \
((float)((E[XVIDC_EDID_BDISP_GAMMA] + 100.0) / 100.0))
/* Basic display parameters and features: Feature support. */
#define XVidC_EdidSuppBDispFeaturePmStandby(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK) != 0)
#define XVidC_EdidSuppBDispFeaturePmSuspend(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK) != 0)
#define XVidC_EdidSuppBDispFeaturePmOffVlp(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK) != 0)
#define XVidC_EdidGetBDispFeatureAnaColorType(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK) >> \
XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT)
#define XVidC_EdidSuppBDispFeatureDidColorEncYCrCb444(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK) != 0)
#define XVidC_EdidSuppBDispFeatureDigColorEncYCrCb422(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK) != 0)
#define XVidC_EdidIsBDispFeatureSrgbDef(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK) != 0)
#define XVidC_EdidIsBDispFeaturePtmInc(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK) != 0)
#define XVidC_EdidIsBDispFeatureContFreq(E) \
((E[XVIDC_EDID_BDISP_FEATURE] & \
XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK) != 0)
/* Color characterisitics (display x,y chromaticity coordinates). */
/* float XVidC_EdidGetCcRedX(u8 *EdidRaw); */
/* float XVidC_EdidGetCcRedY(u8 *EdidRaw); */
/* float XVidC_EdidGetCcGreenX(u8 *EdidRaw); */
/* float XVidC_EdidGetCcGreenY(u8 *EdidRaw); */
/* float XVidC_EdidGetCcBlueX(u8 *EdidRaw); */
/* float XVidC_EdidGetCcBlueY(u8 *EdidRaw); */
/* float XVidC_EdidGetCcWhiteX(u8 *EdidRaw); */
/* float XVidC_EdidGetCcWhiteY(u8 *EdidRaw); */
/* Established timings. */
#define XVidC_EdidSuppEstTimings720x400_70(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK) != 0)
#define XVidC_EdidSuppEstTimings720x400_88(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK) != 0)
#define XVidC_EdidSuppEstTimings640x480_60(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK) != 0)
#define XVidC_EdidSuppEstTimings640x480_67(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK) != 0)
#define XVidC_EdidSuppEstTimings640x480_72(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK) != 0)
#define XVidC_EdidSuppEstTimings640x480_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK) != 0)
#define XVidC_EdidSuppEstTimings800x600_56(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK) != 0)
#define XVidC_EdidSuppEstTimings800x600_60(E) \
((E[XVIDC_EDID_EST_TIMINGS_I] & \
XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK) != 0)
#define XVidC_EdidSuppEstTimings800x600_72(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK) != 0)
#define XVidC_EdidSuppEstTimings800x600_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK) != 0)
#define XVidC_EdidSuppEstTimings832x624_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK) != 0)
#define XVidC_EdidSuppEstTimings1024x768_87(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK) != 0)
#define XVidC_EdidSuppEstTimings1024x768_60(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK) != 0)
#define XVidC_EdidSuppEstTimings1024x768_70(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK) != 0)
#define XVidC_EdidSuppEstTimings1024x768_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK) != 0)
#define XVidC_EdidSuppEstTimings1280x1024_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_II] & \
XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK) != 0)
#define XVidC_EdidSuppEstTimings1152x870_75(E) \
((E[XVIDC_EDID_EST_TIMINGS_MAN] & \
XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK) != 0)
#define XVidC_EdidGetTimingsMan(E) \
(E[XVIDC_EDID_EST_TIMINGS_MAN] & XVIDC_EDID_EST_TIMINGS_MAN_MASK)
/* Standard timings. */
#define XVidC_EdidGetStdTimingsH(E, N) \
((E[XVIDC_EDID_STD_TIMINGS_H(N)] + 31) * 8)
#define XVidC_EdidGetStdTimingsAr(E, N) \
(E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] >> XVIDC_EDID_STD_TIMINGS_AR_SHIFT)
#define XVidC_EdidGetStdTimingsFrr(E, N) \
((E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] & \
XVIDC_EDID_STD_TIMINGS_FRR_MASK) + 60)
/* u16 XVidC_EdidGetStdTimingsV(u8 *EdidRaw, u8 StdTimingsNum); */
#define XVidC_EdidIsDtdPtmInterlaced(E) \
((E[XVIDC_EDID_PTM + XVIDC_EDID_DTD_PTM_SIGNAL] & \
XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \
XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT)
/* Extension block count. */
#define XVidC_EdidGetExtBlkCount(E) (E[XVIDC_EDID_EXT_BLK_COUNT])
/* Checksum. */
#define XVidC_EdidGetChecksum(E) (E[XVIDC_EDID_CHECKSUM])
/**************************** Function Prototypes *****************************/
/* Vendor and product identification: ID manufacturer name. */
void XVidC_EdidGetVpiIdManName(u8 *EdidRaw, char ManName[4]);
/* Basic display parameters and features: Video input definition. */
u8 XVidC_EdidGetBDispVidDigBpc(u8 *EdidRaw);
/* Color characteristics (display x,y chromaticity coordinates). */
float XVidC_EdidGetCcRedX(u8 *EdidRaw);
float XVidC_EdidGetCcRedY(u8 *EdidRaw);
float XVidC_EdidGetCcGreenX(u8 *EdidRaw);
float XVidC_EdidGetCcGreenY(u8 *EdidRaw);
float XVidC_EdidGetCcBlueX(u8 *EdidRaw);
float XVidC_EdidGetCcBlueY(u8 *EdidRaw);
float XVidC_EdidGetCcWhiteX(u8 *EdidRaw);
float XVidC_EdidGetCcWhiteY(u8 *EdidRaw);
/* Standard timings. */
u16 XVidC_EdidGetStdTimingsV(u8 *EdidRaw, u8 StdTimingsNum);
/* Utility functions. */
u32 XVidC_EdidIsVideoTimingSupported(u8 *EdidRaw,
XVidC_VideoTimingMode *VtMode);
#endif /* XVIDC_EDID_H_ */

202
XilinxProcessorIPLib/drivers/video_common/src/xvid_timings_table.c → XilinxProcessorIPLib/drivers/video_common/src/xvidc_timings_table.c
View file

@ -32,7 +32,7 @@
/******************************************************************************/
/**
*
* @file xvid_timings_table.c
* @file xvidc_timings_table.c
*
* Contains video timings for various standard resolutions.
*
@ -51,16 +51,16 @@
/******************************* Include Files ********************************/
#include "xvid.h"
#include "xvidc.h"
/**************************** Variable Definitions ****************************/
/**
* This table contains the main stream attributes for various standard
* resolutions. Each entry is of the format:
* 1) ID: XVID_VM_<HRES>x<VRES>_<FRAME RATE (HZ)>_<P|I>(_RB = Reduced Blanking)
* 1) ID: XVIDC_VM_<HRES>x<VRES>_<FRAME RATE (HZ)>_<P|I>(_RB = Reduced Blanking)
* 2) Resolution naming: "<HRES>x<VRES>@<FRAME RATE (HZ)>"
* 3) Frame rate: XVID_FR_<FRAME RATE (HZ)>
* 3) Frame rate: XVIDC_FR_<FRAME RATE (HZ)>
* 4) Video timing structure:
* 1) Horizontal active resolution (pixels)
* 2) Horizontal front porch (pixels)
@ -79,297 +79,297 @@
* 15) Frame 1: Vertical total (lines)
* 16) Vertical sync polarity (0=negative|1=positive)
*/
const XVid_VideoTimingMode XVid_VideoTimingModes[XVID_VM_NUM_SUPPORTED] =
const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED] =
{
/* Interlaced modes. */
{ XVID_VM_480_30_I, "720x480@30Hz (I)", XVID_FR_30HZ,
{ XVIDC_VM_480_30_I, "720x480@30Hz (I)", XVIDC_FR_30HZ,
{720, 19, 62, 57, 858, 0,
240, 4, 3, 15, 262, 4, 3, 16, 263, 0} },
{ XVID_VM_576_25_I, "720x576@25Hz (I)", XVID_FR_25HZ,
{ XVIDC_VM_576_25_I, "720x576@25Hz (I)", XVIDC_FR_25HZ,
{720, 12, 63, 69, 864, 0,
288, 2, 3, 19, 312, 2, 3, 20, 313, 0} },
{ XVID_VM_1080_25_I, "1920x1080@25Hz (I)", XVID_FR_25HZ,
{ XVIDC_VM_1080_25_I, "1920x1080@25Hz (I)", XVIDC_FR_25HZ,
{1920, 88, 44, 148, 2200, 1,
540, 2, 5, 15, 562, 2, 5, 16, 563, 1} },
{ XVID_VM_1080_30_I, "1920x1080@30Hz (I)", XVID_FR_30HZ,
{ XVIDC_VM_1080_30_I, "1920x1080@30Hz (I)", XVIDC_FR_30HZ,
{1920, 88, 44, 148, 2200, 1,
540, 2, 5, 15, 562, 2, 5, 16, 563, 1} },
/* Progressive modes. */
{ XVID_VM_640x350_85_P, "640x350@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_640x350_85_P, "640x350@85Hz", XVIDC_FR_85HZ,
{640, 32, 64, 96, 832, 1,
350, 32, 3, 60, 445, 0, 0, 0, 0, 0} },
{ XVID_VM_640x480_60_P, "640x480@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_640x480_60_P, "640x480@60Hz", XVIDC_FR_60HZ,
{640, 8+8, 96, 40+8, 800, 0,
480, 2+8, 2, 25+8, 525, 0, 0, 0, 0, 0} },
{ XVID_VM_640x480_72_P, "640x480@72Hz", XVID_FR_72HZ,
{ XVIDC_VM_640x480_72_P, "640x480@72Hz", XVIDC_FR_72HZ,
{640, 8+16, 40, 120+8, 832, 0,
480, 8+1, 3, 20+8, 520, 0, 0, 0, 0, 0} },
{ XVID_VM_640x480_75_P, "640x480@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_640x480_75_P, "640x480@75Hz", XVIDC_FR_75HZ,
{640, 16, 64, 120, 840, 0,
480, 1, 3, 16, 500, 0, 0, 0, 0, 0} },
{ XVID_VM_640x480_85_P, "640x480@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_640x480_85_P, "640x480@85Hz", XVIDC_FR_85HZ,
{640, 56, 56, 80, 832, 0,
480, 1, 3, 25, 509, 0, 0, 0, 0, 0} },
{ XVID_VM_720x400_85_P, "720x400@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_720x400_85_P, "720x400@85Hz", XVIDC_FR_85HZ,
{720, 36, 72, 108, 936, 0,
400, 1, 3, 42, 446, 0, 0, 0, 0, 1} },
{ XVID_VM_720x480_60_P, "720x480@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_720x480_60_P, "720x480@60Hz", XVIDC_FR_60HZ,
{720, 16, 62, 60, 858, 0,
480, 9, 6, 30, 525, 0, 0, 0, 0, 0} },
{ XVID_VM_800x600_56_P, "800x600@56Hz", XVID_FR_56HZ,
{ XVIDC_VM_800x600_56_P, "800x600@56Hz", XVIDC_FR_56HZ,
{800, 24, 72, 128, 1024, 1,
600, 1, 2, 22, 625, 0, 0, 0, 0, 1} },
{ XVID_VM_800x600_60_P, "800x600@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_800x600_60_P, "800x600@60Hz", XVIDC_FR_60HZ,
{800, 40, 128, 88, 1056, 1,
600, 1, 4, 23, 628, 0, 0, 0, 0, 1} },
{ XVID_VM_800x600_72_P, "800x600@72Hz", XVID_FR_72HZ,
{ XVIDC_VM_800x600_72_P, "800x600@72Hz", XVIDC_FR_72HZ,
{800, 56, 120, 64, 1040, 1,
600, 37, 6, 23, 666, 0, 0, 0, 0, 1} },
{ XVID_VM_800x600_75_P, "800x600@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_800x600_75_P, "800x600@75Hz", XVIDC_FR_75HZ,
{800, 16, 80, 160, 1056, 1,
600, 1, 3, 21, 625, 0, 0, 0, 0, 1} },
{ XVID_VM_800x600_85_P, "800x600@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_800x600_85_P, "800x600@85Hz", XVIDC_FR_85HZ,
{800, 32, 64, 152, 1048, 1,
600, 1, 3, 27, 631, 0, 0, 0, 0, 1} },
{ XVID_VM_800x600_120_P_RB, "800x700@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_800x600_120_P_RB, "800x700@120Hz (RB)", XVIDC_FR_120HZ,
{800, 48, 32, 80, 960, 1,
600, 3, 4, 29, 636, 0, 0, 0, 0, 0} },
{ XVID_VM_848x480_60_P, "848x480@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_848x480_60_P, "848x480@60Hz", XVIDC_FR_60HZ,
{848, 16, 112, 112, 1088, 1,
480, 6, 8, 23, 517, 0, 0, 0, 0, 1} },
{ XVID_VM_1024x768_60_P, "1024x768@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1024x768_60_P, "1024x768@60Hz", XVIDC_FR_60HZ,
{1024, 24, 136, 160, 1344, 0,
768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
{ XVID_VM_1024x768_70_P, "1024x768@70Hz", XVID_FR_70HZ,
{ XVIDC_VM_1024x768_70_P, "1024x768@70Hz", XVIDC_FR_70HZ,
{1024, 24, 136, 144, 1328, 0,
768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
{ XVID_VM_1024x768_75_P, "1024x768@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1024x768_75_P, "1024x768@75Hz", XVIDC_FR_75HZ,
{1024, 16, 96, 176, 1312, 1,
768, 1, 3, 28, 800, 0, 0, 0, 0, 1} },
{ XVID_VM_1024x768_85_P, "1024x768@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1024x768_85_P, "1024x768@85Hz", XVIDC_FR_85HZ,
{1024, 48, 96, 208, 1376, 1,
768, 1, 3, 36, 808, 0, 0, 0, 0, 1} },
{ XVID_VM_1024x768_120_P_RB, "1024x768@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1024x768_120_P_RB, "1024x768@120Hz (RB)", XVIDC_FR_120HZ,
{1024, 48, 32, 80, 1184, 1,
768, 3, 4, 38, 813, 0, 0, 0, 0, 0} },
{ XVID_VM_1152x864_75_P, "1152x864@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1152x864_75_P, "1152x864@75Hz", XVIDC_FR_75HZ,
{1152, 64, 128, 256, 1600, 1,
864, 1, 3, 32, 900, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x720_50_P, "1280x720@50Hz", XVID_FR_50HZ,
{ XVIDC_VM_1280x720_50_P, "1280x720@50Hz", XVIDC_FR_50HZ,
{1280, 440, 40, 220, 1980, 0,
720, 5, 5, 20, 750, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x720_60_P, "720p@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1280x720_60_P, "720p@60Hz", XVIDC_FR_60HZ,
{1280, 110, 40, 220, 1650, 0,
720, 5, 5, 20, 750, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x768_60_P_RB, "1280x768@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1280x768_60_P_RB, "1280x768@60Hz (RB)", XVIDC_FR_60HZ,
{1280, 48, 32, 80, 1440, 1,
768, 3, 7, 12, 790, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x768_60_P, "1280x768@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1280x768_60_P, "1280x768@60Hz", XVIDC_FR_60HZ,
{1280, 64, 128, 192, 1664, 0,
768, 3, 7, 20, 798, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x768_75_P, "1280x768@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1280x768_75_P, "1280x768@75Hz", XVIDC_FR_75HZ,
{1280, 80, 128, 208, 1696, 0,
768, 3, 7, 27, 805, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x768_85_P, "1280x768@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1280x768_85_P, "1280x768@85Hz", XVIDC_FR_85HZ,
{1280, 80, 136, 216, 1712, 0,
768, 3, 7, 31, 809, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x768_120_P_RB, "1280x768@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1280x768_120_P_RB, "1280x768@120Hz (RB)", XVIDC_FR_120HZ,
{1280, 48, 32, 80, 1440, 1,
768, 3, 7, 35, 813, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x800_60_P_RB, "1280x800@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1280x800_60_P_RB, "1280x800@60Hz (RB)", XVIDC_FR_60HZ,
{1280, 48, 32, 80, 1440, 1,
800, 3, 6, 14, 823, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x800_60_P, "1280x800@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1280x800_60_P, "1280x800@60Hz", XVIDC_FR_60HZ,
{1280, 72, 128, 200, 1680, 0,
800, 3, 6, 22, 831, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x800_75_P, "1280x800@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1280x800_75_P, "1280x800@75Hz", XVIDC_FR_75HZ,
{1280, 80, 128, 208, 1696, 0,
800, 3, 6, 29, 838, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x800_85_P, "1280x800@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1280x800_85_P, "1280x800@85Hz", XVIDC_FR_85HZ,
{1280, 80, 136, 216, 1712, 0,
800, 3, 6, 34, 843, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x800_120_P_RB, "1280x800@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1280x800_120_P_RB, "1280x800@120Hz (RB)", XVIDC_FR_120HZ,
{1280, 48, 32, 80, 1440, 1,
800, 3, 6, 38, 847, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x960_60_P, "1280x960@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1280x960_60_P, "1280x960@60Hz", XVIDC_FR_60HZ,
{1280, 96, 112, 312, 1800, 1,
960, 1, 3, 36, 1000, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x960_85_P, "1280x960@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1280x960_85_P, "1280x960@85Hz", XVIDC_FR_85HZ,
{1280, 64, 160, 224, 1728, 1,
960, 1, 3, 47, 1011, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x960_120_P_RB, "1280x960@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1280x960_120_P_RB, "1280x960@120Hz (RB)", XVIDC_FR_120HZ,
{1280, 48, 32, 80, 1440, 1,
960, 3, 4, 50, 1017, 0, 0, 0, 0, 0} },
{ XVID_VM_1280x1024_60_P, "1280x1024@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1280x1024_60_P, "1280x1024@60Hz", XVIDC_FR_60HZ,
{1280, 48, 112, 248, 1688, 1,
1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x1024_75_P, "1280x1024@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1280x1024_75_P, "1280x1024@75Hz", XVIDC_FR_75HZ,
{1280, 16, 144, 248, 1688, 1,
1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x1024_85_P, "1280x1024@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1280x1024_85_P, "1280x1024@85Hz", XVIDC_FR_85HZ,
{1280, 64, 160, 224, 1728, 1,
1024, 1, 3, 44, 1072, 0, 0, 0, 0, 1} },
{ XVID_VM_1280x1024_120_P_RB, "1280x1024@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1280x1024_120_P_RB, "1280x1024@120Hz (RB)", XVIDC_FR_120HZ,
{1280, 48, 32, 80, 1440, 1,
1024, 3, 7, 50, 1084, 0, 0, 0, 0, 0} },
{ XVID_VM_1360x768_60_P, "1360x768@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1360x768_60_P, "1360x768@60Hz", XVIDC_FR_60HZ,
{1360, 64, 112, 256, 1792, 1,
768, 3, 6, 18, 795, 0, 0, 0, 0, 1} },
{ XVID_VM_1360x768_120_P_RB, "1360x768@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1360x768_120_P_RB, "1360x768@120Hz (RB)", XVIDC_FR_120HZ,
{1360, 48, 32, 80, 1520, 1,
768, 3, 5, 37, 813, 0, 0, 0, 0, 0} },
{ XVID_VM_1366x768_60_P, "1366x768@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1366x768_60_P, "1366x768@60Hz", XVIDC_FR_60HZ,
{1366, 14, 56, 64, 1500, 1,
768, 1, 3, 28, 800, 0, 0, 0, 0, 1} },
{ XVID_VM_1400x1050_60_P_RB, "1400x1050@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1400x1050_60_P_RB, "1400x1050@60Hz (RB)", XVIDC_FR_60HZ,
{1400, 48, 32, 80, 1560, 1,
1050, 3, 4, 23, 1080, 0, 0, 0, 0, 0} },
{ XVID_VM_1400x1050_60_P, "1400x1050@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1400x1050_60_P, "1400x1050@60Hz", XVIDC_FR_60HZ,
{1400, 88, 144, 232, 1864, 0,
1050, 3, 4, 32, 1089, 0, 0, 0, 0, 1} },
{ XVID_VM_1400x1050_75_P, "1400x1050@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1400x1050_75_P, "1400x1050@75Hz", XVIDC_FR_75HZ,
{1400, 104, 144, 248, 1896, 0,
1050, 3, 4, 42, 1099, 0, 0, 0, 0, 1} },
{ XVID_VM_1400x1050_85_P, "1400x1050@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1400x1050_85_P, "1400x1050@85Hz", XVIDC_FR_85HZ,
{1400, 104, 152, 256, 1912, 0,
1050, 3, 4, 48, 1105, 0, 0, 0, 0, 1} },
{ XVID_VM_1400x1050_120_P_RB, "1400x1050@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1400x1050_120_P_RB, "1400x1050@120Hz (RB)", XVIDC_FR_120HZ,
{1400, 48, 32, 80, 1560, 1,
1050, 3, 4, 55, 1112, 0, 0, 0, 0, 0} },
{ XVID_VM_1440x900_60_P_RB, "1440x900@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1440x900_60_P_RB, "1440x900@60Hz (RB)", XVIDC_FR_60HZ,
{1440, 48, 32, 80, 1600, 1,
900, 3, 6, 17, 926, 0, 0, 0, 0, 0} },
{ XVID_VM_1440x900_60_P, "1440x900@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1440x900_60_P, "1440x900@60Hz", XVIDC_FR_60HZ,
{1440, 80, 152, 232, 1904, 0,
900, 3, 6, 25, 934, 0, 0, 0, 0, 1} },
{ XVID_VM_1440x900_75_P, "1440x900@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1440x900_75_P, "1440x900@75Hz", XVIDC_FR_75HZ,
{1440, 96, 152, 248, 1936, 0,
900, 3, 6, 33, 942, 0, 0, 0, 0, 1} },
{ XVID_VM_1440x900_85_P, "1440x900@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1440x900_85_P, "1440x900@85Hz", XVIDC_FR_85HZ,
{1440, 104, 152, 256, 1952, 0,
900, 3, 6, 39, 948, 0, 0, 0, 0, 1} },
{ XVID_VM_1440x900_120_P_RB, "1440x900@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1440x900_120_P_RB, "1440x900@120Hz (RB)", XVIDC_FR_120HZ,
{1440, 48, 32, 80, 1600, 1,
900, 3, 6, 44, 953, 0, 0, 0, 0, 0} },
{ XVID_VM_1600x1200_60_P, "1600x1200@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1600x1200_60_P, "1600x1200@60Hz", XVIDC_FR_60HZ,
{1600, 64, 192, 304, 2160, 1,
1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} },
{ XVID_VM_1600x1200_65_P, "1600x1200@65Hz", XVID_FR_65HZ,
{ XVIDC_VM_1600x1200_65_P, "1600x1200@65Hz", XVIDC_FR_65HZ,
{1600, 64, 192, 304, 2160, 1,
1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} },
{ XVID_VM_1600x1200_70_P, "1600x1200@70Hz", XVID_FR_70HZ,
{ XVIDC_VM_1600x1200_70_P, "1600x1200@70Hz", XVIDC_FR_70HZ,
{1600, 64, 192, 304, 2160, 1,
1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} },
{ XVID_VM_1600x1200_75_P, "1600x1200@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1600x1200_75_P, "1600x1200@75Hz", XVIDC_FR_75HZ,
{1600, 64, 192, 304, 2160, 1,
1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} },
{ XVID_VM_1600x1200_85_P, "1600x1200@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1600x1200_85_P, "1600x1200@85Hz", XVIDC_FR_85HZ,
{1600, 64, 192, 304, 2160, 1,
1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} },
{ XVID_VM_1600x1200_120_P_RB, "1600x1200@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1600x1200_120_P_RB, "1600x1200@120Hz (RB)", XVIDC_FR_120HZ,
{1600, 48, 32, 80, 1760, 1,
1200, 3, 4, 64, 1271, 0, 0, 0, 0, 0} },
{ XVID_VM_1680x1050_60_P_RB, "1680x1050@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1680x1050_60_P_RB, "1680x1050@60Hz (RB)", XVIDC_FR_60HZ,
{1680, 48, 32, 80, 1840, 1,
1050, 3, 6, 21, 1080, 0, 0, 0, 0, 0} },
{ XVID_VM_1680x1050_60_P, "1680x1050@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1680x1050_60_P, "1680x1050@60Hz", XVIDC_FR_60HZ,
{1680, 104, 176, 280, 2240, 0,
1050, 3, 6, 30, 1089, 0, 0, 0, 0, 1} },
{ XVID_VM_1680x1050_75_P, "1680x1050@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1680x1050_75_P, "1680x1050@75Hz", XVIDC_FR_75HZ,
{1680, 120, 176, 296, 2272, 0,
1050, 3, 6, 40, 1099, 0, 0, 0, 0, 1} },
{ XVID_VM_1680x1050_85_P, "1680x1050@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1680x1050_85_P, "1680x1050@85Hz", XVIDC_FR_85HZ,
{1680, 128, 176, 304, 2288, 0,
1050, 3, 6, 46, 1105, 0, 0, 0, 0, 1} },
{ XVID_VM_1680x1050_120_P_RB, "1680x1050@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1680x1050_120_P_RB, "1680x1050@120Hz (RB)", XVIDC_FR_120HZ,
{1680, 48, 32, 80, 1840, 1,
1050, 3, 6, 53, 1112, 0, 0, 0, 0, 0} },
{ XVID_VM_1792x1344_60_P, "1792x1344@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1792x1344_60_P, "1792x1344@60Hz", XVIDC_FR_60HZ,
{1792, 128, 200, 328, 2448, 0,
1344, 1, 3, 46, 1394, 0, 0, 0, 0, 1} },
{ XVID_VM_1792x1344_75_P, "1792x1344@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1792x1344_75_P, "1792x1344@75Hz", XVIDC_FR_75HZ,
{1792, 96, 216, 352, 2456, 0,
1344, 1, 3, 69, 1417, 0, 0, 0, 0, 1} },
{ XVID_VM_1792x1344_120_P_RB, "1792x1344@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1792x1344_120_P_RB, "1792x1344@120Hz (RB)", XVIDC_FR_120HZ,
{1792, 48, 32, 80, 1952, 1,
1344, 3, 4, 72, 1423, 0, 0, 0, 0, 0} },
{ XVID_VM_1856x1392_60_P, "1856x1392@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1856x1392_60_P, "1856x1392@60Hz", XVIDC_FR_60HZ,
{1856, 96, 224, 352, 2528, 0,
1392, 1, 3, 43, 1439, 0, 0, 0, 0, 1} },
{ XVID_VM_1856x1392_75_P, "1856x1392@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1856x1392_75_P, "1856x1392@75Hz", XVIDC_FR_75HZ,
{1856, 128, 224, 352, 2560, 0,
1392, 1, 3, 104, 1500, 0, 0, 0, 0, 1} },
{ XVID_VM_1856x1392_120_P_RB, "1856x1392@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1856x1392_120_P_RB, "1856x1392@120Hz (RB)", XVIDC_FR_120HZ,
{1856, 48, 32, 80, 2016, 1,
1392, 3, 4, 75, 1474, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1080_24_P, "1920x1080@24Hz", XVID_FR_24HZ,
{ XVIDC_VM_1920x1080_24_P, "1920x1080@24Hz", XVIDC_FR_24HZ,
{1920, 638, 44, 148, 2750, 0,
1080, 4, 5, 36, 1125, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1080_25_P, "1920x1080@25Hz", XVID_FR_25HZ,
{ XVIDC_VM_1920x1080_25_P, "1920x1080@25Hz", XVIDC_FR_25HZ,
{1920, 528, 44, 148, 2640, 0,
1080, 4, 5, 36, 1125, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1080_30_P, "1920x1080@30Hz", XVID_FR_30HZ,
{ XVIDC_VM_1920x1080_30_P, "1920x1080@30Hz", XVIDC_FR_30HZ,
{1920, 88, 44, 148, 2200, 0,
1080, 4, 5, 36, 1125, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1080_50_P, "1920x1080@50Hz", XVID_FR_50HZ,
{ XVIDC_VM_1920x1080_50_P, "1920x1080@50Hz", XVIDC_FR_50HZ,
{1920, 528, 44, 148, 2640, 0,
1080, 4, 5, 36, 1125, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1080_60_P, "1920x1080@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1920x1080_60_P, "1920x1080@60Hz", XVIDC_FR_60HZ,
{1920, 88, 44, 148, 2200, 0,
1080, 4, 5, 36, 1125, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1200_60_P_RB, "1920x1200@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_1920x1200_60_P_RB, "1920x1200@60Hz (RB)", XVIDC_FR_60HZ,
{1920, 48, 32, 80, 2080, 1,
1200, 3, 6, 26, 1235, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1200_60_P, "1920x1200@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1920x1200_60_P, "1920x1200@60Hz", XVIDC_FR_60HZ,
{1920, 136, 200, 336, 2592, 0,
1200, 3, 6, 36, 1245, 0, 0, 0, 0, 1} },
{ XVID_VM_1920x1200_75_P, "1920x1200@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1920x1200_75_P, "1920x1200@75Hz", XVIDC_FR_75HZ,
{1920, 136, 208, 344, 2608, 0,
1200, 3, 6, 46, 1255, 0, 0, 0, 0, 1} },
{ XVID_VM_1920x1200_85_P, "1920x1200@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_1920x1200_85_P, "1920x1200@85Hz", XVIDC_FR_85HZ,
{1920, 144, 208, 352, 2624, 0,
1200, 3, 6, 53, 1262, 0, 0, 0, 0, 1} },
{ XVID_VM_1920x1200_120_P_RB, "1920x1200@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1920x1200_120_P_RB, "1920x1200@120Hz (RB)", XVIDC_FR_120HZ,
{1920, 48, 32, 80, 2080, 1,
1200, 3, 6, 62, 1271, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x1440_60_P, "1920x1440@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1920x1440_60_P, "1920x1440@60Hz", XVIDC_FR_60HZ,
{1920, 128, 208, 344, 2600, 0,
1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} },
{ XVID_VM_1920x1440_75_P, "1920x1440@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_1920x1440_75_P, "1920x1440@75Hz", XVIDC_FR_75HZ,
{1920, 144, 224, 352, 2640, 0,
1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} },
{ XVID_VM_1920x1440_120_P_RB, "1920x1440@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_1920x1440_120_P_RB, "1920x1440@120Hz (RB)", XVIDC_FR_120HZ,
{1920, 48, 32, 80, 2080, 1,
1440, 3, 4, 78, 1525, 0, 0, 0, 0, 0} },
{ XVID_VM_1920x2160_60_P, "1920x2160@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_1920x2160_60_P, "1920x2160@60Hz", XVIDC_FR_60HZ,
{1920, 88, 44, 148, 2200, 1,
2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} },
{ XVID_VM_2560x1600_60_P_RB, "2560x1600@60Hz (RB)", XVID_FR_60HZ,
{ XVIDC_VM_2560x1600_60_P_RB, "2560x1600@60Hz (RB)", XVIDC_FR_60HZ,
{2560, 48, 32, 80, 2720, 1,
1600, 3, 6, 37, 1646, 0, 0, 0, 0, 0} },
{ XVID_VM_2560x1600_60_P, "2560x1600@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_2560x1600_60_P, "2560x1600@60Hz", XVIDC_FR_60HZ,
{2560, 192, 280, 472, 3504, 0,
1600, 3, 6, 49, 1658, 0, 0, 0, 0, 1} },
{ XVID_VM_2560x1600_75_P, "2560x1600@75Hz", XVID_FR_75HZ,
{ XVIDC_VM_2560x1600_75_P, "2560x1600@75Hz", XVIDC_FR_75HZ,
{2560, 208, 280, 488, 3536, 0,
1600, 3, 6, 63, 1672, 0, 0, 0, 0, 1} },
{ XVID_VM_2560x1600_85_P, "2560x1600@85Hz", XVID_FR_85HZ,
{ XVIDC_VM_2560x1600_85_P, "2560x1600@85Hz", XVIDC_FR_85HZ,
{2560, 208, 280, 488, 3536, 0,
1600, 3, 6, 73, 1682, 0, 0, 0, 0, 1} },
{ XVID_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVID_FR_120HZ,
{ XVIDC_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVIDC_FR_120HZ,
{2560, 48, 32, 80, 2720, 1,
1600, 3, 6, 85, 1694, 0, 0, 0, 0, 0} },
{ XVID_VM_3840x2160_24_P, "3840x2160@24Hz", XVID_FR_24HZ,
{ XVIDC_VM_3840x2160_24_P, "3840x2160@24Hz", XVIDC_FR_24HZ,
{3840, 1276, 88, 296, 5500, 0,
2160, 8, 10, 72, 2250, 0, 0, 0, 0, 0} },
{ XVID_VM_3840x2160_25_P, "3840x2160@25Hz", XVID_FR_25HZ,
{ XVIDC_VM_3840x2160_25_P, "3840x2160@25Hz", XVIDC_FR_25HZ,
{3840, 1056, 88, 296, 5280, 0,
2160, 8, 10, 72, 2250, 0, 0, 0, 0, 0} },
{ XVID_VM_3840x2160_30_P, "3840x2160@30Hz", XVID_FR_30HZ,
{ XVIDC_VM_3840x2160_30_P, "3840x2160@30Hz", XVIDC_FR_30HZ,
{3840, 176, 88, 296, 4400, 1,
2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} },
{ XVID_VM_3840x2160_60_P, "3840x2160@60Hz", XVID_FR_60HZ,
{ XVIDC_VM_3840x2160_60_P, "3840x2160@60Hz", XVIDC_FR_60HZ,
{3840, 176, 88, 296, 4400, 1,
2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} }
};