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dp: rx: Added register values to override the lane count.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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Andrei-Liviu Simion 2015-01-15 18:13:08 -08:00 • committed by Nava kishore Manne
parent aa7172ded9
commit 36aa085a0e
1 changed files with 5 additions and 0 deletions
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5
XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h
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@ -583,6 +583,11 @@
#define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ #define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
#define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ #define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
#define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ #define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
/* 0x0A0: XDPRX_OVER_LANE_COUNT_SET */
#define XDPRX_OVER_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */
#define XDPRX_OVER_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */
#define XDPRX_OVER_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */
/* @} */ /* @} */
#endif /* XDPRX_HW_H_ */ #endif /* XDPRX_HW_H_ */