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scuwdt_v2_1: Modified the src code according to MISRAC 2012.

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This patch modifies the the code according to MISRAC 2012.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2015-01-06 16:35:19 +05:30 • committed by Suneel Garapati
parent e7aecfb1d9
commit 39f428b47b
6 changed files with 75 additions and 69 deletions
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52
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt.c
View file

@ -81,11 +81,13 @@
* @note This function enables the watchdog mode.
*
******************************************************************************/
int XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
{
s32 CfgStatus;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddress != 0x00U);
/*
* If the device is started, disallow the initialize and return a
@ -94,32 +96,34 @@ int XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
* initializing.
*/
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return XST_DEVICE_IS_STARTED;
CfgStatus = (s32)XST_DEVICE_IS_STARTED;
}
else {
/*
* Copy configuration into instance.
*/
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
/*
* Copy configuration into instance.
*/
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
/*
* Save the base address pointer such that the registers of the block
* can be accessed and indicate it has not been started yet.
*/
InstancePtr->Config.BaseAddr = EffectiveAddress;
InstancePtr->IsStarted = 0U;
/*
* Save the base address pointer such that the registers of the block
* can be accessed and indicate it has not been started yet.
*/
InstancePtr->Config.BaseAddr = EffectiveAddress;
InstancePtr->IsStarted = 0;
/*
* Put the watchdog timer in Watchdog mode.
*/
XScuWdt_SetWdMode(InstancePtr);
/*
* Put the watchdog timer in Watchdog mode.
*/
XScuWdt_SetWdMode(InstancePtr);
/*
* Indicate the instance is ready to use, successfully initialized.
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
/*
* Indicate the instance is ready to use, successfully initialized.
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
CfgStatus =(s32)XST_SUCCESS;
}
return CfgStatus;
}
/****************************************************************************/
@ -195,7 +199,7 @@ void XScuWdt_Stop(XScuWdt *InstancePtr)
/*
* Clear the 'watchdog enable' bit in the register.
*/
Register &= ~XSCUWDT_CONTROL_WD_ENABLE_MASK;
Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
/*
* Update the Control register with the new value.
@ -206,5 +210,5 @@ void XScuWdt_Stop(XScuWdt *InstancePtr)
/*
* Indicate that the device is stopped.
*/
InstancePtr->IsStarted = 0;
InstancePtr->IsStarted = 0U;
}

24
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt.h
View file

@ -178,9 +178,9 @@ typedef struct {
*
******************************************************************************/
#define XScuWdt_IsWdtExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
{((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_RST_STS_OFFSET) & \
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK);}
/****************************************************************************/
/**
@ -199,9 +199,9 @@ typedef struct {
*
******************************************************************************/
#define XScuWdt_IsTimerExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
{((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_ISR_OFFSET) & \
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK);}
/****************************************************************************/
/**
@ -220,7 +220,7 @@ typedef struct {
*
******************************************************************************/
#define XScuWdt_RestartWdt(InstancePtr) \
XScuWdt_LoadWdt(InstancePtr, \
XScuWdt_LoadWdt((InstancePtr), \
(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_LOAD_OFFSET)))
@ -242,7 +242,7 @@ typedef struct {
******************************************************************************/
#define XScuWdt_LoadWdt(InstancePtr, Value) \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_LOAD_OFFSET, Value)
XSCUWDT_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
@ -263,7 +263,7 @@ typedef struct {
XSCUWDT_CONTROL_OFFSET, \
(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET) | \
XSCUWDT_CONTROL_WD_MODE_MASK))
(XSCUWDT_CONTROL_WD_MODE_MASK)))
/****************************************************************************/
/**
@ -326,7 +326,7 @@ typedef struct {
******************************************************************************/
#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET, ControlReg)
XSCUWDT_CONTROL_OFFSET, (ControlReg))
/****************************************************************************/
/**
@ -356,22 +356,18 @@ XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
/*
* Selftest function in xscuwdt_selftest.c
*/
int XScuWdt_SelfTest(XScuWdt *InstancePtr);
s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
/*
* Interface functions in xscuwdt.c
*/
int XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
void XScuWdt_Start(XScuWdt *InstancePtr);
void XScuWdt_Stop(XScuWdt *InstancePtr);
/*
* Self-test function in xwdttb_selftest.c.
*/
int XScuWdt_SelfTest(XScuWdt *InstancePtr);
#ifdef __cplusplus
}

4
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt_g.c
View file

@ -69,7 +69,7 @@
*/
XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] = {
{
XPAR_SCUWDT_0_DEVICE_ID,
XPAR_SCUWDT_0_BASEADDR
(u16)XPAR_SCUWDT_0_DEVICE_ID,
(u32)XPAR_SCUWDT_0_BASEADDR
}
};

36
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt_hw.h
View file

@ -73,12 +73,12 @@ extern "C" {
* @{
*/
#define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */
#define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */
#define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */
#define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */
#define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */
#define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */
#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
/* @} */
/** @name Watchdog Control register
@ -87,14 +87,14 @@ extern "C" {
* @{
*/
#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */
#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8
#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */
#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in
#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
timer mode) */
#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in
#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
timer mode) */
#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */
#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
/* @} */
/** @name Interrupt Status register
@ -103,7 +103,7 @@ extern "C" {
* @{
*/
#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */
#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
/*@}*/
/** @name Reset Status register
@ -112,7 +112,7 @@ extern "C" {
* @{
*/
#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */
#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
/*@}*/
/** @name Disable register
@ -122,9 +122,9 @@ extern "C" {
* Control Register is set to zero.
* @{
*/
#define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable
#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
value 1 */
#define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable
#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
value 2 */
/*@}*/
@ -147,7 +147,7 @@ extern "C" {
*
*****************************************************************************/
#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
Xil_In32((BaseAddr) + ((u32)RegOffset))
/****************************************************************************/
/**
@ -165,7 +165,7 @@ extern "C" {
*
*****************************************************************************/
#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
/************************** Function Prototypes ******************************/

18
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt_selftest.c
View file

@ -78,8 +78,9 @@
* @note None.
*
******************************************************************************/
int XScuWdt_SelfTest(XScuWdt *InstancePtr)
s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
{
s32 SelfTestStatus;
u32 Register;
u32 CtrlOrig;
u32 LoadOrig;
@ -96,18 +97,18 @@ int XScuWdt_SelfTest(XScuWdt *InstancePtr)
*/
CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
XScuWdt_SetControlReg(InstancePtr,
CtrlOrig & ~XSCUWDT_CONTROL_WD_ENABLE_MASK);
CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUWDT_LOAD_OFFSET);
XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFF);
XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
/*
* Start the watchdog timer and check if the watchdog counter is
* decrementing.
*/
XScuWdt_SetControlReg(InstancePtr,
CtrlOrig | XSCUWDT_CONTROL_WD_ENABLE_MASK);
CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUWDT_COUNTER_OFFSET);
@ -115,9 +116,12 @@ int XScuWdt_SelfTest(XScuWdt *InstancePtr)
XScuWdt_LoadWdt(InstancePtr, LoadOrig);
XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
if (Register == 0xFFFFFFFF) {
return XST_FAILURE;
if (Register == 0xFFFFFFFFU) {
SelfTestStatus = (s32)XST_FAILURE;
}
else {
SelfTestStatus = (s32)XST_SUCCESS;
}
return XST_SUCCESS;
return SelfTestStatus;
}

10
XilinxProcessorIPLib/drivers/scuwdt/src/xscuwdt_sinit.c
View file

@ -60,6 +60,9 @@
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
@ -75,16 +78,15 @@
******************************************************************************/
XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
{
extern XScuWdt_Config XScuWdt_ConfigTable[];
XScuWdt_Config *CfgPtr = NULL;
int Index;
u32 Index;
for (Index = 0; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XScuWdt_ConfigTable[Index];
break;
}
}
return (CfgPtr);
return (XScuWdt_Config *)CfgPtr;
}