dptx: Added new v3_0 version and deprecate v2_0.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion
Suneel Garapati
parent
ef064c430d
commit
3d78e1ab5f
23 changed files with 11123 additions and 0 deletions
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xdptx_audio_example.c=xdptx_example_common.h,xdptx_example_common.c
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xdptx_intr_example.c=xdptx_example_common.h,xdptx_example_common.c
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xdptx_mst_example.c=xdptx_example_common.h,xdptx_example_common.c
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xdptx_poll_example.c=xdptx_example_common.h,xdptx_example_common.c
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xdptx_selftest_example.c=xdptx_example_common.h,xdptx_example_common.c
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xdptx_timer_example.c=xdptx_example_common.h,xdptx_example_common.c
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41
XilinxProcessorIPLib/drivers/dptx/data/dptx.mdd
Normal file
41
XilinxProcessorIPLib/drivers/dptx/data/dptx.mdd
Normal file
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##******************************************************************************
|
||||
##
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## Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
##
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## Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
## of this software and associated documentation files (the "Software"), to deal
|
||||
## in the Software without restriction, including without limitation the rights
|
||||
## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
## copies of the Software, and to permit persons to whom the Software is
|
||||
## furnished to do so, subject to the following conditions:
|
||||
##
|
||||
## The above copyright notice and this permission notice shall be included in
|
||||
## all copies or substantial portions of the Software.
|
||||
##
|
||||
## Use of the Software is limited solely to applications:
|
||||
## (a) running on a Xilinx device, or
|
||||
## (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
##
|
||||
## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
## XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
## WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
## OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
## SOFTWARE.
|
||||
##
|
||||
## Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
## in advertising or otherwise to promote the sale, use or other dealings in
|
||||
## this Software without prior written authorization from Xilinx.
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##
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##*****************************************************************************/
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OPTION psf_version = 2.1;
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BEGIN driver dptx
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OPTION supported_peripherals = (displayport);
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OPTION driver_state = ACTIVE;
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OPTION copyfiles = all;
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OPTION VERSION = 3.0;
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OPTION NAME = dptx;
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END driver
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186
XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl
Normal file
186
XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl
Normal file
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@ -0,0 +1,186 @@
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##******************************************************************************
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##
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## Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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||||
##
|
||||
## Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
## of this software and associated documentation files (the "Software"), to deal
|
||||
## in the Software without restriction, including without limitation the rights
|
||||
## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
## copies of the Software, and to permit persons to whom the Software is
|
||||
## furnished to do so, subject to the following conditions:
|
||||
##
|
||||
## The above copyright notice and this permission notice shall be included in
|
||||
## all copies or substantial portions of the Software.
|
||||
##
|
||||
## Use of the Software is limited solely to applications:
|
||||
## (a) running on a Xilinx device, or
|
||||
## (b) that interact with a Xilinx device through a bus or interconnect.
|
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##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
## XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
## WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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## OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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## SOFTWARE.
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##
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## Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
## in advertising or otherwise to promote the sale, use or other dealings in
|
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## this Software without prior written authorization from Xilinx.
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##
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##*****************************************************************************/
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
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xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
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}
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#
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# Given a list of arguments, define them all in an include file.
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# Handles IP model/user parameters, as well as the special parameters NUM_INSTANCES,
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# DEVICE_ID
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# Will not work for a processor.
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#
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proc xdefine_include_file {drv_handle file_name drv_string args} {
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set args [get_exact_arg_list $args]
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# Open include file
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set file_handle [xopen_include_file $file_name]
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# Get all peripherals connected to this driver
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set periphs [xget_sw_iplist_for_driver $drv_handle]
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# Handle special cases
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set arg "NUM_INSTANCES"
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set posn [lsearch -exact $args $arg]
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if {$posn > -1} {
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puts $file_handle "/* Definitions for driver [string toupper [get_property name $drv_handle]] */"
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# Define NUM_INSTANCES
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puts $file_handle "#define [xget_dname $drv_string $arg] [llength $periphs]"
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set args [lreplace $args $posn $posn]
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}
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# Check if it is a driver parameter
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lappend newargs
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foreach arg $args {
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set value [get_property CONFIG.$arg $drv_handle]
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if {[llength $value] == 0} {
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lappend newargs $arg
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} else {
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puts $file_handle "#define [xget_dname $drv_string $arg] [get_property $arg $drv_handle]"
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}
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}
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set args $newargs
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# Print all parameters for all peripherals
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set device_id 0
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foreach periph $periphs {
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puts $file_handle ""
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puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
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foreach arg $args {
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if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
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set value $device_id
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incr device_id
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} elseif {[string compare -nocase "S_AXI_ACLK" $arg] == 0} {
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set freq [xget_ip_clk_pin_freq $periph $arg]
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if {[llength $freq] == 0} {
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set freq 0
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puts "WARNING: Clock frequency information is not available in the design, \
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for peripheral $periph_name. This will not work."
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}
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set value $freq
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} else {
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set value [get_property CONFIG.$arg $periph]
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}
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if {[llength $value] == 0} {
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set value 0
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}
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set value [xformat_addr_string $value $arg]
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if {[string compare -nocase "HW_VER" $arg] == 0} {
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puts $file_handle "#define [xget_name $periph $arg] \"$value\""
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} else {
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puts $file_handle "#define [xget_name $periph $arg] $value"
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}
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}
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puts $file_handle ""
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}
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puts $file_handle "\n/******************************************************************/\n"
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close $file_handle
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}
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#
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# xdefine_canonical_xpars - Used to print out canonical defines for a driver.
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# Given a list of arguments, define each as a canonical constant name, using
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# the driver name, in an include file.
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#
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proc xdefine_canonical_xpars {drv_handle file_name drv_string args} {
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set args [get_exact_arg_list $args]
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# Open include file
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set file_handle [xopen_include_file $file_name]
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# Get all the peripherals connected to this driver
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set periphs [xget_sw_iplist_for_driver $drv_handle]
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# Get the names of all the peripherals connected to this driver
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foreach periph $periphs {
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set peripheral_name [string toupper [get_property NAME $periph]]
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lappend peripherals $peripheral_name
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}
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# Get possible canonical names for all the peripherals connected to this
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# driver
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set device_id 0
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foreach periph $periphs {
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set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]]
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lappend canonicals $canonical_name
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# Create a list of IDs of the peripherals whose hardware instance name
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# doesn't match the canonical name. These IDs can be used later to
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# generate canonical definitions
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if { [lsearch $peripherals $canonical_name] < 0 } {
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lappend indices $device_id
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}
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incr device_id
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}
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set i 0
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foreach periph $periphs {
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set periph_name [string toupper [get_property NAME $periph]]
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# Generate canonical definitions only for the peripherals whose
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# canonical name is not the same as hardware instance name
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if { [lsearch $canonicals $periph_name] < 0 } {
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puts $file_handle "/* Canonical definitions for peripheral $periph_name */"
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set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]]
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foreach arg $args {
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set lvalue [xget_dname $canonical_name $arg]
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# The commented out rvalue is the name of the instance-specific constant
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# set rvalue [xget_name $periph $arg]
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# The rvalue set below is the actual value of the parameter
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if {[string compare -nocase "S_AXI_ACLK" $arg] == 0} {
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set freq [xget_ip_clk_pin_freq $periph $arg]
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if {[llength $freq] == 0} {
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set freq 0
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puts "WARNING: Clock frequency information is not available in the design, \
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for peripheral $periph_name. This will not work."
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}
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set rvalue $freq
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} else {
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set rvalue [xget_param_value $periph $arg]
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if {[llength $rvalue] == 0} {
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set rvalue 0
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}
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set rvalue [xformat_addr_string $rvalue $arg]
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}
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puts $file_handle "#define $lvalue $rvalue"
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}
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puts $file_handle ""
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incr i
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}
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}
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puts $file_handle "\n/******************************************************************/\n"
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close $file_handle
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}
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22
XilinxProcessorIPLib/drivers/dptx/examples/index.html
Executable file
22
XilinxProcessorIPLib/drivers/dptx/examples/index.html
Executable file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
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<html>
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<head>
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<meta http-equiv="Content-Language" content="en-us">
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<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
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<title>Driver example applications</title>
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<link rel="stylesheet" type="text/css" href="../help.css">
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</head>
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<body bgcolor="#FFFFFF">
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<h1> Example applications for the dptx_v2_0 driver. </h1>
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<HR>
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<ul>
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<li>xdptx_audio_example.c <a href="xdptx_audio_example.c">(source)</a> </li>
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<li>xdptx_intr_example.c <a href="xdptx_intr_example.c">(source)</a> </li>
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<li>xdptx_mst_example.c <a href="xdptx_mst_example.c">(source)</a> </li>
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<li>xdptx_poll_example.c <a href="xdptx_poll_example.c">(source)</a> </li>
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<li>xdptx_selftest_example.c <a href="xdptx_selftest_example.c">(source)</a> </li>
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<li>xdptx_timer_example.c <a href="xdptx_timer_example.c">(source)</a> </li>
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</ul>
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<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
|
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</body>
|
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</html>
|
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62
XilinxProcessorIPLib/drivers/dptx/examples/readme.txt
Normal file
62
XilinxProcessorIPLib/drivers/dptx/examples/readme.txt
Normal file
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@ -0,0 +1,62 @@
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There are 6 examples included in this directory:
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1) xdptx_audio_example.c : This audio example, apart from training the main link
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and outputting video, illustrates the sequence required for setting up audio
|
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in the DisplayPort TX. This example requires that an audio source, such as a
|
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S/PDIF instance be present and connected to the DisplayPort TX in the
|
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hardware system, and for the audio enable configuration parameter to be set
|
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for the instantiated DisplayPort TX. For audio to output, the user will need
|
||||
to implement the following functions:
|
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a) Dptx_ConfigureAudioSrc : This function needs to configure the audio source
|
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to output to the DisplayPort TX.
|
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b) Dptx_AudioSendInfoFrame : This function needs to set up and write an audio
|
||||
info frame as per user requirements.
|
||||
|
||||
2) xdptx_intr_example.c : This interrupt example shows how to set up the
|
||||
interrupt system and specify the interrupt handlers for when a DisplayPort
|
||||
interrupt event occurs. An interrupt controller with a connection to the
|
||||
DisplayPort interrupt signal needs to exist in the hardware system.
|
||||
|
||||
3) xdptx_mst_example.c : This multi-stream transport (MST) example shows how to
|
||||
use the driver's MST capabilities. Streams can be directed at sinks using two
|
||||
methods:
|
||||
a) After topology discover has created a sink list, streams may be assigned
|
||||
to sinks using the index in the sink list.
|
||||
b) The streams may be assigned to sinks directly without using topology
|
||||
discovery if their relative addresses (and total number of DisplayPort
|
||||
links) from the DisplayPort source is known beforehand.
|
||||
|
||||
4) xdptx_poll_example.c : This interrupt example shows how to poll the
|
||||
DisplayPort TX instance's registers for DisplayPort interrupt events.
|
||||
|
||||
5) xdptx_timer_example.c : This timer example shows how to override the default
|
||||
sleep/delay functionality for MicroBlaze. A timer needs to exist in the
|
||||
hardware system and will be used for sleep/delay functionality inside of a
|
||||
callback function. The default behavior in MicroBlaze for sleep/delay is to
|
||||
call MB_Sleep from microblaze_sleep.h, which has only millisecond accuracy.
|
||||
For ARM/Zynq SoC systems, the supplied callback function will be ignored -
|
||||
the usleep function will be called since the SoC has a timer built-in.
|
||||
|
||||
6) xdptx_selftest_example.c : This self test example will perform a sanity check
|
||||
on the state of the DisplayPort TX instance. It may be called prior to usage
|
||||
of the core or after a reset to ensure that (a subset of) the registers hold
|
||||
their default values.
|
||||
|
||||
Each of these examples are meant to be used in conjunction with
|
||||
xdptx_example_common.[ch] which holds common functionality for all examples.
|
||||
After importing the examples, these files will need to be manually copied into
|
||||
the example src/ directory.
|
||||
This code shows how to train the main link and set up a video stream.
|
||||
|
||||
Additionally, in order to be able to use the interrupt, polling, and timer
|
||||
examples, the user will need to implement and link the following functions:
|
||||
1) Dptx_InitPlatform : This function needs to do all hardware system
|
||||
initialization.
|
||||
2) Dptx_StreamSrc* : These function need to configure the source of the stream
|
||||
(pattern generators, video input, etc.) such that a video stream, with
|
||||
timings and video attributes that correspond to the main stream attributes
|
||||
(MSA) configuration, is received by the DisplayPort Tx. The examples call
|
||||
this function from the Dptx_Run->Dptx_StartVideoStream functions in
|
||||
xdptx_example_common.c.
|
||||
|
||||
Note: All example functions start with Dptx_*, while all driver functions start
|
||||
with XDptx_*.
|
||||
268
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
Normal file
268
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_audio_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver to train the main link and
|
||||
* to display video. In this example application, the sequence to enable audio
|
||||
* is illustrated.
|
||||
*
|
||||
* @note This example requires an audio source such as an S/PDIF instance
|
||||
* to be part of the hardware system. See XAPP1178 for reference.
|
||||
* @note This example requires that the audio enable configuration
|
||||
* parameter for DisplayPort be turned on when creating the
|
||||
* hardware design.
|
||||
* @note For this example to output audio, the user will need to
|
||||
* implement initialization of the system (Dptx_PlatformInit),
|
||||
* configuration of the audio source (Dptx_ConfigureAudioSrc) and,
|
||||
* depending on the hardware system, will need to implement sending
|
||||
* of an info frame (Dptx_AudioSendInfoFrame). See XAPP1178 and the
|
||||
* IP documentation for reference.
|
||||
* @note For this example to display output, after training is complete,
|
||||
* the user will need to implement configuration of the video
|
||||
* stream source in order to provide the DisplayPort core with
|
||||
* input (Dptx_StreamSrc* - called in xdptx_example_common.c). See
|
||||
* XAPP1178 for reference.
|
||||
* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
|
||||
* extern in xdptx_example_common.h and are left up to the user to
|
||||
* implement. The functions Dptx_ConfigureAudioSrc and
|
||||
* Dptx_AudioSendInfoFrame are present in this file and are also
|
||||
* left for the user to implement.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 07/29/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId);
|
||||
static void Dptx_AudioInit(XDptx *InstancePtr);
|
||||
static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr);
|
||||
static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx audio example.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the audio example finished successfully.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Run the XDptx audio example. */
|
||||
Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the audio example using the XDptx driver. This
|
||||
* function will set up audio, initiate link training, and a video stream will
|
||||
* start being sent over the main link.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the system was set up correctly and link
|
||||
* training was successful.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Use single-stream transport (SST) mode for this example. Audio is
|
||||
* not supported in multi-stream transport (MST) mode. */
|
||||
XDptx_MstCfgModeDisable(InstancePtr);
|
||||
|
||||
/* Do platform initialization here. This is hardware system specific -
|
||||
* it is up to the user to implement this function. */
|
||||
Dptx_PlatformInit();
|
||||
/*******************/
|
||||
|
||||
Status = Dptx_SetupExample(InstancePtr, DeviceId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Initialize DisplayPort audio. */
|
||||
Dptx_AudioInit(InstancePtr);
|
||||
|
||||
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
|
||||
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
|
||||
|
||||
/* A sink monitor must be connected at this point. See the polling or
|
||||
* interrupt examples for how to wait for a connection event. */
|
||||
Status = Dptx_Run(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function will set up audio in the DisplayPort TX. The user will need
|
||||
* to implement configuration of the audio stream and, if needed, sending of
|
||||
* the info frame.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The user needs to implement the Dptx_ConfigureAudioSrc and
|
||||
* the Dptx_AudioSendInfoFrame functions to fulfill audio
|
||||
* initialization.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_AudioInit(XDptx *InstancePtr)
|
||||
{
|
||||
u32 Fs;
|
||||
u32 MAud;
|
||||
u32 NAud;
|
||||
u32 NumChs;
|
||||
|
||||
/* Disable audio in the DisplayPort TX. This will also flush the buffers
|
||||
* in the DisplayPort TX and set MUTE bit in VB-ID. */
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
|
||||
0x0);
|
||||
|
||||
/* Configure the audio source (the S/PDIF controller). It is up to the
|
||||
* user to implement this function. */
|
||||
Dptx_ConfigureAudioSrc(InstancePtr);
|
||||
/*******************/
|
||||
|
||||
/* Write audio info frame as per user requirements. This may be optional
|
||||
* for some systems. 8 writes are required to register
|
||||
* XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this
|
||||
* function. */
|
||||
Dptx_AudioSendInfoFrame(InstancePtr);
|
||||
/*******************/
|
||||
|
||||
Fs = 48; /* KHz (32 | 44.1 | 48) */
|
||||
if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) {
|
||||
MAud = 512 * Fs;
|
||||
}
|
||||
else if (InstancePtr->LinkConfig.LinkRate ==
|
||||
XDPTX_LINK_BW_SET_270GBPS) {
|
||||
MAud = 512 * Fs;
|
||||
}
|
||||
else if (InstancePtr->LinkConfig.LinkRate ==
|
||||
XDPTX_LINK_BW_SET_162GBPS) {
|
||||
MAud = 512 * Fs;
|
||||
}
|
||||
|
||||
/* Write the channel count. The value is (actual count - 1). */
|
||||
NumChs = 2;
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS,
|
||||
NumChs - 1);
|
||||
|
||||
/* NAud = 540000 | 270000 | 162000 */
|
||||
NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000;
|
||||
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud);
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud);
|
||||
|
||||
/* Enable audio in the DisplayPort TX. */
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
|
||||
0x1);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function needs to configure the audio source.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The user needs to implement this. See XAPP1178 and the IP
|
||||
* documentation for reference.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr)
|
||||
{
|
||||
xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n");
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function needs to send an info frame as per user requirements.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The user needs to implement this. See XAPP1178 and the IP
|
||||
* documentation for reference.
|
||||
* @note This may be optional for some systems.
|
||||
* @note A sequence of 8 writes are required to register
|
||||
* XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation
|
||||
* for reference.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr)
|
||||
{
|
||||
xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,347 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_example_common.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver. It performs a self test on
|
||||
* the DisplayPort TX core by training the main link at the maximum common
|
||||
* capabilities between the TX and RX and checking the lane status.
|
||||
*
|
||||
* @note The DisplayPort TX core does not work alone - video/audio
|
||||
* sources need to be set up in the system correctly, as well as
|
||||
* setting up the output path (for example, configuring the
|
||||
* hardware system with the DisplayPort TX core output to an FMC
|
||||
* card with DisplayPort output capabilities. Some platform
|
||||
* initialization will need to happen prior to calling XDptx driver
|
||||
* functions. See XAPP1178 as a reference.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
static void Dptx_StartVideoStream(XDptx *InstancePtr);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function will configure and establish a link with the receiver device,
|
||||
* afterwards, a video stream will start to be sent over the main link.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param LaneCount is the number of lanes to use over the main link.
|
||||
* @param LinkRate is the link rate to use over the main link.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if main link was successfully established.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_Run(XDptx *InstancePtr)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Configure and establish a link. */
|
||||
Status = Dptx_StartLink(InstancePtr);
|
||||
if (Status == XST_SUCCESS) {
|
||||
/* Start the video stream. */
|
||||
Dptx_StartVideoStream(InstancePtr);
|
||||
} else {
|
||||
xil_printf("<-- Failed to establish/train the link.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function will setup and initialize the DisplayPort TX core. The core's
|
||||
* configuration parameters will be retrieved based on the configuration
|
||||
* to the DisplayPort TX core instance with the specified device ID.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the device configuration was found and obtained
|
||||
* and if the main link was successfully established.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
XDptx_Config *ConfigPtr;
|
||||
u32 Status;
|
||||
|
||||
/* Obtain the device configuration for the DisplayPort TX core. */
|
||||
ConfigPtr = XDptx_LookupConfig(DeviceId);
|
||||
if (!ConfigPtr) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
/* Copy the device configuration into the InstancePtr's Config
|
||||
* structure. */
|
||||
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
|
||||
|
||||
/* Initialize the DisplayPort TX core. */
|
||||
Status = XDptx_InitializeTx(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function will configure and establish a link with the receiver device.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS the if main link was successfully established.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_StartLink(XDptx *InstancePtr)
|
||||
{
|
||||
u32 VsLevelTx;
|
||||
u32 PeLevelTx;
|
||||
u32 Status;
|
||||
u8 LaneCount;
|
||||
u8 LinkRate;
|
||||
|
||||
/* Obtain the capabilities of the RX device by reading the monitor's
|
||||
* DPCD. */
|
||||
Status = XDptx_GetRxCapabilities(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
#if (TRAIN_USE_MAX_LINK == 1)
|
||||
LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
|
||||
LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
|
||||
#else
|
||||
LaneCount = TRAIN_USE_LANE_COUNT;
|
||||
LinkRate = TRAIN_USE_LINK_RATE;
|
||||
#endif
|
||||
|
||||
/* Check if the link is already trained */
|
||||
Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
|
||||
if (Status == XST_SUCCESS) {
|
||||
xil_printf("-> Link is already trained on %d lanes.\n",
|
||||
LaneCount);
|
||||
if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_LINK_BW_SET) == LinkRate) {
|
||||
xil_printf("-> Link needs to be re-trained %d Mbps.\n",
|
||||
(270 * LinkRate));
|
||||
}
|
||||
else {
|
||||
xil_printf("-> Link is already trained at %d Mbps.\n",
|
||||
(270 * LinkRate));
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
}
|
||||
else if (Status == XST_FAILURE) {
|
||||
xil_printf("-> Needs training.\n");
|
||||
}
|
||||
else {
|
||||
/* Either a connection does not exist or the supplied lane count
|
||||
* is invalid. */
|
||||
xil_printf("-> Error checking link status.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XDptx_SetEnhancedFrameMode(InstancePtr, 1);
|
||||
XDptx_SetDownspread(InstancePtr, 0);
|
||||
|
||||
#if (TRAIN_USE_MAX_LINK == 1)
|
||||
/* Configure the main link based on the maximum common capabilities of
|
||||
* the DisplayPort TX core and the receiver device. */
|
||||
Status = XDptx_CfgMainLinkMax(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
#else
|
||||
XDptx_SetLinkRate(InstancePtr, LinkRate);
|
||||
XDptx_SetLaneCount(InstancePtr, LaneCount);
|
||||
#endif
|
||||
|
||||
/* Train the link. */
|
||||
xil_printf("******************************************\n");
|
||||
Status = XDptx_EstablishLink(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("!!! Training failed !!!\n");
|
||||
xil_printf("******************************************\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
|
||||
PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_PHY_POSTCURSOR_LANE_0);
|
||||
xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
|
||||
InstancePtr->LinkConfig.LinkRate,
|
||||
InstancePtr->LinkConfig.LaneCount);
|
||||
xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
|
||||
InstancePtr->LinkConfig.VsLevel, VsLevelTx,
|
||||
InstancePtr->LinkConfig.PeLevel, PeLevelTx);
|
||||
xil_printf("******************************************\n");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function will start sending a video stream over the main link. The
|
||||
* settings to be used are as follows:
|
||||
* - 8 bits per color.
|
||||
* - Video timing and screen resolution used:
|
||||
* - The connected monitor's preferred timing is used to determine the
|
||||
* video resolution (and associated timings) for the stream.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The Dptx_StreamSrc* are intentionally left for the user to
|
||||
* implement since configuration of the stream source is
|
||||
* application-specific.
|
||||
* @note The Extended Display Identification Data (EDID) is read in order
|
||||
* to obtain the video resolution and timings. If this read fails,
|
||||
* a resolution of 640x480 is used at a refresh rate of 60Hz.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_StartVideoStream(XDptx *InstancePtr)
|
||||
{
|
||||
u32 Status;
|
||||
u8 Edid[XDPTX_EDID_SIZE];
|
||||
|
||||
/* Set the bits per color. If not set, the default is 6. */
|
||||
XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0, 8);
|
||||
|
||||
/* Set synchronous clock mode. */
|
||||
XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID0, 1);
|
||||
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
|
||||
|
||||
/* Choose a method for selecting the video mode. There are 3 ways to do this:
|
||||
* 1) Use the preferred timing from the monitor's EDID:
|
||||
* u8 Edid[XDPTX_EDID_SIZE];
|
||||
* XDptx_GetEdid(InstancePtr, Edid);
|
||||
* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID0, Edid);
|
||||
*
|
||||
* 2) Use a standard video timing mode (see mode_table.h):
|
||||
* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0,
|
||||
XDPTX_VM_640x480_60_P);
|
||||
*
|
||||
* 3) Use a custom configuration for the main stream attributes (MSA):
|
||||
* XDptx_MainStreamAttributes MsaConfigCustom;
|
||||
* MsaConfigCustom.Dmt.HResolution = 1280;
|
||||
* MsaConfigCustom.Dmt.VResolution = 1024;
|
||||
* MsaConfigCustom.Dmt.PixelClkKhz = 108000;
|
||||
* MsaConfigCustom.Dmt.HSyncPolarity = 0;
|
||||
* MsaConfigCustom.Dmt.VSyncPolarity = 0;
|
||||
* MsaConfigCustom.Dmt.HFrontPorch = 48;
|
||||
* MsaConfigCustom.Dmt.HSyncPulseWidth = 112;
|
||||
* MsaConfigCustom.Dmt.HBackPorch = 248;
|
||||
* MsaConfigCustom.Dmt.VFrontPorch = 1;
|
||||
* MsaConfigCustom.Dmt.VSyncPulseWidth = 3;
|
||||
* MsaConfigCustom.Dmt.VBackPorch = 38;
|
||||
* XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID0,
|
||||
* &MsaConfigCustom, 1);
|
||||
*
|
||||
* To override the user pixel width:
|
||||
* InstancePtr->MsaConfig[_STREAM#_].OverrideUserPixelWidth = 1;
|
||||
* InstancePtr->MsaConfig[_STREAM#_].UserPixelWidth = _DESIRED_VALUE_;
|
||||
* Then, use one of the methods above to calculate the rest of the MSA.
|
||||
*/
|
||||
Status = XDptx_GetEdid(InstancePtr, Edid);
|
||||
if (Status == XST_SUCCESS) {
|
||||
XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr,
|
||||
XDPTX_STREAM_ID0, Edid);
|
||||
}
|
||||
else {
|
||||
XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0,
|
||||
XDPTX_VM_640x480_60_P);
|
||||
}
|
||||
|
||||
/* Disable MST for this example. */
|
||||
XDptx_MstDisable(InstancePtr);
|
||||
|
||||
/* Disable main stream to force sending of IDLE patterns. */
|
||||
XDptx_DisableMainLink(InstancePtr);
|
||||
|
||||
/* Reset the transmitter. */
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
|
||||
XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
|
||||
|
||||
/* Set the DisplayPort TX video mode. */
|
||||
XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0);
|
||||
|
||||
/* Configure video stream source or generator here. These function need
|
||||
* to be implemented in order for video to be displayed and is hardware
|
||||
* system specific. It is up to the user to implement these
|
||||
* functions. */
|
||||
Dptx_StreamSrcSetup(InstancePtr);
|
||||
Dptx_StreamSrcConfigure(InstancePtr);
|
||||
Dptx_StreamSrcSync(InstancePtr);
|
||||
/*********************************/
|
||||
|
||||
XDptx_EnableMainLink(InstancePtr);
|
||||
}
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_example_common.h
|
||||
*
|
||||
* Contains a design example using the XDptx driver. It performs a self test on
|
||||
* the DisplayPort TX core by training the main link at the maximum common
|
||||
* capabilities between the TX and RX and checking the lane status.
|
||||
*
|
||||
* @note The DisplayPort TX core does not work alone - video/audio
|
||||
* sources need to be set up in the system correctly, as well as
|
||||
* setting up the output path (for example, configuring the
|
||||
* hardware system with the DisplayPort TX core output to an FMC
|
||||
* card with DisplayPort output capabilities. Some platform
|
||||
* initialization will need to happen prior to calling XDptx driver
|
||||
* functions. See XAPP1178 as a reference.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef XDPTX_EXAMPLE_COMMON_H_
|
||||
/* Prevent circular inclusions by using protection macros. */
|
||||
#define XDPTX_EXAMPLE_COMMON_H_
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx.h"
|
||||
#include "xil_printf.h"
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/**************************** Constant Definitions ****************************/
|
||||
|
||||
/* The unique device ID of the DisplayPort TX core instance to be used with the
|
||||
* examples. */
|
||||
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
|
||||
|
||||
/* If set to 1, the link training process will continue training despite failing
|
||||
* by attempting training at a reduced link rate. It will also continue
|
||||
* attempting to train the link at a reduced lane count if needed. With this
|
||||
* option enabled, link training will return failure only when all link rate and
|
||||
* lane count combinations have been exhausted - that is, training fails using
|
||||
* 1-lane and a 1.62Gbps link rate.
|
||||
* If set to 0, link training will return failure if the training failed using
|
||||
* the current lane count and link rate settings.
|
||||
* TRAIN_ADAPTIVE is used by the examples as input to the
|
||||
* XDptx_EnableTrainAdaptive driver function. */
|
||||
#define TRAIN_ADAPTIVE 1
|
||||
|
||||
/* A value of 1 is used to indicate that the DisplayPort output path has a
|
||||
* redriver on the board that adjusts the voltage swing and pre-emphasis levels
|
||||
* that are outputted from the FPGA. If this is the case, the voltage swing and
|
||||
* pre-emphasis values supplied to the DisplayPort TX core will be evenly
|
||||
* distributed among the available levels as specified in the IP documentation.
|
||||
* Otherwise, a value of 0 is used to indicate that no redriver is present. In
|
||||
* order to meet the necessary voltage swing and pre-emphasis levels required by
|
||||
* a DisplayPort RX device, the level values specified to the DisplayPort TX
|
||||
* core will require some compensation.
|
||||
* TRAIN_HAS_REDRIVER is used by the examples as input to the
|
||||
* XDptx_SetHasRedriverInPath driver function.
|
||||
* Note: There are 16 possible voltage swing levels and 32 possible pre-emphasis
|
||||
* levels in the DisplayPort TX core that will be mapped to 4 possible
|
||||
* voltage swing and 4 possible pre-emphasis levels in the RX device. */
|
||||
#define TRAIN_HAS_REDRIVER 1
|
||||
|
||||
/* The link rate setting to begin link training with. Valid values are:
|
||||
* XDPTX_LINK_BW_SET_540GBPS, XDPTX_LINK_BW_SET_270GBPS, and
|
||||
* XDPTX_LINK_BW_SET_162GBPS. */
|
||||
#define TRAIN_USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS
|
||||
/* The lane count setting to begin link training with. Valid values are:
|
||||
* XDPTX_LANE_COUNT_SET_4, XDPTX_LANE_COUNT_SET_2, and
|
||||
* XDPTX_LANE_COUNT_SET_1. */
|
||||
#define TRAIN_USE_LANE_COUNT XDPTX_LANE_COUNT_SET_4
|
||||
/* If set to 1, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will be ignored.
|
||||
* Instead, the maximum common link capabilities between the DisplayPort TX core
|
||||
* and the RX device will be used when establishing a link.
|
||||
* If set to 0, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will determine the
|
||||
* link rate and lane count settings that the link training process will begin
|
||||
* with. */
|
||||
#define TRAIN_USE_MAX_LINK 1
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
extern u32 Dptx_PlatformInit(void);
|
||||
extern u32 Dptx_StreamSrcSync(XDptx *InstancePtr);
|
||||
extern u32 Dptx_StreamSrcSetup(XDptx *InstancePtr);
|
||||
extern u32 Dptx_StreamSrcConfigure(XDptx *InstancePtr);
|
||||
|
||||
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId);
|
||||
u32 Dptx_StartLink(XDptx *InstancePtr);
|
||||
u32 Dptx_Run(XDptx *InstancePtr);
|
||||
|
||||
/*************************** Variable Declarations ****************************/
|
||||
|
||||
XDptx DptxInstance;
|
||||
|
||||
#endif /* XDPTX_EXAMPLE_COMMON_H_ */
|
||||
351
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
Normal file
351
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_intr_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver with interrupts. Upon Hot-
|
||||
* Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is
|
||||
* turned on/off), the main link will be trained.
|
||||
*
|
||||
* @note This example requires an interrupt controller connected to the
|
||||
* processor and the DisplayPort TX core in the system.
|
||||
* @note For this example to display output, the user will need to
|
||||
* implement initialization of the system (Dptx_PlatformInit) and,
|
||||
* after training is complete, implement configuration of the video
|
||||
* stream source in order to provide the DisplayPort core with
|
||||
* input (Dptx_StreamSrc* - called in xdptx_example_common.c). See
|
||||
* XAPP1178 for reference.
|
||||
* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
|
||||
* extern in xdptx_example_common.h and are left up to the user to
|
||||
* implement.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
/* For MicroBlaze systems. */
|
||||
#include "xintc.h"
|
||||
#else
|
||||
/* For ARM/Zynq SoC systems. */
|
||||
#include "xscugic.h"
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
|
||||
/**************************** Constant Definitions ****************************/
|
||||
|
||||
/* The following constants map to the XPAR parameters created in the
|
||||
* xparameters.h file. */
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
|
||||
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
|
||||
#else
|
||||
#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
|
||||
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
|
||||
/****************************** Type Definitions ******************************/
|
||||
|
||||
/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system,
|
||||
* different drivers and associated types will be used. */
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
#define INTC XIntc
|
||||
#define INTC_HANDLER XIntc_InterruptHandler
|
||||
#else
|
||||
#define INTC XScuGic
|
||||
#define INTC_HANDLER XScuGic_InterruptHandler
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
|
||||
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
|
||||
XDptx_HpdPulseHandler HpdPulseHandler);
|
||||
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
|
||||
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
|
||||
XDptx_HpdPulseHandler HpdPulseHandler);
|
||||
static void Dptx_HpdEventHandler(void *InstancePtr);
|
||||
static void Dptx_HpdPulseHandler(void *InstancePtr);
|
||||
|
||||
/**************************** Variable Definitions ****************************/
|
||||
|
||||
INTC IntcInstance; /* The interrupt controller instance. */
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx interrupt example. If the
|
||||
* DptxIntrExample function, which sets up the system succeeds, this function
|
||||
* will wait for interrupts. Once a connection event or pulse is detected, link
|
||||
* training will commence (if needed) and a video stream will start being sent
|
||||
* over the main link.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the interrupt example was unsuccessful - system
|
||||
* setup failed.
|
||||
*
|
||||
* @note Unless setup failed, main will never return since
|
||||
* DptxIntrExample is blocking (it is waiting on interrupts for
|
||||
* Hot-Plug-Detect (HPD) events.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* Run the XDptx interrupt example. */
|
||||
Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
|
||||
&IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
|
||||
&Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
|
||||
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the interrupt example using the XDptx driver. This
|
||||
* function will set up the system with interrupts and set up the Hot-Plug-Event
|
||||
* (HPD) handlers.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
* @param IntcPtr is a pointer to the interrupt instance.
|
||||
* @param IntrId is the unique device ID of the interrupt controller.
|
||||
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
|
||||
* the interrupt controller.
|
||||
* @param HpdEventHandler is a pointer to the handler called when an HPD
|
||||
* event occurs.
|
||||
* @param HpdPulseHandler is a pointer to the handler called when an HPD
|
||||
* pulse occurs.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the system setup failed.
|
||||
* - XST_SUCCESS should never return since this function, if setup
|
||||
* was successful, is blocking.
|
||||
*
|
||||
* @note If system setup was successful, this function is blocking in
|
||||
* order to illustrate interrupt handling taking place for HPD
|
||||
* events.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
|
||||
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
|
||||
XDptx_HpdPulseHandler HpdPulseHandler)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Use single-stream transport (SST) mode for this example. */
|
||||
XDptx_MstCfgModeDisable(InstancePtr);
|
||||
|
||||
/* Do platform initialization here. This is hardware system specific -
|
||||
* it is up to the user to implement this function. */
|
||||
Dptx_PlatformInit();
|
||||
/******************/
|
||||
|
||||
Status = Dptx_SetupExample(InstancePtr, DeviceId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
|
||||
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
|
||||
|
||||
/* Setup interrupt handling in the system. */
|
||||
Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
|
||||
DpIntrId, HpdEventHandler, HpdPulseHandler);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Do not return in order to allow interrupt handling to run. HPD events
|
||||
* (connect, disconnect, and pulse) will be detected and handled. */
|
||||
while (1);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function sets up the interrupt system such that interrupts caused by
|
||||
* Hot-Plug-Detect (HPD) events and pulses are handled. This function is
|
||||
* application-specific for systems that have an interrupt controller connected
|
||||
* to the processor. The user should modify this function to fit the
|
||||
* application.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param IntcPtr is a pointer to the interrupt instance.
|
||||
* @param IntrId is the unique device ID of the interrupt controller.
|
||||
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
|
||||
* the interrupt controller.
|
||||
* @param HpdEventHandler is a pointer to the handler called when an HPD
|
||||
* event occurs.
|
||||
* @param HpdPulseHandler is a pointer to the handler called when an HPD
|
||||
* pulse occurs.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the interrupt system was successfully set up.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note An interrupt controller must be present in the system, connected
|
||||
* to the processor and the DisplayPort TX core.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
|
||||
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
|
||||
XDptx_HpdPulseHandler HpdPulseHandler)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Set the HPD interrupt handlers. */
|
||||
XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
|
||||
XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
|
||||
|
||||
/* Initialize interrupt controller driver. */
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
Status = XIntc_Initialize(IntcPtr, IntrId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
#else
|
||||
XScuGic_Config *IntcConfig;
|
||||
|
||||
IntcConfig = XScuGic_LookupConfig(IntrId);
|
||||
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
|
||||
IntcConfig->CpuBaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
|
||||
/* Connect the device driver handler that will be called when an
|
||||
* interrupt for the device occurs, the handler defined above performs
|
||||
* the specific interrupt processing for the device. */
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
Status = XIntc_Connect(IntcPtr, DpIntrId,
|
||||
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
|
||||
#else
|
||||
Status = XScuGic_Connect(IntcPtr, DpIntrId,
|
||||
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Start the interrupt controller. */
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
XIntc_Enable(IntcPtr, DpIntrId);
|
||||
#else
|
||||
XScuGic_Enable(IntcPtr, DpIntrId);
|
||||
#endif /* XPAR_INTC_0_DEVICE_ID */
|
||||
|
||||
/* Initialize the exception table. */
|
||||
Xil_ExceptionInit();
|
||||
|
||||
/* Register the interrupt controller handler with the exception table. */
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
|
||||
|
||||
/* Enable exceptions. */
|
||||
Xil_ExceptionEnable();
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is called when a Hot-Plug-Detect (HPD) event is received by the
|
||||
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the
|
||||
* core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
|
||||
* occurred.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note Use the XDptx_SetHpdEventHandler driver function to set this
|
||||
* function as the handler for HPD pulses.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_HpdEventHandler(void *InstancePtr)
|
||||
{
|
||||
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
|
||||
|
||||
if (XDptx_IsConnected(XDptx_InstancePtr)) {
|
||||
xil_printf("+===> HPD connection event detected.\n");
|
||||
|
||||
Dptx_Run(XDptx_InstancePtr);
|
||||
}
|
||||
else {
|
||||
xil_printf("+===> HPD disconnection event detected.\n\n");
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is called when a Hot-Plug-Detect (HPD) pulse is received by the
|
||||
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit
|
||||
* of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
|
||||
* occurred.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note Use the XDptx_SetHpdPulseHandler driver function to set this
|
||||
* function as the handler for HPD pulses.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_HpdPulseHandler(void *InstancePtr)
|
||||
{
|
||||
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
|
||||
|
||||
xil_printf("===> HPD pulse detected.\n");
|
||||
|
||||
Dptx_Run(XDptx_InstancePtr);
|
||||
}
|
||||
385
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c
Normal file
385
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c
Normal file
|
|
@ -0,0 +1,385 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_mst_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver in multi-stream transport
|
||||
* (MST) mode.
|
||||
*
|
||||
* @note For this example to display output, the user will need to
|
||||
* implement initialization of the system (Dptx_PlatformInit) and,
|
||||
* after training is complete, implement configuration of the video
|
||||
* stream source in order to provide the DisplayPort core with
|
||||
* input. See XAPP1178 for reference.
|
||||
* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
|
||||
* extern in xdptx_example_common.h and are left up to the user to
|
||||
* implement.
|
||||
* @note Some setups may require introduction of delays when sending
|
||||
* sideband messages.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 08/07/14 Initial creation.
|
||||
* 2.0 als 09/23/14 Improved programming sequence for payload allocation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
|
||||
/**************************** Constant Definitions ****************************/
|
||||
|
||||
/* The maximum number of streams to enable. */
|
||||
#define NUM_STREAMS 4
|
||||
|
||||
/* This enables topology discovery which will create a list of sinks in the
|
||||
* topology. If ALLOCATE_FROM_SINKLIST is defined, the streams will sent to
|
||||
* to the sinks with the corresponding index. See the function calls for
|
||||
* the XDptx_SetStreamSelectFromSinkList driver function below. */
|
||||
#define ALLOCATE_FROM_SINKLIST
|
||||
#ifdef ALLOCATE_FROM_SINKLIST
|
||||
/* Define the mapping between sinks and streams. The sink numbers are in the
|
||||
* order that they are discovered by the XDptx_FindAccessibleDpDevices driver
|
||||
* function. */
|
||||
#define STREAM0_USE_SINKNUM 0
|
||||
#define STREAM1_USE_SINKNUM 1
|
||||
#define STREAM2_USE_SINKNUM 2
|
||||
#define STREAM3_USE_SINKNUM 3
|
||||
#endif
|
||||
|
||||
/* The video resolution from the display mode timings (DMT) table to use for
|
||||
* each stream. */
|
||||
#define USE_VIDEO_MODE XDPTX_VM_1920x1080_60_P
|
||||
|
||||
/* The color depth (bits per color component) to use for each stream. */
|
||||
#define USE_BPC 8
|
||||
|
||||
/* Some MST configurations may require delays when sending sideband messages. By
|
||||
* default, disable these delays.*/
|
||||
#undef USE_DELAYS_FOR_MST
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId);
|
||||
u32 Dptx_MstExampleRun(XDptx *InstancePtr);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx multi-stream transport (MST)
|
||||
* example.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the MST example was unsuccessful - system
|
||||
* setup failed.
|
||||
*
|
||||
* @note Unless setup failed, main will never return since
|
||||
* Dptx_MstExample is blocking.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* Run the XDptx MST example. */
|
||||
Dptx_MstExample(&DptxInstance, DPTX_DEVICE_ID);
|
||||
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the multi-stream transport (MST) example using the
|
||||
* XDptx driver. This function will either discover the topology and map streams
|
||||
* to the sinks in the sink list, or map streams to relative addresses.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the system setup failed.
|
||||
* - XST_SUCCESS should never return since this function, if setup
|
||||
* was successful, is blocking.
|
||||
*
|
||||
* @note If system setup was successful, this function is blocking.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Do platform initialization here. This is hardware system specific -
|
||||
* it is up to the user to implement this function. */
|
||||
Dptx_PlatformInit();
|
||||
/******************/
|
||||
|
||||
Status = Dptx_SetupExample(InstancePtr, DeviceId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XDptx_MstCapable(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
/* If the immediate downstream RX device is an MST monitor and
|
||||
* the DisplayPort Configuration Data (DPCD) does not indicate
|
||||
* MST capability, it is likely that the MST or DisplayPort v1.2
|
||||
* option must be selected from the monitor's option menu.
|
||||
* Likewise, the DisplayPort TX core must be configured to
|
||||
* support MST mode. */
|
||||
xil_printf("!!! Verify DisplayPort MST capabilities in the TX "
|
||||
"and/or RX device.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
do {
|
||||
Status = Dptx_MstExampleRun(InstancePtr);
|
||||
if (Status == XST_DATA_LOST) {
|
||||
xil_printf("!!! Link lost... Need to re-train.\n");
|
||||
}
|
||||
} while (Status != XST_SUCCESS);
|
||||
|
||||
/* Do not return. */
|
||||
xil_printf("MST example DONE.\n");
|
||||
while (1);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function trains the link and allocates stream payloads.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if MST allocation was successful.
|
||||
* - XST_ERROR_COUNT_MAX if the ACT trigger was lost.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_MstExampleRun(XDptx *InstancePtr)
|
||||
{
|
||||
u32 Status;
|
||||
u32 MaskVal;
|
||||
u8 StreamIndex;
|
||||
XDptx_VideoMode VideoMode = USE_VIDEO_MODE;
|
||||
u8 Bpc = USE_BPC;
|
||||
u8 NumStreams = NUM_STREAMS;
|
||||
|
||||
/* Limit the number of streams to configure based on the configuration
|
||||
* of the DisplayPort core. */
|
||||
if (NumStreams > InstancePtr->Config.NumMstStreams) {
|
||||
NumStreams = InstancePtr->Config.NumMstStreams;
|
||||
}
|
||||
|
||||
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
|
||||
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
|
||||
|
||||
/* A DisplayPort connection must exist at this point. See the interrupt
|
||||
* and polling examples for waiting for connection events. */
|
||||
Status = Dptx_StartLink(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Link Training failed.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
#ifdef USE_DELAYS_FOR_MST
|
||||
InstancePtr->AuxDelayUs = 30000;
|
||||
InstancePtr->SbMsgDelayUs = 100000;
|
||||
#else
|
||||
InstancePtr->AuxDelayUs = 0;
|
||||
InstancePtr->SbMsgDelayUs = 0;
|
||||
#endif
|
||||
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
|
||||
XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
|
||||
|
||||
#ifdef ALLOCATE_FROM_SINKLIST
|
||||
/* Run topology discovery to determine what devices are accessible to
|
||||
* the DisplayPort TX. */
|
||||
xil_printf("Find topology >>>\n");
|
||||
InstancePtr->Topology.NodeTotal = 0;
|
||||
InstancePtr->Topology.SinkTotal = 0;
|
||||
|
||||
Status = XDptx_DiscoverTopology(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("!!! A LINK_ADDRESS response from a branch device "
|
||||
"in the MST topology was not successfully received.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf("<<< Find topology DONE; # of sinks found = %d.\n",
|
||||
InstancePtr->Topology.SinkTotal);
|
||||
|
||||
if (NumStreams > InstancePtr->Topology.SinkTotal) {
|
||||
NumStreams = InstancePtr->Topology.SinkTotal;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable multi-stream transport (MST) mode for this example. */
|
||||
XDptx_MstCfgModeEnable(InstancePtr);
|
||||
for (StreamIndex = 0; StreamIndex < NumStreams; StreamIndex++) {
|
||||
XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID0 +
|
||||
StreamIndex);
|
||||
}
|
||||
for (StreamIndex = NumStreams; StreamIndex < 4; StreamIndex++) {
|
||||
XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID0 +
|
||||
StreamIndex);
|
||||
}
|
||||
|
||||
/* Specify the DisplayPort sink devices that each enabled stream will be
|
||||
* directed towards. */
|
||||
#ifndef ALLOCATE_FROM_SINKLIST
|
||||
/* If topology discovery is not used, specify the relative addresses of
|
||||
* the DisplayPort sink devices. */
|
||||
u8 Lct;
|
||||
u8 Rad[15];
|
||||
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) {
|
||||
Lct = 2; Rad[0] = 8;
|
||||
XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID0, Lct, Rad);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
|
||||
Lct = 3; Rad[0] = 1; Rad[1] = 8;
|
||||
XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID1, Lct, Rad);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) {
|
||||
Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8;
|
||||
XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID2, Lct, Rad);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) {
|
||||
Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 9;
|
||||
XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad);
|
||||
}
|
||||
#else
|
||||
/* If topology discovery is used, associate a stream number with a sink
|
||||
* number from the sink list obtained during topology discovery. The
|
||||
* sinks are numbered in the order that they were found during topology
|
||||
* discovery. */
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) {
|
||||
XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID0,
|
||||
STREAM0_USE_SINKNUM);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
|
||||
XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1,
|
||||
STREAM1_USE_SINKNUM);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) {
|
||||
XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID2,
|
||||
STREAM2_USE_SINKNUM);
|
||||
}
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) {
|
||||
XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3,
|
||||
STREAM3_USE_SINKNUM);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Reset MST mode in both the RX and TX. */
|
||||
XDptx_MstDisable(InstancePtr);
|
||||
XDptx_MstEnable(InstancePtr);
|
||||
|
||||
/* Set the main stream attributes (MSA) for each enabled stream (each
|
||||
* stream has an identical configuration). Then, set the configuration
|
||||
* for that stream in the corresponding DisplayPort TX registers. */
|
||||
for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
|
||||
if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 +
|
||||
StreamIndex)) {
|
||||
XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0 +
|
||||
StreamIndex, Bpc);
|
||||
XDptx_CfgMsaEnSynchClkMode(InstancePtr,
|
||||
XDPTX_STREAM_ID0 + StreamIndex, 1);
|
||||
|
||||
XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
|
||||
XDPTX_STREAM_ID0 + StreamIndex, VideoMode);
|
||||
XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0 +
|
||||
StreamIndex);
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure video stream source or generator here. This function needs
|
||||
* to be implemented in order for video to be displayed and is hardware
|
||||
* system specific. It is up to the user to implement this function. */
|
||||
Dptx_StreamSrcSetup(InstancePtr);
|
||||
Dptx_StreamSrcConfigure(InstancePtr);
|
||||
Dptx_StreamSrcSync(InstancePtr);
|
||||
////////////////////////////////////
|
||||
|
||||
/* Mask interrupts while allocating payloads. */
|
||||
MaskVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_INTERRUPT_MASK);
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK,
|
||||
0x3F);
|
||||
|
||||
/* Clear the payload ID table first. */
|
||||
Status = XDptx_ClearPayloadVcIdTable(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_DATA_LOST;
|
||||
}
|
||||
|
||||
/* Allocate payloads. */
|
||||
Status = XDptx_AllocatePayloadStreams(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_DATA_LOST;
|
||||
}
|
||||
|
||||
/* Enable the main link. */
|
||||
XDptx_EnableMainLink(InstancePtr);
|
||||
|
||||
/* Unmask interrupts. */
|
||||
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK,
|
||||
MaskVal);
|
||||
|
||||
/* Do a final check to verify that the link wasn't lost. */
|
||||
Status = XDptx_CheckLinkStatus(InstancePtr,
|
||||
InstancePtr->LinkConfig.LaneCount);
|
||||
if (Status != XST_SUCCESS) {
|
||||
XDptx_WaitUs(InstancePtr, 10000);
|
||||
return XST_DATA_LOST;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
200
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
Normal file
200
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_poll_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver with polling. Once the
|
||||
* polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/
|
||||
* unplugged or the monitor is turned on/off), the main link will be trained.
|
||||
*
|
||||
* @note For this example to display output, the user will need to
|
||||
* implement initialization of the system (Dptx_PlatformInit) and,
|
||||
* after training is complete, implement configuration of the video
|
||||
* stream source in order to provide the DisplayPort core with
|
||||
* input (Dptx_StreamSrc* - called in xdptx_example_common.c). See
|
||||
* XAPP1178 for reference.
|
||||
* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
|
||||
* extern in xdptx_example_common.h and are left up to the user to
|
||||
* implement.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId);
|
||||
static void Dptx_HpdPoll(XDptx *InstancePtr);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx polling example.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the polling example was unsuccessful - system
|
||||
* setup failed.
|
||||
*
|
||||
* @note Unless setup failed, main will never return since
|
||||
* Dptx_PollExample is blocking (it is continuously polling for
|
||||
* Hot-Plug-Detect (HPD) events.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* Run the XDptx polling example. */
|
||||
Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
|
||||
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the polling example using the XDptx driver. This
|
||||
* function will set up the system. If this is successful, this example will
|
||||
* begin polling the Hot-Plug-Detect (HPD) status registers for HPD events. Once
|
||||
* a connection event or a pulse is detected, link training will commence (if
|
||||
* needed) and a video stream will start being sent over the main link.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_FAILURE if the system setup failed.
|
||||
* - XST_SUCCESS should never return since this function, if setup
|
||||
* was successful, is blocking.
|
||||
*
|
||||
* @note If system setup was successful, this function is blocking in
|
||||
* order to illustrate polling taking place for HPD events.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Do platform initialization here. This is hardware system specific -
|
||||
* it is up to the user to implement this function. */
|
||||
Dptx_PlatformInit();
|
||||
/******************/
|
||||
|
||||
Status = Dptx_SetupExample(InstancePtr, DeviceId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
|
||||
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
|
||||
|
||||
/* Continuously poll for HPD events. */
|
||||
while (1) {
|
||||
Dptx_HpdPoll(InstancePtr);
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function polls the XDPTX_INTERRUPT_SIG_STATE and XDPTX_INTERRUPT_STATUS
|
||||
* registers for Hot-Plug-Detect (HPD) events and handles them accordingly. If a
|
||||
* connection or pulse event is detected, link training will begin (if required)
|
||||
* and a video stream will be initiated.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_HpdPoll(XDptx *InstancePtr)
|
||||
{
|
||||
u32 InterruptSignalState;
|
||||
u32 InterruptStatus;
|
||||
u32 HpdState;
|
||||
u32 HpdEvent;
|
||||
u32 HpdPulseDetected;
|
||||
u32 HpdDuration;
|
||||
|
||||
/* Read interrupt registers. */
|
||||
InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_INTERRUPT_SIG_STATE);
|
||||
InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_INTERRUPT_STATUS);
|
||||
|
||||
/* Check for HPD events. */
|
||||
HpdState = InterruptSignalState &
|
||||
XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
|
||||
HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
|
||||
HpdPulseDetected = InterruptStatus &
|
||||
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
|
||||
if (HpdPulseDetected) {
|
||||
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_HPD_DURATION);
|
||||
}
|
||||
|
||||
/* HPD event handling. */
|
||||
if (HpdState && HpdEvent) {
|
||||
xil_printf("+===> HPD connection event detected.\n");
|
||||
|
||||
/* Initiate link training. */
|
||||
Dptx_Run(InstancePtr);
|
||||
}
|
||||
else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
|
||||
xil_printf("===> HPD pulse detected.\n");
|
||||
|
||||
/* Re-train if needed. */
|
||||
Dptx_Run(InstancePtr);
|
||||
}
|
||||
else if (!HpdState && HpdEvent) {
|
||||
xil_printf("+===> HPD disconnection event detected.\n\n");
|
||||
|
||||
/* Disable main link. */
|
||||
XDptx_DisableMainLink(InstancePtr);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_selftest_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver. It performs a self test on
|
||||
* the DisplayPort TX core that will compare many of the DisplayPort TX core's
|
||||
* registers against their default reset values.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx selftest example.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the self test example passed.
|
||||
* - XST_FAILURE if the self test example was unsuccessful - the
|
||||
* DisplayPort TX's registers do not match their default values
|
||||
* or no DisplayPort TX instance was found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("XDptx_SelfTest failed, check register values.\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
xil_printf("XDptx_SelfTest passed.\n");
|
||||
return Status;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the selftest example using the XDptx driver. This
|
||||
* function will check whether or not the DisplayPort TX's registers are at
|
||||
* their default reset values to ensure that the core is in a known and working
|
||||
* state.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the DisplayPort TX's registers are at their
|
||||
* default reset values.
|
||||
* - XST_FAILURE if the DisplayPort TX's registers do not match
|
||||
* their default values or no DisplayPort TX instance was found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
u32 Status;
|
||||
XDptx_Config *ConfigPtr;
|
||||
|
||||
/* Obtain the device configuration for the DisplayPort TX core. */
|
||||
ConfigPtr = XDptx_LookupConfig(DeviceId);
|
||||
if (!ConfigPtr) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
/* Copy the device configuration into the InstancePtr's Config
|
||||
* structure. */
|
||||
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
|
||||
|
||||
/* Run the self test. */
|
||||
Status = XDptx_SelfTest(InstancePtr);
|
||||
return Status;
|
||||
}
|
||||
201
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
Normal file
201
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
Normal file
|
|
@ -0,0 +1,201 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_timer_example.c
|
||||
*
|
||||
* Contains a design example using the XDptx driver with a user-defined hook
|
||||
* for delay. The reasoning behind this is that MicroBlaze sleep is not very
|
||||
* accurate without a hardware timer. For systems that have a hardware timer,
|
||||
* the user may override the default MicroBlaze sleep with a function that will
|
||||
* use the hardware timer.
|
||||
*
|
||||
* @note This example requires an AXI timer in the system.
|
||||
* @note For this example to display output, the user will need to
|
||||
* implement initialization of the system (Dptx_PlatformInit) and,
|
||||
* after training is complete, implement configuration of the video
|
||||
* stream source in order to provide the DisplayPort core with
|
||||
* input (Dptx_StreamSrc* - called in xdptx_example_common.c). See
|
||||
* XAPP1178 for reference.
|
||||
* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
|
||||
* extern in xdptx_example_common.h and are left up to the user to
|
||||
* implement.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 06/17/14 Initial creation.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_example_common.h"
|
||||
#include "xtmrctr.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
|
||||
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
|
||||
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds);
|
||||
|
||||
/*************************** Variable Declarations ****************************/
|
||||
|
||||
XTmrCtr TimerCounterInst; /* The timer counter instance. */
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the main function of the XDptx timer example.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the timer example finished successfully.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Run the XDptx timer example. */
|
||||
Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
|
||||
&TimerCounterInst, &Dptx_CustomWaitUs);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* The main entry point for the timer example using the XDptx driver. This
|
||||
* function will set up the system and the custom sleep handler. If this is
|
||||
* successful, link training will commence and a video stream will start being
|
||||
* sent over the main link.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param DeviceId is the unique device ID of the DisplayPort TX core
|
||||
* instance.
|
||||
* @param TimerCounterPtr is a pointer to the timer instance.
|
||||
* @param UserSleepFunc is a pointer to the custom handler for sleep.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the system was set up correctly and link
|
||||
* training was successful.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
|
||||
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/* Use single-stream transport (SST) mode for this example. */
|
||||
XDptx_MstCfgModeDisable(InstancePtr);
|
||||
|
||||
/* Do platform initialization here. This is hardware system specific -
|
||||
* it is up to the user to implement this function. */
|
||||
Dptx_PlatformInit();
|
||||
/*******************/
|
||||
|
||||
/* Set a custom timer handler for improved delay accuracy on MicroBlaze
|
||||
* systems since the driver does not assume/have a dependency on the
|
||||
* system having a timer in the FPGA.
|
||||
* Note: This only has an affect for MicroBlaze systems since the Zynq
|
||||
* ARM SoC contains a timer, which is used when the driver calls the
|
||||
* delay function. */
|
||||
XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
|
||||
|
||||
Status = Dptx_SetupExample(InstancePtr, DeviceId);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
|
||||
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
|
||||
|
||||
/* A sink monitor must be connected at this point. See the polling or
|
||||
* interrupt examples for how to wait for a connection event. */
|
||||
Status = Dptx_Run(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is used to override the driver's default sleep functionality.
|
||||
* For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior
|
||||
* is to use the MB_Sleep function from microblaze_sleep.h, which is implemented
|
||||
* in software and only has millisecond accuracy. For this reason, using a
|
||||
* hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is
|
||||
* used - XDptx_WaitUs will ignore this custom timer handler.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note Use the XDptx_SetUserTimerHandler driver function to set this
|
||||
* function as the handler for when the XDptx_WaitUs driver
|
||||
* function is called.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
|
||||
{
|
||||
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
|
||||
u32 TimerVal;
|
||||
|
||||
XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0);
|
||||
|
||||
/* Wait specified number of useconds. */
|
||||
do {
|
||||
TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
|
||||
}
|
||||
while (TimerVal < (MicroSeconds *
|
||||
(XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
|
||||
|
||||
XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
|
||||
}
|
||||
40
XilinxProcessorIPLib/drivers/dptx/src/Makefile
Executable file
40
XilinxProcessorIPLib/drivers/dptx/src/Makefile
Executable file
|
|
@ -0,0 +1,40 @@
|
|||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
OUTS = *.o
|
||||
|
||||
LIBSOURCES:=*.c
|
||||
INCLUDEFILES:=*.h
|
||||
|
||||
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
|
||||
|
||||
libs: banner xdptx_libs clean
|
||||
|
||||
%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
|
||||
|
||||
banner:
|
||||
echo "Compiling dptx"
|
||||
|
||||
xdptx_libs: ${OBJECTS}
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
|
||||
|
||||
.PHONY: include
|
||||
include: xdptx_includes
|
||||
|
||||
xdptx_includes:
|
||||
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
|
||||
|
||||
clean:
|
||||
rm -rf ${OBJECTS}
|
||||
2626
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
Normal file
2626
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
Normal file
File diff suppressed because it is too large
Load diff
865
XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
Normal file
865
XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
Normal file
|
|
@ -0,0 +1,865 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx.h
|
||||
*
|
||||
* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
|
||||
* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
|
||||
* DisplayPort 1.2a specification.
|
||||
*
|
||||
* The Xilinx DisplayPort soft IP supports the following features:
|
||||
* - 1, 2, or 4 lanes.
|
||||
* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
|
||||
* - 1, 2, or 4 pixel-wide video interfaces.
|
||||
* - RGB and YCbCr color space.
|
||||
* - Up to 16 bits per component.
|
||||
* - Up to 4Kx2K monitor resolution.
|
||||
* - Auto lane rate and width negotiation.
|
||||
* - I2C over a 1Mb/s AUX channel.
|
||||
* - Secondary channel audio support (2 channels).
|
||||
* - 4 independent video multi-streams.
|
||||
*
|
||||
* The Xilinx DisplayPort soft IP does not support the following features:
|
||||
* - The automated test feature.
|
||||
* - Audio (3-8 channel).
|
||||
* - FAUX.
|
||||
* - Bridging function.
|
||||
* - MST audio.
|
||||
* - eDP optional features.
|
||||
* - iDP.
|
||||
* - GTC.
|
||||
*
|
||||
* <b>DisplayPort overview</b>
|
||||
*
|
||||
* A DisplayPort link consists of:
|
||||
* - A unidirectional main link which is used to transport isochronous data
|
||||
* streams such as video and audio. The main link may use 1, 2, or 4
|
||||
* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
|
||||
* needs to be trained prior to sending streams.
|
||||
* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
|
||||
* link training, link management, and device control.
|
||||
* - A hot-plug-detect (HPD) signal line is used to determine whether a
|
||||
* DisplayPort connection exists between the DisplayPort TX connector and
|
||||
* an RX device. It is serves as an interrupt request by the RX device.
|
||||
*
|
||||
* <b>Driver description</b>
|
||||
*
|
||||
* The device driver enables higher-level software (e.g., an application) to
|
||||
* configure and control a DisplayPort TX soft IP, communicate and control an
|
||||
* RX device/sink monitor over the AUX channel, and to initialize and transmit
|
||||
* data streams over the main link.
|
||||
*
|
||||
* This driver implements link layer functionality: a Link Policy Maker (LPM)
|
||||
* and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
|
||||
* - The LPM manages the main link and is responsible for keeping the link
|
||||
* synchronized. It will establish a link with a downstream RX device by
|
||||
* undergoing a link training sequence which consists of:
|
||||
* - Clock recovery: The clock needs to be recovered and PLLs need to be
|
||||
* locked for all lanes.
|
||||
* - Channel equalization: All lanes need to achieve channel equalization
|
||||
* and and symbol lock, as well as for interlane alignment to take place.
|
||||
* - The SPM manages transportation of an isochronous stream. That is, it will
|
||||
* initialize and maintain a video stream, establish a virtual channel to a
|
||||
* sink monitor, and transmit the stream.
|
||||
*
|
||||
* Using AUX transactions to read/write from/to the sink's DisplayPort
|
||||
* Configuration Data (DPCD) address space, the LPM obtains the link
|
||||
* capabilities, obtains link configuration and link and sink status, and
|
||||
* configures and controls the link and sink. The main link is trained this way.
|
||||
*
|
||||
* I2C-over-AUX transactions are used to obtain the sink's Extended Display
|
||||
* Identification Data (EDID) which give information on the display capabilities
|
||||
* of the monitor. The SPM may use this information to determine what available
|
||||
* screen resolutions and video timing are possible.
|
||||
*
|
||||
* <b>Device configuration</b>
|
||||
*
|
||||
* The device can be configured in various ways during the FPGA implementation
|
||||
* process. Configuration parameters are stored in the xdptx_g.c file which is
|
||||
* generated when compiling the board support package (BSP). A table is defined
|
||||
* where each entry contains configuration information for the DisplayPort
|
||||
* instances present in the system. This information includes parameters that
|
||||
* are defined in the driver's data/dptx.tcl file such as the base address of
|
||||
* the memory-mapped device and the maximum number of lanes, maximum link rate,
|
||||
* and video interface that the DisplayPort instance supports, among others.
|
||||
*
|
||||
* <b>Interrupt processing</b>
|
||||
*
|
||||
* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
|
||||
* cable is connected/disconnected or when the RX device sends a pulse. The user
|
||||
* hardware design must contain an interrupt controller which the DisplayPort
|
||||
* TX instance's interrupt signal is connected to. The user application must
|
||||
* enable interrupts in the system and set up the interrupt controller such that
|
||||
* the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
|
||||
* When the XDptx_HpdInterruptHandler function is invoked, the handler will
|
||||
* identify what type of DisplayPort interrupt has occurred, and will call
|
||||
* either the HPD event handler function or the HPD pulse handler function,
|
||||
* depending on whether a an HPD event on an HPD pulse event occurred.
|
||||
*
|
||||
* The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of
|
||||
* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
|
||||
* information to decide which handler to call. An HPD event is identified if
|
||||
* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
|
||||
* identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
|
||||
*
|
||||
* The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
|
||||
* function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
|
||||
* function.
|
||||
*
|
||||
* <b>Multi-stream transport (MST) mode</b>
|
||||
*
|
||||
* The driver handles MST mode functionality, including sideband messaging,
|
||||
* topology discovery, virtual channel payload ID table management, and
|
||||
* directing streams to different sinks.
|
||||
*
|
||||
* MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy-
|
||||
* chain configuration, with each stream having the same resolution. Testing has
|
||||
* been done at the following resolutions: 640x480, 720x480, 800x600, 848x480,
|
||||
* 1024x768, 1280x720, 1280x1024, 1080p, and UHD (UHD/2 on 2 streams). Each
|
||||
* resolutions was tested at 24 bits per pixel using 1, 2, 3, and 4 streams.
|
||||
* Color depths of 18, 30, 36, and 48 bits per pixel were also tested.
|
||||
*
|
||||
* <b>Audio</b>
|
||||
*
|
||||
* The driver does not handle audio. For an example as to how to configure and
|
||||
* transmit audio, dptx_v2_0/examples/xdptx_audio_example.c illustrates the
|
||||
* required sequence. The user will need to configure the audio source connected
|
||||
* to the Displayport TX instance and set up the audio info frame as per user
|
||||
* requirements.
|
||||
*
|
||||
* <b>Asserts</b>
|
||||
*
|
||||
* Asserts are used within all Xilinx drivers to enforce constraints on argument
|
||||
* values. Asserts can be turned off on a system-wide basis by defining, at
|
||||
* compile time, the NDEBUG identifier. By default, asserts are turned on and
|
||||
* it is recommended that application developers leave asserts on during
|
||||
* development.
|
||||
*
|
||||
* <b>Limitations and known issues</b>
|
||||
*
|
||||
* - For MST mode to correctly display, the current version of the driver
|
||||
* requires that each of the DisplayPort TX streams be allocated without
|
||||
* skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems
|
||||
* were experienced if skipping stream 2 and assigning stream 4 instead).
|
||||
* skipping monitors in a daisy chain is OK as long as they are assigned to
|
||||
* streams in order.
|
||||
* - In MST mode, the current version of the driver does not support removal of
|
||||
* an allocated stream from the virtual channel payload ID table without
|
||||
* clearing the entire table.
|
||||
* - Some sideband messages have not been implemented in the current version of
|
||||
* the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY
|
||||
* sideband message.
|
||||
* - The driver does not handle audio. See the audio example in the driver
|
||||
* examples directory for the required sequence for enabling audio.
|
||||
*
|
||||
* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
|
||||
* required with a speed grade of -2 or -3.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* als 08/03/14 Initial MST addition.
|
||||
* 2.0 als 09/21/14 Added XDptx_DiscoverTopology function and changed
|
||||
* XDptx_IsConnected from macro to function.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef XDPTX_H_
|
||||
/* Prevent circular inclusions by using protection macros. */
|
||||
#define XDPTX_H_
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx_hw.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/****************************** Type Definitions ******************************/
|
||||
|
||||
/**
|
||||
* This typedef enumerates the list of available standard display monitor
|
||||
* timings as specified in the mode_table.c file. The naming format is:
|
||||
*
|
||||
* XDPTX_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|RB>
|
||||
*
|
||||
* Where RB stands for reduced blanking.
|
||||
*/
|
||||
typedef enum {
|
||||
XDPTX_VM_640x480_60_P,
|
||||
XDPTX_VM_800x600_60_P,
|
||||
XDPTX_VM_848x480_60_P,
|
||||
XDPTX_VM_1024x768_60_P,
|
||||
XDPTX_VM_1280x768_60_P_RB,
|
||||
XDPTX_VM_1280x768_60_P,
|
||||
XDPTX_VM_1280x800_60_P_RB,
|
||||
XDPTX_VM_1280x800_60_P,
|
||||
XDPTX_VM_1280x960_60_P,
|
||||
XDPTX_VM_1280x1024_60_P,
|
||||
XDPTX_VM_1360x768_60_P,
|
||||
XDPTX_VM_1400x1050_60_P_RB,
|
||||
XDPTX_VM_1400x1050_60_P,
|
||||
XDPTX_VM_1440x900_60_P_RB,
|
||||
XDPTX_VM_1440x900_60_P,
|
||||
XDPTX_VM_1600x1200_60_P,
|
||||
XDPTX_VM_1680x1050_60_P_RB,
|
||||
XDPTX_VM_1680x1050_60_P,
|
||||
XDPTX_VM_1792x1344_60_P,
|
||||
XDPTX_VM_1856x1392_60_P,
|
||||
XDPTX_VM_1920x1200_60_P_RB,
|
||||
XDPTX_VM_1920x1200_60_P,
|
||||
XDPTX_VM_1920x1440_60_P,
|
||||
XDPTX_VM_2560x1600_60_P_RB,
|
||||
XDPTX_VM_2560x1600_60_P,
|
||||
XDPTX_VM_800x600_56_P,
|
||||
XDPTX_VM_1600x1200_65_P,
|
||||
XDPTX_VM_1600x1200_70_P,
|
||||
XDPTX_VM_1024x768_70_P,
|
||||
XDPTX_VM_640x480_72_P,
|
||||
XDPTX_VM_800x600_72_P,
|
||||
XDPTX_VM_640x480_75_P,
|
||||
XDPTX_VM_800x600_75_P,
|
||||
XDPTX_VM_1024x768_75_P,
|
||||
XDPTX_VM_1152x864_75_P,
|
||||
XDPTX_VM_1280x768_75_P,
|
||||
XDPTX_VM_1280x800_75_P,
|
||||
XDPTX_VM_1280x1024_75_P,
|
||||
XDPTX_VM_1400x1050_75_P,
|
||||
XDPTX_VM_1440x900_75_P,
|
||||
XDPTX_VM_1600x1200_75_P,
|
||||
XDPTX_VM_1680x1050_75_P,
|
||||
XDPTX_VM_1792x1344_75_P,
|
||||
XDPTX_VM_1856x1392_75_P,
|
||||
XDPTX_VM_1920x1200_75_P,
|
||||
XDPTX_VM_1920x1440_75_P,
|
||||
XDPTX_VM_2560x1600_75_P,
|
||||
XDPTX_VM_640x350_85_P,
|
||||
XDPTX_VM_640x400_85_P,
|
||||
XDPTX_VM_720x400_85_P,
|
||||
XDPTX_VM_640x480_85_P,
|
||||
XDPTX_VM_800x600_85_P,
|
||||
XDPTX_VM_1024x768_85_P,
|
||||
XDPTX_VM_1280x768_85_P,
|
||||
XDPTX_VM_1280x800_85_P,
|
||||
XDPTX_VM_1280x960_85_P,
|
||||
XDPTX_VM_1280x1024_85_P,
|
||||
XDPTX_VM_1400x1050_85_P,
|
||||
XDPTX_VM_1440x900_85_P,
|
||||
XDPTX_VM_1600x1200_85_P,
|
||||
XDPTX_VM_1680x1050_85_P,
|
||||
XDPTX_VM_1920x1200_85_P,
|
||||
XDPTX_VM_2560x1600_85_P,
|
||||
XDPTX_VM_800x600_120_P_RB,
|
||||
XDPTX_VM_1024x768_120_P_RB,
|
||||
XDPTX_VM_1280x768_120_P_RB,
|
||||
XDPTX_VM_1280x800_120_P_RB,
|
||||
XDPTX_VM_1280x960_120_P_RB,
|
||||
XDPTX_VM_1280x1024_120_P_RB,
|
||||
XDPTX_VM_1360x768_120_P_RB,
|
||||
XDPTX_VM_1400x1050_120_P_RB,
|
||||
XDPTX_VM_1440x900_120_P_RB,
|
||||
XDPTX_VM_1600x1200_120_P_RB,
|
||||
XDPTX_VM_1680x1050_120_P_RB,
|
||||
XDPTX_VM_1792x1344_120_P_RB,
|
||||
XDPTX_VM_1856x1392_120_P_RB,
|
||||
XDPTX_VM_1920x1200_120_P_RB,
|
||||
XDPTX_VM_1920x1440_120_P_RB,
|
||||
XDPTX_VM_2560x1600_120_P_RB,
|
||||
XDPTX_VM_1366x768_60_P,
|
||||
XDPTX_VM_1920x1080_60_P,
|
||||
XDPTX_VM_UHD_30_P,
|
||||
XDPTX_VM_720_60_P,
|
||||
XDPTX_VM_480_60_P,
|
||||
XDPTX_VM_UHD2_60_P,
|
||||
XDPTX_VM_UHD_60,
|
||||
XDPTX_VM_USE_EDID_PREFERRED,
|
||||
XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
|
||||
} XDptx_VideoMode;
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the DisplayPort TX core.
|
||||
*/
|
||||
typedef struct {
|
||||
u16 DeviceId; /**< Device instance ID. */
|
||||
u32 BaseAddr; /**< The base address of the core instance. */
|
||||
u32 SAxiClkHz; /**< The clock frequency of the core instance's
|
||||
S_AXI_ACLK port. */
|
||||
u8 MaxLaneCount; /**< The maximum lane count supported by this
|
||||
core instance. */
|
||||
u8 MaxLinkRate; /**< The maximum link rate supported by this
|
||||
core instance. */
|
||||
u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
|
||||
core instance*/
|
||||
u8 QuadPixelEn; /**< Quad pixel support by this core
|
||||
instance. */
|
||||
u8 DualPixelEn; /**< Dual pixel support by this core
|
||||
instance. */
|
||||
u8 YCrCbEn; /**< YCrCb format support by this core
|
||||
instance. */
|
||||
u8 YOnlyEn; /**< YOnly format support by this core
|
||||
instance. */
|
||||
u8 PayloadDataWidth; /**< The payload data width used by this core
|
||||
instance. */
|
||||
u8 SecondaryChEn; /**< This core instance supports audio packets
|
||||
being sent by the secondary channel. */
|
||||
u8 NumAudioChs; /**< The number of audio channels supported by
|
||||
this core instance. */
|
||||
u8 MstSupport; /**< Multi-stream transport (MST) mode is
|
||||
enabled by this core instance. */
|
||||
u8 NumMstStreams; /**< The total number of MST streams supported
|
||||
by this core instance. */
|
||||
u8 DpProtocol; /**< The DisplayPort protocol version that this
|
||||
core instance is configured for.
|
||||
0 = v1.1a, 1 = v1.2. */
|
||||
} XDptx_Config;
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information about the RX device.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
|
||||
/**< The raw capabilities field
|
||||
of the RX device's DisplayPort
|
||||
Configuration Data (DPCD). */
|
||||
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
|
||||
RX device's status registers.
|
||||
The first 4 bytes correspond to
|
||||
the lane status associated with
|
||||
clock recovery, channel
|
||||
equalization, symbol lock, and
|
||||
interlane alignment. The
|
||||
remaining 2 bytes represent the
|
||||
pre-emphasis and voltage swing
|
||||
level adjustments requested by
|
||||
the RX device. */
|
||||
} XDptx_SinkConfig;
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information about the main link settings.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 LaneCount; /**< The current lane count of the main
|
||||
link. */
|
||||
u8 LinkRate; /**< The current link rate of the main
|
||||
link. */
|
||||
u8 ScramblerEn; /**< Symbol scrambling is currently in
|
||||
use over the main link. */
|
||||
u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
|
||||
use over the main link. */
|
||||
u8 DownspreadControl; /**< Downspread control is currently in
|
||||
use over the main link. */
|
||||
u8 MaxLaneCount; /**< The maximum lane count of the main
|
||||
link. */
|
||||
u8 MaxLinkRate; /**< The maximum link rate of the main
|
||||
link. */
|
||||
u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
|
||||
the RX device. */
|
||||
u8 SupportDownspreadControl; /**< Downspread control is supported by
|
||||
the RX device. */
|
||||
u8 VsLevel; /**< The current voltage swing level for
|
||||
each lane. */
|
||||
u8 PeLevel; /**< The current pre-emphasis/cursor
|
||||
level for each lane. */
|
||||
u8 Pattern; /**< The current pattern currently in
|
||||
use over the main link. */
|
||||
} XDptx_LinkConfig;
|
||||
|
||||
/**
|
||||
* This typedef contains the display monitor timing attributes for a video mode.
|
||||
*/
|
||||
typedef struct {
|
||||
XDptx_VideoMode VideoMode; /**< Enumerated key. */
|
||||
u8 DmtId; /**< Standard Display Monitor Timing
|
||||
(DMT) ID number. */
|
||||
u16 HResolution; /**< Horizontal resolution (in
|
||||
pixels). */
|
||||
u16 VResolution; /**< Vertical resolution (in lines). */
|
||||
u32 PixelClkKhz; /**< Pixel frequency (in KHz). This is
|
||||
also the M value for the video
|
||||
stream (MVid). */
|
||||
u8 Interlaced; /**< Input stream interlaced scan
|
||||
(0=non-interlaced/
|
||||
1=interlaced). */
|
||||
u8 HSyncPolarity; /**< Horizontal synchronization polarity
|
||||
(0=positive/1=negative). */
|
||||
u8 VSyncPolarity; /**< Vertical synchronization polarity
|
||||
(0=positive/1=negative). */
|
||||
u32 HFrontPorch; /**< Horizontal front porch (in
|
||||
pixels). */
|
||||
u32 HSyncPulseWidth; /**< Horizontal synchronization time
|
||||
(pulse width in pixels). */
|
||||
u32 HBackPorch; /**< Horizontal back porch (in
|
||||
pixels). */
|
||||
u32 VFrontPorch; /**< Vertical front porch (in lines). */
|
||||
u32 VSyncPulseWidth; /**< Vertical synchronization time
|
||||
(pulse width in lines). */
|
||||
u32 VBackPorch; /**< Vertical back porch (in lines). */
|
||||
} XDptx_DmtMode;
|
||||
|
||||
/**
|
||||
* This typedef contains the main stream attributes which determine how the
|
||||
* video will be displayed.
|
||||
*/
|
||||
typedef struct {
|
||||
XDptx_DmtMode Dmt; /**< Holds the set of Display Mode
|
||||
Timing (DMT) attributes that
|
||||
correspond to the information
|
||||
stored in the XDptx_DmtModes
|
||||
table. */
|
||||
u32 HClkTotal; /**< Horizontal total time (in
|
||||
pixels). */
|
||||
u32 VClkTotal; /**< Vertical total time (in pixels). */
|
||||
u32 HStart; /**< Horizontal blank start (in
|
||||
pixels). */
|
||||
u32 VStart; /**< Vertical blank start (in lines). */
|
||||
u32 Misc0; /**< Miscellaneous stream attributes 0
|
||||
as specified by the DisplayPort
|
||||
1.2 specification. */
|
||||
u32 Misc1; /**< Miscellaneous stream attributes 1
|
||||
as specified by the DisplayPort
|
||||
1.2 specification. */
|
||||
u32 NVid; /**< N value for the video stream. */
|
||||
u32 UserPixelWidth; /**< The width of the user data input
|
||||
port. */
|
||||
u32 DataPerLane; /**< Used to translate the number of
|
||||
pixels per line to the native
|
||||
internal 16-bit datapath. */
|
||||
u32 AvgBytesPerTU; /**< Average number of bytes per
|
||||
transfer unit, scaled up by a
|
||||
factor of 1000. */
|
||||
u32 TransferUnitSize; /**< Size of the transfer unit in the
|
||||
framing logic. In MST mode, this
|
||||
is also the number of time slots
|
||||
that are alloted in the payload
|
||||
ID table. */
|
||||
u32 InitWait; /**< Number of initial wait cycles at
|
||||
the start of a new line by
|
||||
the framing logic. */
|
||||
u32 BitsPerColor; /**< Number of bits per color
|
||||
component. */
|
||||
u8 ComponentFormat; /**< The component format currently in
|
||||
use by the video stream. */
|
||||
u8 DynamicRange; /**< The dynamic range currently in use
|
||||
by the video stream. */
|
||||
u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
|
||||
use by the video stream. */
|
||||
u8 SynchronousClockMode; /**< Synchronous clock mode is currently
|
||||
in use by the video stream. */
|
||||
u8 OverrideUserPixelWidth; /**< If set to 1, the value stored for
|
||||
UserPixelWidth will be used as
|
||||
the pixel width. */
|
||||
} XDptx_MainStreamAttributes;
|
||||
|
||||
/**
|
||||
* This typedef describes a stream when the driver is running in multi-stream
|
||||
* transport (MST) mode.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 LinkCountTotal; /** The total number of DisplayPort
|
||||
links from the DisplayPort TX to
|
||||
the sink device that this MST
|
||||
stream is targeting.*/
|
||||
u8 RelativeAddress[15]; /** The relative address from the
|
||||
DisplayPort TX to the sink
|
||||
device that this MST stream is
|
||||
targeting.*/
|
||||
u16 MstPbn; /**< Payload bandwidth number used to
|
||||
allocate bandwidth for the MST
|
||||
stream. */
|
||||
u8 MstStreamEnable; /**< In MST mode, enables the
|
||||
corresponding stream for this
|
||||
MSA configuration. */
|
||||
} XDptx_MstStream;
|
||||
|
||||
/**
|
||||
* This typedef describes some board characteristics information that affects
|
||||
* link training.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 HasRedriverInPath; /**< Redriver in path requires different voltage
|
||||
swing and pre-emphasis. */
|
||||
u8 TxVsLevels[4]; /**< The voltage swing levels to be used by the
|
||||
DisplayPort TX. */
|
||||
u8 TxPeLevels[4]; /**< The pre-emphasis/cursor level to be used by
|
||||
the DisplayPort TX. */
|
||||
u8 TxVsOffset; /**< Voltage swing compensation offset used when
|
||||
pre-emphasis is used. */
|
||||
} XDptx_BoardChar;
|
||||
|
||||
/**
|
||||
* This typedef describes a downstream DisplayPort device when the driver is
|
||||
* running in multi-stream transport (MST) mode.
|
||||
*/
|
||||
typedef struct {
|
||||
u32 Guid[4]; /**< The global unique identifier (GUID)
|
||||
of the device. */
|
||||
u8 RelativeAddress[15]; /**< The relative address from the
|
||||
DisplayPort TX to this
|
||||
device. */
|
||||
u8 DeviceType; /**< The type of DisplayPort device.
|
||||
Either a branch or sink. */
|
||||
u8 LinkCountTotal; /**< The total number of DisplayPort
|
||||
links connecting this device to
|
||||
the DisplayPort TX. */
|
||||
u8 DpcdRev; /**< The revision of the device's
|
||||
DisplayPort Configuration Data
|
||||
(DPCD). For this device to
|
||||
support MST features, this value
|
||||
must represent a protocl version
|
||||
greater or equal to 1.2. */
|
||||
u8 MsgCapStatus; /**< This device is capable of sending
|
||||
and receiving sideband
|
||||
messages. */
|
||||
} XDptx_TopologyNode;
|
||||
|
||||
/**
|
||||
* This typedef describes a the entire topology of connected downstream
|
||||
* DisplayPort devices (from the DisplayPort TX) when the driver is operating
|
||||
* in multi-stream transport (MST) mode.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 NodeTotal; /**< The total number of nodes that were
|
||||
found in the MST topology. */
|
||||
XDptx_TopologyNode NodeTable[63]; /**< A table listing all the nodes in
|
||||
the MST topology. */
|
||||
u8 SinkTotal; /**< The total number of sinks in the
|
||||
MST topology. */
|
||||
XDptx_TopologyNode *SinkList[63]; /**< A pointer list of sinks in the
|
||||
MST topology. The entries will
|
||||
point to the sinks in the
|
||||
NodeTable. */
|
||||
} XDptx_Topology;
|
||||
|
||||
/**
|
||||
* This typedef describes a port that is connected to a DisplayPort branch
|
||||
* device. This structure is used when the driver is operating in multi-stream
|
||||
* transport (MST) mode.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 InputPort; /**< Specifies that this port is an
|
||||
input port. */
|
||||
u8 PeerDeviceType; /**< Specifies the device type connected
|
||||
to this port. */
|
||||
u8 PortNum; /**< The port number of this port. */
|
||||
u8 MsgCapStatus; /**< This port or the device at this
|
||||
port can send and receive MST
|
||||
messages. */
|
||||
u8 DpDevPlugStatus; /**< There is a device connected to this
|
||||
port. */
|
||||
|
||||
u8 LegacyDevPlugStatus; /**< This port is connected to a legacy
|
||||
device. */
|
||||
u8 DpcdRev; /**< The DisplayPort Configuration Data
|
||||
(DPCD) revision of the device
|
||||
connected to this port. */
|
||||
u32 Guid[4]; /**< The global unique identifier (GUID)
|
||||
of the device connected to this
|
||||
port. */
|
||||
u8 NumSdpStreams; /**< The total number of Secondary-Data
|
||||
Packet (SDP) streams that this
|
||||
port can handle. */
|
||||
u8 NumSdpStreamSinks; /**< The number of SDP streams
|
||||
associated with this port. */
|
||||
} XDptx_SbMsgLinkAddressReplyPortDetail;
|
||||
|
||||
/**
|
||||
* This typedef describes a DisplayPort branch device. This structure is used
|
||||
* when the driver is operating in multi-stream transport (MST) mode.
|
||||
*/
|
||||
typedef struct {
|
||||
u8 ReplyType; /**< The reply type of the sideband
|
||||
message. A value of 1 indicates
|
||||
that the request wasn't
|
||||
successful and the return data
|
||||
will give the reason for a
|
||||
negative-acknowledge (NACK). */
|
||||
u8 RequestId; /**< The request identifier of the
|
||||
reply. This should correspond to
|
||||
the request identifier for the
|
||||
LINK_ADDRESS sideband message
|
||||
request. */
|
||||
u32 Guid[4]; /**< The global unique identifier (GUID)
|
||||
of the branch device. */
|
||||
u8 NumPorts; /**< The number of ports associated with
|
||||
this branch device. */
|
||||
XDptx_SbMsgLinkAddressReplyPortDetail PortDetails[16]; /**< An array
|
||||
describing all ports attached to
|
||||
this branch device. */
|
||||
} XDptx_SbMsgLinkAddressReplyDeviceInfo;
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* Callback type which represents a custom timer wait handler. This is only
|
||||
* used for Microblaze since it doesn't have a native sleep function. To avoid
|
||||
* dependency on a hardware timer, the default wait functionality is implemented
|
||||
* using loop iterations; this isn't too accurate. If a custom timer handler is
|
||||
* used, the user may implement their own wait implementation using a hardware
|
||||
* timer (see example/) for better accuracy.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param MicroSeconds is the number of microseconds to be passed to the
|
||||
* timer function.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
|
||||
* interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
|
||||
* interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
|
||||
|
||||
/**
|
||||
* The XDptx driver instance data. The user is required to allocate a variable
|
||||
* of this type for every XDptx device in the system. A pointer to a variable of
|
||||
* this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
u32 MstEnable; /**< Multi-stream transport
|
||||
(MST) mode. Enables
|
||||
functionality, allowing
|
||||
multiple streams to be
|
||||
sent over the main
|
||||
link. */
|
||||
u32 IsReady; /**< Device is initialized and
|
||||
ready. */
|
||||
u8 TrainAdaptive; /**< Downshift lane count and
|
||||
link rate if necessary
|
||||
during training. */
|
||||
XDptx_Config Config; /**< Configuration structure for
|
||||
the DisplayPort TX
|
||||
core. */
|
||||
XDptx_SinkConfig RxConfig; /**< Configuration structure for
|
||||
the RX device. */
|
||||
XDptx_LinkConfig LinkConfig; /**< Configuration structure for
|
||||
the main link. */
|
||||
XDptx_BoardChar BoardChar; /**< Some board characteristics
|
||||
information that affects
|
||||
link training. */
|
||||
XDptx_MainStreamAttributes MsaConfig[4]; /**< Configuration structure
|
||||
for the main stream
|
||||
attributes (MSA). Each
|
||||
stream has its own set
|
||||
of attributes. When MST
|
||||
mode is disabled, only
|
||||
MsaConfig[0] is used. */
|
||||
XDptx_MstStream MstStreamConfig[4]; /**< Configuration structure
|
||||
for a multi-stream
|
||||
transport (MST)
|
||||
stream. */
|
||||
XDptx_Topology Topology; /**< The topology of connected
|
||||
downstream DisplayPort
|
||||
devices when the driver
|
||||
is running in MST
|
||||
mode. */
|
||||
u32 AuxDelayUs; /**< Amount of latency in micro-
|
||||
seconds to use between
|
||||
AUX transactions. */
|
||||
u32 SbMsgDelayUs; /**< Amount of latency in micro-
|
||||
seconds to use between
|
||||
sideband messages for
|
||||
multi-stream transport
|
||||
(MST) mode. */
|
||||
XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
|
||||
delay/sleep. */
|
||||
void *UserTimerPtr; /**< Pointer to a timer instance
|
||||
used by the custom user
|
||||
delay/sleep function. */
|
||||
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
|
||||
Plug-Detect (HPD) event
|
||||
interrupts. */
|
||||
void *HpdEventCallbackRef; /**< A pointer to the user data
|
||||
passed to the HPD event
|
||||
callback function. */
|
||||
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
|
||||
Plug-Detect (HPD) pulse
|
||||
interrupts. */
|
||||
void *HpdPulseCallbackRef; /**< A pointer to the user data
|
||||
passed to the HPD pulse
|
||||
callback function. */
|
||||
} XDptx;
|
||||
|
||||
/*************************** Variable Declarations ****************************/
|
||||
|
||||
extern XDptx_DmtMode XDptx_DmtModes[];
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
/* xdptx.c: Setup and initialization functions. */
|
||||
u32 XDptx_InitializeTx(XDptx *InstancePtr);
|
||||
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
|
||||
u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid);
|
||||
|
||||
/* xdptx.c: Link policy maker functions. */
|
||||
u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr);
|
||||
u32 XDptx_EstablishLink(XDptx *InstancePtr);
|
||||
u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount);
|
||||
void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable);
|
||||
void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set);
|
||||
void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset);
|
||||
void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel);
|
||||
void XDptx_CfgTxPeLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel);
|
||||
|
||||
/* xdptx.c: AUX transaction functions. */
|
||||
u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
|
||||
u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
|
||||
u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
|
||||
u8 NumBytes, void *Data);
|
||||
u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
|
||||
u8 NumBytes, void *Data);
|
||||
|
||||
/* xdptx.c: Functions for controlling the link configuration. */
|
||||
u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable);
|
||||
u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable);
|
||||
u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount);
|
||||
u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate);
|
||||
u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable);
|
||||
|
||||
/* xdptx.c: General usage functions. */
|
||||
u32 XDptx_IsConnected(XDptx *InstancePtr);
|
||||
void XDptx_EnableMainLink(XDptx *InstancePtr);
|
||||
void XDptx_DisableMainLink(XDptx *InstancePtr);
|
||||
void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset);
|
||||
void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds);
|
||||
void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
|
||||
XDptx_TimerHandler CallbackFunc, void *CallbackRef);
|
||||
|
||||
/* xdptx_spm.c: Stream policy maker functions. */
|
||||
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream);
|
||||
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream,
|
||||
XDptx_VideoMode VideoMode);
|
||||
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream,
|
||||
u8 *Edid);
|
||||
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
|
||||
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
|
||||
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor);
|
||||
void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable);
|
||||
void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream);
|
||||
void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream);
|
||||
void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream);
|
||||
|
||||
/* xdptx_intr.c: Interrupt handling functions. */
|
||||
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
|
||||
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
|
||||
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
|
||||
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
|
||||
void XDptx_HpdInterruptHandler(XDptx *InstancePtr);
|
||||
|
||||
/* xdptx_selftest.c: Self test function. */
|
||||
u32 XDptx_SelfTest(XDptx *InstancePtr);
|
||||
|
||||
/* xdptx_sinit.c: Configuration extraction function.*/
|
||||
XDptx_Config *XDptx_LookupConfig(u16 DeviceId);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling
|
||||
* MST mode. */
|
||||
void XDptx_MstCfgModeEnable(XDptx *InstancePtr);
|
||||
void XDptx_MstCfgModeDisable(XDptx *InstancePtr);
|
||||
u32 XDptx_MstCapable(XDptx *InstancePtr);
|
||||
u32 XDptx_MstEnable(XDptx *InstancePtr);
|
||||
u32 XDptx_MstDisable(XDptx *InstancePtr);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling
|
||||
* MST streams and selecting their associated target sinks. */
|
||||
void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream);
|
||||
void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream);
|
||||
u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream);
|
||||
void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8
|
||||
SinkNum);
|
||||
void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST topology
|
||||
* discovery. */
|
||||
u32 XDptx_DiscoverTopology(XDptx *InstancePtr);
|
||||
u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST stream
|
||||
* allocation. */
|
||||
u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr);
|
||||
u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u8 VcId, u16 Pbn, u8 Ts);
|
||||
u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) functions for issuing sideband
|
||||
* messages. */
|
||||
u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData);
|
||||
u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData);
|
||||
u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToRead, u8 *ReadData);
|
||||
u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo);
|
||||
u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn);
|
||||
u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u8 VcId, u16 Pbn);
|
||||
u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr);
|
||||
|
||||
/* xdptx_mst.c: Multi-stream transport (MST) utility functions. */
|
||||
void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress,
|
||||
u32 Guid[4]);
|
||||
void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress,
|
||||
u32 *Guid);
|
||||
u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal,
|
||||
u8 *RelativeAddress, u8 *Edid);
|
||||
|
||||
#endif /* XDPTX_H_ */
|
||||
1228
XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
Normal file
1228
XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
Normal file
File diff suppressed because it is too large
Load diff
160
XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
Normal file
160
XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_intr.c
|
||||
*
|
||||
* This file contains functions related to XDptx interrupt handling.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx.h"
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function installs a callback function for when a hot-plug-detect event
|
||||
* interrupt occurs.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param CallbackFunc is the address to the callback function.
|
||||
* @param CallbackRef is the user data item that will be passed to the
|
||||
* callback function when it is invoked.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
|
||||
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
|
||||
{
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(CallbackFunc != NULL);
|
||||
Xil_AssertVoid(CallbackRef != NULL);
|
||||
|
||||
InstancePtr->HpdEventHandler = CallbackFunc;
|
||||
InstancePtr->HpdEventCallbackRef = CallbackRef;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function installs a callback function for when a hot-plug-detect pulse
|
||||
* interrupt occurs.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param CallbackFunc is the address to the callback function.
|
||||
* @param CallbackRef is the user data item that will be passed to the
|
||||
* callback function when it is invoked.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
|
||||
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
|
||||
{
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(CallbackFunc != NULL);
|
||||
Xil_AssertVoid(CallbackRef != NULL);
|
||||
|
||||
InstancePtr->HpdPulseHandler = CallbackFunc;
|
||||
InstancePtr->HpdPulseCallbackRef = CallbackRef;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function is the interrupt handler for the XDptx driver.
|
||||
*
|
||||
* When an interrupt happens, it first detects what kind of interrupt happened,
|
||||
* then decides which callback function to invoke.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
|
||||
{
|
||||
u32 IntrStatus;
|
||||
u8 HpdEventDetected;
|
||||
u8 HpdPulseDetected;
|
||||
u32 HpdDuration;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
/* Determine what kind of interrupt occurred.
|
||||
* Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
|
||||
IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_INTERRUPT_STATUS);
|
||||
IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_INTERRUPT_MASK);
|
||||
|
||||
HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
|
||||
HpdPulseDetected = IntrStatus &
|
||||
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
|
||||
|
||||
if (HpdEventDetected) {
|
||||
InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef);
|
||||
}
|
||||
|
||||
if (HpdPulseDetected) {
|
||||
/* The source device must debounce the incoming HPD signal by
|
||||
* sampling the value at an interval greater than 250 ms. */
|
||||
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XDPTX_HPD_DURATION);
|
||||
if (HpdDuration >= 250) {
|
||||
InstancePtr->HpdPulseHandler(
|
||||
InstancePtr->HpdPulseCallbackRef);
|
||||
}
|
||||
}
|
||||
}
|
||||
2482
XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c
Normal file
2482
XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c
Normal file
File diff suppressed because it is too large
Load diff
212
XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
Normal file
212
XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
Normal file
|
|
@ -0,0 +1,212 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_selftest.c
|
||||
*
|
||||
* This file contains a diagnostic self-test function for the XDptx driver. It
|
||||
* will check many of the DisplayPort TX's register values against the default
|
||||
* reset values as a sanity-check that the core is ready to be used.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/**************************** Variable Definitions ****************************/
|
||||
|
||||
/**
|
||||
* This table contains the default values for the DisplayPort TX core's general
|
||||
* usage registers.
|
||||
*/
|
||||
u32 ResetValues[53][2] =
|
||||
{
|
||||
{XDPTX_LINK_BW_SET, 0},
|
||||
{XDPTX_LANE_COUNT_SET, 0},
|
||||
{XDPTX_ENHANCED_FRAME_EN, 0},
|
||||
{XDPTX_TRAINING_PATTERN_SET, 0},
|
||||
{XDPTX_LINK_QUAL_PATTERN_SET, 0},
|
||||
{XDPTX_SCRAMBLING_DISABLE, 0},
|
||||
{XDPTX_DOWNSPREAD_CTRL, 0},
|
||||
{XDPTX_SOFT_RESET, 0},
|
||||
{XDPTX_ENABLE, 0},
|
||||
{XDPTX_ENABLE_MAIN_STREAM, 0},
|
||||
{XDPTX_ENABLE_SEC_STREAM, 0},
|
||||
{XDPTX_FORCE_SCRAMBLER_RESET, 0},
|
||||
{XDPTX_TX_MST_CONFIG, 0},
|
||||
{XDPTX_AUX_CMD, 0},
|
||||
{XDPTX_AUX_WRITE_FIFO, 0},
|
||||
{XDPTX_AUX_ADDRESS, 0},
|
||||
{XDPTX_AUX_CLK_DIVIDER, 0},
|
||||
{XDPTX_TX_USER_FIFO_OVERFLOW, 0},
|
||||
{XDPTX_AUX_REPLY_DATA, 0},
|
||||
{XDPTX_AUX_REPLY_CODE, 0},
|
||||
{XDPTX_AUX_REPLY_COUNT, 0},
|
||||
{XDPTX_INTERRUPT_MASK, 0x3F},
|
||||
{XDPTX_REPLY_DATA_COUNT, 0},
|
||||
{XDPTX_REPLY_STATUS, 0x10},
|
||||
{XDPTX_STREAM0, 0},
|
||||
{XDPTX_STREAM1, 0},
|
||||
{XDPTX_STREAM2, 0},
|
||||
{XDPTX_STREAM3, 0},
|
||||
{XDPTX_PHY_CONFIG, 0x03},
|
||||
{XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0},
|
||||
{XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0},
|
||||
{XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0},
|
||||
{XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0},
|
||||
{XDPTX_PHY_TRANSMIT_PRBS7, 0},
|
||||
{XDPTX_PHY_CLOCK_SELECT, 0},
|
||||
{XDPTX_TX_PHY_POWER_DOWN, 0},
|
||||
{XDPTX_PHY_PRECURSOR_LANE_0, 0},
|
||||
{XDPTX_PHY_PRECURSOR_LANE_1, 0},
|
||||
{XDPTX_PHY_PRECURSOR_LANE_2, 0},
|
||||
{XDPTX_PHY_PRECURSOR_LANE_3, 0},
|
||||
{XDPTX_PHY_POSTCURSOR_LANE_0, 0},
|
||||
{XDPTX_PHY_POSTCURSOR_LANE_1, 0},
|
||||
{XDPTX_PHY_POSTCURSOR_LANE_2, 0},
|
||||
{XDPTX_PHY_POSTCURSOR_LANE_3, 0},
|
||||
{XDPTX_GT_DRP_COMMAND, 0},
|
||||
{XDPTX_GT_DRP_READ_DATA, 0},
|
||||
{XDPTX_GT_DRP_CHANNEL_STATUS, 0},
|
||||
{XDPTX_TX_AUDIO_CONTROL, 0},
|
||||
{XDPTX_TX_AUDIO_CHANNELS, 0},
|
||||
{XDPTX_TX_AUDIO_INFO_DATA, 0},
|
||||
{XDPTX_TX_AUDIO_MAUD, 0},
|
||||
{XDPTX_TX_AUDIO_NAUD, 0},
|
||||
{XDPTX_TX_AUDIO_EXT_DATA, 0}
|
||||
};
|
||||
|
||||
/**
|
||||
* This table contains the default values for the DisplayPort TX core's main
|
||||
* stream attribute (MSA) registers.
|
||||
*/
|
||||
u32 ResetValuesMsa[20][2] =
|
||||
{
|
||||
{XDPTX_MAIN_STREAM_HTOTAL, 0},
|
||||
{XDPTX_MAIN_STREAM_VTOTAL, 0},
|
||||
{XDPTX_MAIN_STREAM_POLARITY, 0},
|
||||
{XDPTX_MAIN_STREAM_HSWIDTH, 0},
|
||||
{XDPTX_MAIN_STREAM_VSWIDTH, 0},
|
||||
{XDPTX_MAIN_STREAM_HRES, 0},
|
||||
{XDPTX_MAIN_STREAM_VRES, 0},
|
||||
{XDPTX_MAIN_STREAM_HSTART, 0},
|
||||
{XDPTX_MAIN_STREAM_VSTART, 0},
|
||||
{XDPTX_MAIN_STREAM_MISC0, 0},
|
||||
{XDPTX_MAIN_STREAM_MISC1, 0},
|
||||
{XDPTX_M_VID, 0},
|
||||
{XDPTX_TU_SIZE, 0},
|
||||
{XDPTX_N_VID, 0},
|
||||
{XDPTX_USER_PIXEL_WIDTH, 0},
|
||||
{XDPTX_USER_DATA_COUNT_PER_LANE, 0},
|
||||
{XDPTX_MAIN_STREAM_INTERLACED, 0},
|
||||
{XDPTX_MIN_BYTES_PER_TU, 0},
|
||||
{XDPTX_FRAC_BYTES_PER_TU, 0},
|
||||
{XDPTX_INIT_WAIT, 32}
|
||||
};
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function runs a self-test on the XDptx driver/device. The sanity test
|
||||
* checks whether or not all tested registers hold their default reset values.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the self-test passed - all tested registers
|
||||
* hold their default reset values.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
u32 XDptx_SelfTest(XDptx *InstancePtr)
|
||||
{
|
||||
u8 Index;
|
||||
u8 StreamIndex;
|
||||
u32 StreamOffset;
|
||||
u32 Val;
|
||||
|
||||
/* Compare general usage registers with their default values. */
|
||||
for (Index = 0; Index < 53; Index++) {
|
||||
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
ResetValues[Index][0]);
|
||||
/* Fail if register does not hold default value. */
|
||||
if (Val != ResetValues[Index][1]) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Compare main stream attribute (MSA) registers for all 4 streams with
|
||||
* their default values. */
|
||||
for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
|
||||
/* Determine the MSA register offset for each stream. */
|
||||
if (StreamIndex == 0) {
|
||||
StreamOffset = 0;
|
||||
}
|
||||
else if (StreamIndex == 1) {
|
||||
StreamOffset = XDPTX_STREAM1_MSA_START_OFFSET;
|
||||
}
|
||||
else if (StreamIndex == 2) {
|
||||
StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
|
||||
}
|
||||
else if (StreamIndex == 3) {
|
||||
StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
|
||||
}
|
||||
|
||||
for (Index = 0; Index < 20; Index++) {
|
||||
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
StreamOffset + ResetValuesMsa[Index][0]);
|
||||
/* Fail if register does not hold default value. */
|
||||
if (Val != ResetValuesMsa[Index][1]) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* All tested registers hold their default reset values. */
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
93
XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
Normal file
93
XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_sinit.c
|
||||
*
|
||||
* This file contains static initialization methods for the XDptx driver.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/*************************** Variable Declarations ****************************/
|
||||
|
||||
/**
|
||||
* A table of configuration structures containing the configuration information
|
||||
* for each DisplayPort TX core in the system.
|
||||
*/
|
||||
extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function looks for the device configuration based on the unique device
|
||||
* ID. The table XDptx_ConfigTable[] contains the configuration information for
|
||||
* each device in the system.
|
||||
*
|
||||
* @param DeviceId is the unique device ID of the device being looked up.
|
||||
*
|
||||
* @return A pointer to the configuration table entry corresponding to the
|
||||
* given device ID, or NULL if no match is found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
XDptx_Config *XDptx_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XDptx_Config *CfgPtr;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {
|
||||
if (XDptx_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XDptx_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return CfgPtr;
|
||||
}
|
||||
834
XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
Normal file
834
XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
Normal file
|
|
@ -0,0 +1,834 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_spm.c
|
||||
*
|
||||
* This file contains the stream policy maker functions for the XDptx driver.
|
||||
* These functions set up the DisplayPort TX core's main stream attributes that
|
||||
* determine how a video stream will be displayed.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* als 08/03/14 Initial MST addition.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xdptx.h"
|
||||
#include "xdptx_hw.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/**************************** Function Prototypes *****************************/
|
||||
|
||||
static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel);
|
||||
|
||||
/**************************** Function Definitions ****************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function calculates the following Main Stream Attributes (MSA):
|
||||
* - Transfer unit size
|
||||
* - User pixel width
|
||||
* - Horizontal start
|
||||
* - Vertical start
|
||||
* - Horizontal total clock
|
||||
* - Vertical total clock
|
||||
* - Misc0
|
||||
* - Misc1
|
||||
* - Data per lane
|
||||
* - Average number of bytes per transfer unit
|
||||
* - Number of initial wait cycles
|
||||
* These values are derived from:
|
||||
* - Bits per color
|
||||
* - Horizontal resolution
|
||||
* - Vertical resolution
|
||||
* - Pixel clock (in KHz)
|
||||
* - Horizontal sync polarity
|
||||
* - Vertical sync polarity
|
||||
* - Horizontal front porch
|
||||
* - Horizontal sync pulse width
|
||||
* - Horizontal back porch
|
||||
* - Vertical front porch
|
||||
* - Vertical sync pulse width
|
||||
* - Vertical back porch
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number for which to calculate the MSA
|
||||
* values.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The MsaConfig structure is modified with the new, calculated
|
||||
* values. The main stream attributes that were used to derive the
|
||||
* calculated values are untouched in the MsaConfig structure.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream)
|
||||
{
|
||||
u32 VideoBw;
|
||||
u8 BitsPerPixel;
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
XDptx_LinkConfig *LinkConfig;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
LinkConfig = &InstancePtr->LinkConfig;
|
||||
|
||||
/* Verify the rest of the values used. */
|
||||
Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
|
||||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
|
||||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
|
||||
Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
|
||||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
|
||||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
|
||||
Xil_AssertVoid((MsaConfig->SynchronousClockMode == 0) ||
|
||||
(MsaConfig->SynchronousClockMode == 1));
|
||||
Xil_AssertVoid((MsaConfig->DynamicRange == 0) ||
|
||||
(MsaConfig->DynamicRange == 1));
|
||||
Xil_AssertVoid((MsaConfig->YCbCrColorimetry == 0) ||
|
||||
(MsaConfig->YCbCrColorimetry == 1));
|
||||
Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
|
||||
(MsaConfig->BitsPerColor == 8) ||
|
||||
(MsaConfig->BitsPerColor == 10) ||
|
||||
(MsaConfig->BitsPerColor == 12) ||
|
||||
(MsaConfig->BitsPerColor == 16));
|
||||
|
||||
/* Set the user pixel width to handle clocks that exceed the
|
||||
* capabilities of the DisplayPort TX core. */
|
||||
if (MsaConfig->OverrideUserPixelWidth == 0) {
|
||||
if ((MsaConfig->Dmt.PixelClkKhz > 300000) &&
|
||||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
|
||||
MsaConfig->UserPixelWidth = 4;
|
||||
}
|
||||
else if ((MsaConfig->Dmt.PixelClkKhz > 75000) &&
|
||||
(LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
|
||||
MsaConfig->UserPixelWidth = 2;
|
||||
}
|
||||
else {
|
||||
MsaConfig->UserPixelWidth = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Compute the rest of the MSA values. */
|
||||
MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
|
||||
MsaConfig->HStart = MsaConfig->Dmt.HSyncPulseWidth +
|
||||
MsaConfig->Dmt.HBackPorch;
|
||||
MsaConfig->VStart = MsaConfig->Dmt.VSyncPulseWidth +
|
||||
MsaConfig->Dmt.VBackPorch;
|
||||
MsaConfig->HClkTotal = (MsaConfig->Dmt.HSyncPulseWidth +
|
||||
MsaConfig->Dmt.HBackPorch +
|
||||
MsaConfig->Dmt.HFrontPorch +
|
||||
MsaConfig->Dmt.HResolution);
|
||||
MsaConfig->VClkTotal = (MsaConfig->Dmt.VSyncPulseWidth +
|
||||
MsaConfig->Dmt.VBackPorch +
|
||||
MsaConfig->Dmt.VFrontPorch +
|
||||
MsaConfig->Dmt.VResolution);
|
||||
|
||||
/* Miscellaneous attributes. */
|
||||
if (MsaConfig->BitsPerColor == 6) {
|
||||
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
|
||||
}
|
||||
else if (MsaConfig->BitsPerColor == 8) {
|
||||
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
|
||||
}
|
||||
else if (MsaConfig->BitsPerColor == 10) {
|
||||
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
|
||||
}
|
||||
else if (MsaConfig->BitsPerColor == 12) {
|
||||
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
|
||||
}
|
||||
else if (MsaConfig->BitsPerColor == 16) {
|
||||
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
|
||||
}
|
||||
MsaConfig->Misc0 = (MsaConfig->Misc0 <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
|
||||
(MsaConfig->YCbCrColorimetry <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
|
||||
(MsaConfig->DynamicRange <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
|
||||
(MsaConfig->ComponentFormat <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
|
||||
(MsaConfig->SynchronousClockMode);
|
||||
MsaConfig->Misc1 = 0;
|
||||
|
||||
/* Determine the number of bits per pixel for the specified color
|
||||
* component format. */
|
||||
if (MsaConfig->ComponentFormat ==
|
||||
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
|
||||
/* YCbCr422 color component format. */
|
||||
BitsPerPixel = MsaConfig->BitsPerColor * 2;
|
||||
}
|
||||
else {
|
||||
/* RGB or YCbCr 4:4:4 color component format. */
|
||||
BitsPerPixel = MsaConfig->BitsPerColor * 3;
|
||||
}
|
||||
|
||||
|
||||
if (InstancePtr->MstEnable == 1) {
|
||||
MsaConfig->DataPerLane = (MsaConfig->Dmt.HResolution *
|
||||
MsaConfig->BitsPerColor * 3 / 16) - 4;
|
||||
|
||||
/* Do time slot (and payload bandwidth number) calculations for
|
||||
* MST. */
|
||||
XDptx_CalculateTs(InstancePtr, Stream, BitsPerPixel);
|
||||
|
||||
MsaConfig->InitWait = 0;
|
||||
}
|
||||
else {
|
||||
MsaConfig->DataPerLane = (MsaConfig->Dmt.HResolution *
|
||||
MsaConfig->BitsPerColor * 3 / 16) -
|
||||
LinkConfig->LaneCount;
|
||||
|
||||
/* Allocate a fixed size for single-stream transport (SST)
|
||||
* operation. */
|
||||
MsaConfig->TransferUnitSize = 64;
|
||||
|
||||
/* Calculate the average number of bytes per transfer unit.
|
||||
* Note: Both the integer and the fractional part is stored in
|
||||
* AvgBytesPerTU. */
|
||||
VideoBw = (MsaConfig->Dmt.PixelClkKhz * BitsPerPixel) / 8;
|
||||
MsaConfig->AvgBytesPerTU = (VideoBw *
|
||||
MsaConfig->TransferUnitSize) /
|
||||
(LinkConfig->LaneCount *
|
||||
(MsaConfig->NVid / 1000));
|
||||
|
||||
/* The number of initial wait cycles at the start of a new line
|
||||
* by the framing logic. This allows enough data to be buffered
|
||||
* in the input FIFO before video is sent. */
|
||||
MsaConfig->InitWait = (MsaConfig->TransferUnitSize -
|
||||
(MsaConfig->AvgBytesPerTU / 1000));
|
||||
if ((MsaConfig->AvgBytesPerTU / 1000) >
|
||||
MsaConfig->TransferUnitSize) {
|
||||
MsaConfig->InitWait = 0;
|
||||
}
|
||||
else if (MsaConfig->InitWait > 10) {
|
||||
MsaConfig->InitWait -= 10;
|
||||
}
|
||||
else {
|
||||
MsaConfig->InitWait = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function sets the Main Stream Attribute (MSA) values in the
|
||||
* configuration structure to match one of the standard display mode timings
|
||||
* from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The
|
||||
* XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number for which the MSA values will be
|
||||
* used for.
|
||||
* @param VideoMode is one of the enumerated standard video modes that is
|
||||
* used to determine the MSA values to be used.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The InstancePtr->MsaConfig structure is modified to reflect the
|
||||
* MSA values associated to the specified video mode.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream,
|
||||
XDptx_VideoMode VideoMode)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Configure the MSA values from the display monitor DMT table. */
|
||||
MsaConfig->Dmt.HResolution = XDptx_DmtModes[VideoMode].HResolution;
|
||||
MsaConfig->Dmt.VResolution = XDptx_DmtModes[VideoMode].VResolution;
|
||||
MsaConfig->Dmt.PixelClkKhz = XDptx_DmtModes[VideoMode].PixelClkKhz;
|
||||
MsaConfig->Dmt.HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
|
||||
MsaConfig->Dmt.VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
|
||||
MsaConfig->Dmt.HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch;
|
||||
MsaConfig->Dmt.HSyncPulseWidth =
|
||||
XDptx_DmtModes[VideoMode].HSyncPulseWidth;
|
||||
MsaConfig->Dmt.HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch;
|
||||
MsaConfig->Dmt.VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch;
|
||||
MsaConfig->Dmt.VSyncPulseWidth =
|
||||
XDptx_DmtModes[VideoMode].VSyncPulseWidth;
|
||||
MsaConfig->Dmt.VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch;
|
||||
|
||||
/* Calculate the rest of the MSA values. */
|
||||
XDptx_CfgMsaRecalculate(InstancePtr, Stream);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function sets the main stream attribute values in the configuration
|
||||
* structure to match the preferred timing of the sink monitor. This Preferred
|
||||
* Timing Mode (PTM) information is stored in the sink's Extended Display
|
||||
* Identification Data (EDID).
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance
|
||||
* @param Stream is the stream number for which the MSA values will be
|
||||
* used for.
|
||||
* @param Edid is a pointer to the Edid to use for the specified stream.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The InstancePtr->MsaConfig structure is modified to reflect the
|
||||
* main stream attribute values associated to the preferred timing
|
||||
* of the sink monitor.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
u8 *Ptm;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid(Edid != NULL);
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
Ptm = &Edid[XDPTX_EDID_PTM];
|
||||
|
||||
/* Configure the MSA values with the PTM information as
|
||||
* specified by the preferred Detailed Timing Descriptor (DTD) of the
|
||||
* monitor's EDID.
|
||||
* Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
|
||||
* versions may not contain this information. */
|
||||
u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_HBLANK_LSB];
|
||||
|
||||
u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_VBLANK_LSB];
|
||||
|
||||
MsaConfig->Dmt.HResolution =
|
||||
(((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_HRES_LSB];
|
||||
|
||||
MsaConfig->Dmt.VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
|
||||
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_VRES_LSB];
|
||||
|
||||
MsaConfig->Dmt.PixelClkKhz = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] <<
|
||||
8) | Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10;
|
||||
|
||||
MsaConfig->Dmt.HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_HFPORCH_LSB];
|
||||
|
||||
MsaConfig->Dmt.HSyncPulseWidth =
|
||||
(((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
|
||||
Ptm[XDPTX_EDID_DTD_HSPW_LSB];
|
||||
|
||||
MsaConfig->Dmt.VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
|
||||
((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
|
||||
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
|
||||
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
|
||||
|
||||
MsaConfig->Dmt.VSyncPulseWidth =
|
||||
((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
|
||||
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
|
||||
(Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
|
||||
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
|
||||
|
||||
MsaConfig->Dmt.HBackPorch = HBlank - (MsaConfig->Dmt.HFrontPorch +
|
||||
MsaConfig->Dmt.HSyncPulseWidth);
|
||||
|
||||
MsaConfig->Dmt.VBackPorch = VBlank - (MsaConfig->Dmt.VFrontPorch +
|
||||
MsaConfig->Dmt.VSyncPulseWidth);
|
||||
|
||||
/* Calculate the rest of the MSA values. */
|
||||
XDptx_CfgMsaRecalculate(InstancePtr, Stream);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function takes a the main stream attributes from MsaConfigCustom and
|
||||
* copies them into InstancePtr->MsaConfig. If desired, given a base set of
|
||||
* attributes, the rest of the attributes may be derived. The minimal required
|
||||
* main stream attributes (MSA) that must be contained in the MsaConfigCustom
|
||||
* structure are:
|
||||
* - Pixel clock (in KHz)
|
||||
* - Horizontal sync polarity
|
||||
* - Vertical sync polarity
|
||||
* - Horizontal sync pulse width
|
||||
* - Vertical sync pulse width
|
||||
* - Horizontal resolution
|
||||
* - Vertical resolution
|
||||
* - Vertical back porch
|
||||
* - Vertical front porch
|
||||
* - Horizontal back porch
|
||||
* - Horizontal front porch
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number for which the MSA values will be
|
||||
* used for.
|
||||
* @param MsaConfigCustom is the structure that will be used to copy the
|
||||
* main stream attributes from (into InstancePtr->MsaConfig).
|
||||
* @param Recalculate is a boolean enable that determines whether or not
|
||||
* the main stream attributes should be recalculated.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The InstancePtr->MsaConfig structure is modified with the new
|
||||
* values.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
|
||||
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid(MsaConfigCustom != NULL);
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Copy the MSA values from the user configuration structure. */
|
||||
MsaConfig->Dmt.HResolution = MsaConfigCustom->Dmt.HResolution;
|
||||
MsaConfig->Dmt.VResolution = MsaConfigCustom->Dmt.VResolution;
|
||||
MsaConfig->Dmt.PixelClkKhz = MsaConfigCustom->Dmt.PixelClkKhz;
|
||||
MsaConfig->Dmt.HSyncPolarity = MsaConfigCustom->Dmt.HSyncPolarity;
|
||||
MsaConfig->Dmt.VSyncPolarity = MsaConfigCustom->Dmt.VSyncPolarity;
|
||||
MsaConfig->Dmt.HFrontPorch = MsaConfigCustom->Dmt.HFrontPorch;
|
||||
MsaConfig->Dmt.HSyncPulseWidth = MsaConfigCustom->Dmt.HSyncPulseWidth;
|
||||
MsaConfig->Dmt.HBackPorch = MsaConfigCustom->Dmt.HBackPorch;
|
||||
MsaConfig->Dmt.VFrontPorch = MsaConfigCustom->Dmt.VFrontPorch;
|
||||
MsaConfig->Dmt.VSyncPulseWidth = MsaConfigCustom->Dmt.VSyncPulseWidth;
|
||||
MsaConfig->Dmt.VBackPorch = MsaConfigCustom->Dmt.VBackPorch;
|
||||
|
||||
if (Recalculate) {
|
||||
/* Calculate the rest of the MSA values. */
|
||||
XDptx_CfgMsaRecalculate(InstancePtr, Stream);
|
||||
}
|
||||
else {
|
||||
/* Use the custom values for the rest. */
|
||||
MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize;
|
||||
MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth;
|
||||
MsaConfig->NVid = MsaConfigCustom->NVid;
|
||||
MsaConfig->HStart = MsaConfigCustom->HStart;
|
||||
MsaConfig->VStart = MsaConfigCustom->VStart;
|
||||
MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
|
||||
MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
|
||||
MsaConfig->Misc0 = MsaConfigCustom->Misc0;
|
||||
MsaConfig->Misc1 = MsaConfigCustom->Misc1;
|
||||
MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
|
||||
MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU;
|
||||
MsaConfig->InitWait = MsaConfigCustom->InitWait;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function sets the bits per color value of the video stream.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance
|
||||
* @param Stream is the stream number for which to set the color depth.
|
||||
* @param BitsPerColor is the new number of bits per color to use.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note The InstancePtr->MsaConfig structure is modified to reflect the
|
||||
* new main stream attributes associated with a new bits per color
|
||||
* value.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor)
|
||||
{
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
|
||||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
|
||||
(BitsPerColor == 16));
|
||||
|
||||
InstancePtr->MsaConfig[Stream].BitsPerColor = BitsPerColor;
|
||||
|
||||
/* Calculate the rest of the MSA values. */
|
||||
XDptx_CfgMsaRecalculate(InstancePtr, Stream);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function enables or disables synchronous clock mode for a video stream.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance
|
||||
* @param Stream is the stream number for which to enable or disable
|
||||
* synchronous clock mode.
|
||||
* @param Enable if set to 1, will enable synchronous clock mode.
|
||||
* Otherwise, if set to 0, synchronous clock mode will be disabled.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
Xil_AssertVoid((Enable == 0) || (Enable == 1));
|
||||
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
MsaConfig->SynchronousClockMode = Enable;
|
||||
|
||||
if (Enable == 1) {
|
||||
MsaConfig->Misc0 |= (1 <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT);
|
||||
}
|
||||
else {
|
||||
MsaConfig->Misc0 &= ~(1 <<
|
||||
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function clears the main stream attributes registers of the DisplayPort
|
||||
* TX core and sets them to the values specified in the main stream attributes
|
||||
* configuration structure.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance
|
||||
* @param Stream is the stream number for which to set the MSA values for.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream)
|
||||
{
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
XDptx_ClearMsaValues(InstancePtr, Stream);
|
||||
XDptx_SetMsaValues(InstancePtr, Stream);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function clears the main stream attributes registers of the DisplayPort
|
||||
* TX core.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number for which to clear the MSA values.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream)
|
||||
{
|
||||
XDptx_Config *Config;
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET,
|
||||
XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET};
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
Config = &InstancePtr->Config;
|
||||
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID +
|
||||
StreamOffset[Stream], 0);
|
||||
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream) * 4, 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU +
|
||||
StreamOffset[Stream], 0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT +
|
||||
StreamOffset[Stream], 0);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* This function sets the main stream attributes registers of the DisplayPort TX
|
||||
* core with the values specified in the main stream attributes configuration
|
||||
* structure.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number for which to set the MSA values for.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream)
|
||||
{
|
||||
XDptx_Config *Config;
|
||||
XDptx_MainStreamAttributes *MsaConfig;
|
||||
u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET,
|
||||
XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET};
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) ||
|
||||
(Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) ||
|
||||
(Stream == XDPTX_STREAM_ID3));
|
||||
|
||||
Config = &InstancePtr->Config;
|
||||
MsaConfig = &InstancePtr->MsaConfig[Stream];
|
||||
|
||||
/* Set the main stream attributes to the associated DisplayPort TX core
|
||||
* registers. */
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL +
|
||||
StreamOffset[Stream], MsaConfig->HClkTotal);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL +
|
||||
StreamOffset[Stream], MsaConfig->VClkTotal);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HSyncPolarity |
|
||||
(MsaConfig->Dmt.VSyncPolarity <<
|
||||
XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HSyncPulseWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.VSyncPulseWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.HResolution);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.VResolution);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART +
|
||||
StreamOffset[Stream], MsaConfig->HStart);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART +
|
||||
StreamOffset[Stream], MsaConfig->VStart);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 +
|
||||
StreamOffset[Stream], MsaConfig->Misc0);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 +
|
||||
StreamOffset[Stream], MsaConfig->Misc1);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID +
|
||||
StreamOffset[Stream], MsaConfig->Dmt.PixelClkKhz);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID +
|
||||
StreamOffset[Stream], MsaConfig->NVid);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH +
|
||||
StreamOffset[Stream], MsaConfig->UserPixelWidth);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE +
|
||||
StreamOffset[Stream], MsaConfig->DataPerLane);
|
||||
|
||||
/* Set the transfer unit values to the associated DisplayPort TX core
|
||||
* registers. */
|
||||
if (InstancePtr->MstEnable == 1) {
|
||||
XDptx_WriteReg(Config->BaseAddr,
|
||||
XDPTX_STREAM0 + (Stream) * 4,
|
||||
((MsaConfig->AvgBytesPerTU / 1000) << 16) |
|
||||
(MsaConfig->AvgBytesPerTU % 1000));
|
||||
}
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE +
|
||||
StreamOffset[Stream], MsaConfig->TransferUnitSize);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU +
|
||||
StreamOffset[Stream], MsaConfig->AvgBytesPerTU / 1000);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU +
|
||||
StreamOffset[Stream], MsaConfig->AvgBytesPerTU % 1000);
|
||||
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT +
|
||||
StreamOffset[Stream], MsaConfig->InitWait);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* When the driver is in multi-stream transport (MST) mode, this function will
|
||||
* make the necessary calculations to describe a stream in MST mode. The key
|
||||
* values are the payload bandwidth number (PBN), the number of timeslots
|
||||
* required for allocating the bandwidth, and the average bytes per transfer
|
||||
* unit (both the integer and the fractional part).
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XDptx instance.
|
||||
* @param Stream is the stream number to make the calculations for.
|
||||
* @param BitsPerPixel is the number of bits that is used to store one
|
||||
* pixel.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel)
|
||||
{
|
||||
XDptx_MainStreamAttributes *MsaConfig =
|
||||
&InstancePtr->MsaConfig[Stream];
|
||||
XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
|
||||
double PeakPixelBw;
|
||||
u32 LinkBw;
|
||||
double Average_StreamSymbolTimeSlotsPerMTP;
|
||||
double Target_Average_StreamSymbolTimeSlotsPerMTP;
|
||||
double MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP;
|
||||
u32 TsInt;
|
||||
u32 TsFrac;
|
||||
|
||||
PeakPixelBw = ((double)MsaConfig->Dmt.PixelClkKhz / 1000) *
|
||||
((double)BitsPerPixel / 8);
|
||||
LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27);
|
||||
|
||||
/* Calculate the payload bandiwdth number (PBN). */
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn =
|
||||
1.006 * PeakPixelBw * ((double)64 / 54);
|
||||
/* Ceil - round up if required, avoiding overhead of math.h. */
|
||||
if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) >
|
||||
((double)InstancePtr->MstStreamConfig[Stream].MstPbn)) {
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn++;
|
||||
}
|
||||
|
||||
/* Calculate the average stream symbol time slots per MTP. */
|
||||
Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw);
|
||||
MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 *
|
||||
((double)InstancePtr->MstStreamConfig[Stream].MstPbn /
|
||||
LinkBw));
|
||||
|
||||
/* The target value to be found needs to follow the condition:
|
||||
* Average_StreamSymbolTimeSlotsPerMTP <=
|
||||
* Target_Average_StreamSymbolTimeSlotsPerMTP
|
||||
* >= MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP
|
||||
* Obtain the greatest target value that satisfies the above condition
|
||||
* and still a multiple of 1/TsFrac_Denominator.
|
||||
* Note: TsFrac_Denominator = 8. */
|
||||
/* Round down. */
|
||||
Target_Average_StreamSymbolTimeSlotsPerMTP =
|
||||
(u32)Average_StreamSymbolTimeSlotsPerMTP;
|
||||
/* Find the greatest multiple that is less than the maximum. */
|
||||
Target_Average_StreamSymbolTimeSlotsPerMTP += ((1.0 / 8.0) * (u32)(8.0 *
|
||||
(MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP -
|
||||
Target_Average_StreamSymbolTimeSlotsPerMTP)));
|
||||
|
||||
/* Determine the integer and the fractional part of the number of time
|
||||
* slots that will be allocated for the stream. */
|
||||
TsInt = Target_Average_StreamSymbolTimeSlotsPerMTP;
|
||||
TsFrac = (((double)Target_Average_StreamSymbolTimeSlotsPerMTP * 1000) -
|
||||
(TsInt * 1000));
|
||||
|
||||
/* Store TsInt and TsFrac in AvgBytesPerTU. */
|
||||
MsaConfig->AvgBytesPerTU = TsInt * 1000 + TsFrac;
|
||||
|
||||
/* Set the number of time slots to allocate for this stream. */
|
||||
MsaConfig->TransferUnitSize = TsInt;
|
||||
if (TsFrac != 0) {
|
||||
/* Round up. */
|
||||
MsaConfig->TransferUnitSize++;
|
||||
}
|
||||
if ((InstancePtr->Config.PayloadDataWidth == 4) &&
|
||||
(MsaConfig->TransferUnitSize % 4) != 0) {
|
||||
/* Set to a multiple of 4 boundary. */
|
||||
MsaConfig->TransferUnitSize += (4 -
|
||||
(MsaConfig->TransferUnitSize % 4));
|
||||
}
|
||||
else if ((MsaConfig->TransferUnitSize % 2) != 0) {
|
||||
/* Set to an even boundary. */
|
||||
MsaConfig->TransferUnitSize++;
|
||||
}
|
||||
|
||||
/* Determine the PBN for the stream. */
|
||||
InstancePtr->MstStreamConfig[Stream].MstPbn =
|
||||
MsaConfig->TransferUnitSize *
|
||||
(LinkConfig->LaneCount * LinkConfig->LinkRate / 2);
|
||||
}
|
||||
250
XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
Normal file
250
XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
Normal file
|
|
@ -0,0 +1,250 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdptx_vidmodetable.c
|
||||
*
|
||||
* Contains display monitor timing (DMT) modes for various standard resolutions.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.0 als 05/17/14 Initial release.
|
||||
* </pre>
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xdptx.h"
|
||||
|
||||
/**************************** Variable Definitions ****************************/
|
||||
|
||||
/**
|
||||
* This table contains the main stream attributes for various standard
|
||||
* resolutions. Each entry is of the format:
|
||||
* 1) XDPTX_VM_<HRES>x<VRES>_<REFRESH (HZ)>_P(_RB = Reduced Blanking)
|
||||
* 2) Display Monitor Timing (DMT) ID
|
||||
* 3) Horizontal resolution (pixels)
|
||||
* 4) Vertical resolution (lines)
|
||||
* 5) Pixel clock (KHz)
|
||||
* 6) Interlaced (0=non-interlaced|1=interlaced)
|
||||
* 7) Horizontal sync polarity (0=positive|1=negative)
|
||||
* 8) Vertical sync polarity (0=positive|1=negative)
|
||||
* 9) Horizontal front porch (pixels)
|
||||
* 10) Horizontal sync time (pixels)
|
||||
* 11) Horizontal back porch (pixels)
|
||||
* 12) Vertical front porch (lines)
|
||||
* 13) Vertical sync time (lines)
|
||||
* 14) Vertical back porch (lines)
|
||||
*/
|
||||
XDptx_DmtMode XDptx_DmtModes[] =
|
||||
{
|
||||
{XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175,
|
||||
0, 1, 1, 8, 96, 40, 2, 2, 25},
|
||||
{XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000,
|
||||
0, 0, 0, 40, 128, 88, 1, 4, 23},
|
||||
{XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750,
|
||||
0, 0, 0, 16, 112, 112, 6, 8, 23},
|
||||
{XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000,
|
||||
0, 1, 1, 24, 136, 160, 3, 6, 29},
|
||||
{XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250,
|
||||
0, 0, 1, 48, 32, 80, 3, 7, 12},
|
||||
{XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500,
|
||||
0, 1, 0, 64, 128, 192, 3, 7, 20},
|
||||
{XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 14},
|
||||
{XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500,
|
||||
0, 1, 0, 72, 128, 200, 3, 6, 22},
|
||||
{XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000,
|
||||
0, 0, 0, 96, 112, 312, 1, 3, 36},
|
||||
{XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000,
|
||||
0, 0, 0, 48, 112, 248, 1, 3, 38},
|
||||
{XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500,
|
||||
0, 0, 0, 64, 112, 256, 3, 6, 18},
|
||||
{XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 23},
|
||||
{XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750,
|
||||
0, 1, 0, 88, 144, 232, 3, 4, 32},
|
||||
{XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 17},
|
||||
{XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500,
|
||||
0, 1, 0, 80, 152, 232, 3, 6, 25},
|
||||
{XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000,
|
||||
0, 0, 0, 64, 192, 304, 1, 3, 46},
|
||||
{XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000,
|
||||
0, 1, 0, 48, 32, 80, 3, 6, 21},
|
||||
{XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250,
|
||||
0, 1, 0, 104, 176, 280, 3, 6, 30},
|
||||
{XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750,
|
||||
0, 1, 0, 128, 200, 328, 1, 3, 46},
|
||||
{XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250,
|
||||
0, 1, 0, 96, 224, 352, 1, 3, 43},
|
||||
{XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 26},
|
||||
{XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250,
|
||||
0, 1, 0, 136, 200, 336, 3, 6, 36},
|
||||
{XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000,
|
||||
0, 1, 0, 128, 208, 344, 1, 3, 56},
|
||||
{XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 37},
|
||||
{XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500,
|
||||
0, 1, 0, 192, 280, 472, 3, 6, 49},
|
||||
{XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000,
|
||||
0, 0, 0, 24, 72, 128, 1, 2, 22},
|
||||
{XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500,
|
||||
0, 0, 0, 64, 192, 304, 1, 3, 46},
|
||||
{XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000,
|
||||
0, 0, 0, 64, 192, 304, 1, 3, 46},
|
||||
{XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000,
|
||||
0, 1, 1, 24, 136, 144, 3, 6, 29},
|
||||
{XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500,
|
||||
0, 1, 1, 16, 40, 120, 1, 3, 20},
|
||||
{XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000,
|
||||
0, 0, 0, 56, 120, 64, 37, 6, 23},
|
||||
{XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500,
|
||||
0, 1, 1, 16, 64, 120, 1, 3, 16},
|
||||
{XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500,
|
||||
0, 0, 0, 16, 80, 160, 1, 3, 21},
|
||||
{XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750,
|
||||
0, 0, 0, 16, 96, 176, 1, 3, 28},
|
||||
{XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000,
|
||||
0, 0, 0, 64, 128, 256, 1, 3, 32},
|
||||
{XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250,
|
||||
0, 1, 0, 80, 128, 208, 3, 7, 27},
|
||||
{XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500,
|
||||
0, 1, 0, 80, 128, 208, 3, 6, 29},
|
||||
{XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000,
|
||||
0, 0, 0, 16, 144, 248, 1, 3, 38},
|
||||
{XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000,
|
||||
0, 1, 0, 104, 144, 248, 3, 4, 42},
|
||||
{XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750,
|
||||
0, 1, 0, 96, 152, 31, 3, 6, 33},
|
||||
{XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500,
|
||||
0, 0, 0, 64, 192, 304, 1, 3, 46},
|
||||
{XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000,
|
||||
0, 1, 0, 120, 176, 37, 3, 6, 40},
|
||||
{XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000,
|
||||
0, 1, 0, 96, 216, 352, 1, 3, 69},
|
||||
{XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000,
|
||||
0, 1, 0, 128, 224, 352, 1, 3, 104},
|
||||
{XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250,
|
||||
0, 1, 0, 136, 208, 344, 3, 6, 46},
|
||||
{XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000,
|
||||
0, 1, 0, 144, 224, 352, 1, 3, 56},
|
||||
{XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250,
|
||||
0, 1, 0, 208, 280, 488, 3, 6, 63},
|
||||
{XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500,
|
||||
0, 0, 1, 32, 64, 96, 32, 3, 60},
|
||||
{XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500,
|
||||
0, 1, 0, 32, 64, 96, 1, 3, 41},
|
||||
{XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500,
|
||||
0, 1, 0, 36, 72, 108, 1, 3, 42},
|
||||
{XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000,
|
||||
0, 1, 1, 56, 56, 80, 1, 3, 25},
|
||||
{XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250,
|
||||
0, 0, 0, 32, 64, 152, 1, 3, 27},
|
||||
{XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500,
|
||||
0, 0, 0, 48, 96, 208, 1, 3, 36},
|
||||
{XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500,
|
||||
0, 1, 0, 80, 136, 216, 3, 7, 31},
|
||||
{XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500,
|
||||
0, 1, 0, 80, 136, 216, 3, 6, 34},
|
||||
{XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500,
|
||||
0, 0, 0, 64, 160, 224, 1, 3, 47},
|
||||
{XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500,
|
||||
0, 0, 0, 64, 160, 224, 1, 3, 44},
|
||||
{XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500,
|
||||
0, 1, 0, 104, 152, 256, 3, 4, 48},
|
||||
{XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000,
|
||||
0, 1, 0, 104, 152, 32, 3, 6, 39},
|
||||
{XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500,
|
||||
0, 0, 0, 64, 192, 304, 1, 3, 46},
|
||||
{XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750,
|
||||
0, 1, 0, 128, 176, 304, 3, 6, 46},
|
||||
{XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250,
|
||||
0, 1, 0, 144, 208, 352, 3, 6, 53},
|
||||
{XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250,
|
||||
0, 1, 0, 208, 280, 488, 3, 6, 73},
|
||||
{XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 29},
|
||||
{XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 38},
|
||||
{XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250,
|
||||
0, 0, 1, 48, 32, 80, 3, 7, 35},
|
||||
{XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 38},
|
||||
{XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 50},
|
||||
{XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250,
|
||||
0, 0, 1, 48, 32, 80, 3, 7, 50},
|
||||
{XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250,
|
||||
0, 0, 1, 48, 32, 80, 3, 5, 37},
|
||||
{XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 55},
|
||||
{XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 44},
|
||||
{XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 64},
|
||||
{XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 53},
|
||||
{XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 72},
|
||||
{XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 75},
|
||||
{XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 62},
|
||||
{XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500,
|
||||
0, 0, 1, 48, 32, 80, 3, 4, 78},
|
||||
{XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750,
|
||||
0, 0, 1, 48, 32, 80, 3, 6, 85},
|
||||
{XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000,
|
||||
0, 0, 0, 14, 56, 64, 1, 3, 28},
|
||||
{XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500,
|
||||
0, 1, 1, 88, 44, 148, 4, 5, 36},
|
||||
{XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000,
|
||||
0, 0, 1, 176, 88, 296, 20, 10, 60},
|
||||
{XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250,
|
||||
0, 1, 1, 110, 40, 220, 5, 5, 20},
|
||||
{XDPTX_VM_480_60_P, 0x00, 720, 480, 27027,
|
||||
0, 1, 1, 16, 62, 60, 9, 6, 30},
|
||||
{XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000,
|
||||
0, 0, 1, 88, 44, 148, 20, 10, 60},
|
||||
{XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000,
|
||||
0, 0, 1, 176, 88, 296, 20, 10, 60}
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue