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intc: update doxygen for the driver

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This patch updates the doxygen for the intc driver.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This commit is contained in:
Kedareswara rao Appana 2014-11-06 10:19:12 +05:30 • committed by Suneel Garapati
parent fc812ca9f8
commit 43a7c2e0c2
27 changed files with 1865 additions and 2328 deletions
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41
XilinxProcessorIPLib/drivers/intc/doc/html/api/annotated.html
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@ -2,39 +2,28 @@
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
Xilinx Driver intc v3_2: Class List
Class List
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
</head>
<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
<hr class="whs1">
<!-- Generated by Doxygen 1.6.1 -->
<div class="navigation" id="top">
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li class="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li class="current"><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul>
</div>
</div>
<div class="contents">
<!-- Generated by Doxygen 1.4.7 -->
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li id="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li id="current"><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul></div>
<h1>Class List</h1>Here are the classes, structs, unions and interfaces with brief descriptions:<table>
<tr><td class="indexkey"><a class="el" href="struct_x_intc.html">XIntc</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td><td class="indexvalue"></td></tr>
</table>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

39
XilinxProcessorIPLib/drivers/intc/doc/html/api/classes.html
View file

@ -1,39 +0,0 @@
<html>
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
Xilinx Driver intc v3_2: Alphabetical List
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
</head>
<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
<hr class="whs1">
<!-- Generated by Doxygen 1.6.1 -->
<div class="navigation" id="top">
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li class="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul>
</div>
</div>
<div class="contents">
<h1>Class Index</h1><div class="qindex"><a class="qindex" href="#letter_X">X</a></div>
<table align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
<tr><td><a name="letter_X"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&nbsp;&nbsp;X&nbsp;&nbsp;</div></td></tr></table>
</td><td><a class="el" href="struct_x_intc.html">XIntc</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a>&nbsp;&nbsp;&nbsp;</td></tr></table><div class="qindex"><a class="qindex" href="#letter_X">X</a></div>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>

41
XilinxProcessorIPLib/drivers/intc/doc/html/api/files.html
View file

@ -2,31 +2,25 @@
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
Xilinx Driver intc v3_2: File Index
File Index
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
</head>
<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
<hr class="whs1">
<!-- Generated by Doxygen 1.6.1 -->
<div class="navigation" id="top">
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li><a href="annotated.html"><span>Classes</span></a></li>
<li class="current"><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li class="current"><a href="files.html"><span>File&nbsp;List</span></a></li>
<li><a href="globals.html"><span>File&nbsp;Members</span></a></li>
</ul>
</div>
</div>
<div class="contents">
<!-- Generated by Doxygen 1.4.7 -->
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li><a href="annotated.html"><span>Classes</span></a></li>
<li id="current"><a href="files.html"><span>Files</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li id="current"><a href="files.html"><span>File&nbsp;List</span></a></li>
<li><a href="globals.html"><span>File&nbsp;Members</span></a></li>
</ul></div>
<h1>File List</h1>Here is a list of all files with brief descriptions:<table>
<tr><td class="indexkey"><a class="el" href="xintc_8c.html">xintc.c</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="xintc_8h.html">xintc.h</a></td><td class="indexvalue"></td></tr>
@ -38,9 +32,4 @@
<tr><td class="indexkey"><a class="el" href="xintc__options_8c.html">xintc_options.c</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="xintc__selftest_8c.html">xintc_selftest.c</a></td><td class="indexvalue"></td></tr>
</table>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

116
XilinxProcessorIPLib/drivers/intc/doc/html/api/functions.html
View file

@ -2,88 +2,48 @@
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
Xilinx Driver intc v3_2: Class Members
Class Members
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
</head>
<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
<hr class="whs1">
<!-- Generated by Doxygen 1.6.1 -->
<div class="navigation" id="top">
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li class="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li class="current"><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li class="current"><a href="functions.html"><span>All</span></a></li>
<li><a href="functions_vars.html"><span>Variables</span></a></li>
</ul>
</div>
<!-- Generated by Doxygen 1.4.7 -->
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li id="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li id="current"><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li id="current"><a href="functions.html"><span>All</span></a></li>
<li><a href="functions_vars.html"><span>Variables</span></a></li>
</ul>
</div>
<div class="contents">
Here is a list of all class members with links to the classes they belong to:<ul>
Here is a list of all class members with links to the classes they belong to:
<p>
<ul>
<li>AckBeforeService
: <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a>
</li>
<li>BaseAddress
: <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a>
, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>
</li>
<li>CallBackRef
: <a class="el" href="struct_x_intc___vector_table_entry.html#a8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry</a>
</li>
<li>CfgPtr
: <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a>
</li>
<li>DeviceId
: <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a>
</li>
<li>FastIntr
: <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config</a>
</li>
<li>Handler
: <a class="el" href="struct_x_intc___vector_table_entry.html#a509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry</a>
</li>
<li>HandlerTable
: <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config</a>
</li>
<li>IntcType
: <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a>
</li>
<li>IntVectorAddr
: <a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a>
</li>
<li>IsReady
: <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc</a>
</li>
<li>IsStarted
: <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a>
</li>
<li>NumberofIntrs
: <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a>
</li>
<li>Options
: <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a>
</li>
<li>UnhandledInterrupts
: <a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">XIntc</a>
</li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
: <a class="el" href="struct_x_intc___config.html#172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a><li>BaseAddress
: <a class="el" href="struct_x_intc.html#9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>, <a class="el" href="struct_x_intc___config.html#c0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a><li>CallBackRef
: <a class="el" href="struct_x_intc___vector_table_entry.html#8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry</a><li>CfgPtr
: <a class="el" href="struct_x_intc.html#c76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a><li>DeviceId
: <a class="el" href="struct_x_intc___config.html#1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a><li>FastIntr
: <a class="el" href="struct_x_intc___config.html#c894d2be382d08d83821c1672615d4d4">XIntc_Config</a><li>Handler
: <a class="el" href="struct_x_intc___vector_table_entry.html#509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry</a><li>HandlerTable
: <a class="el" href="struct_x_intc___config.html#f62197288a9019af6084a1675844e1ca">XIntc_Config</a><li>IntcType
: <a class="el" href="struct_x_intc___config.html#e54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a><li>IntVectorAddr
: <a class="el" href="struct_x_intc___config.html#3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a><li>IsReady
: <a class="el" href="struct_x_intc.html#277e8f00e1f6eb05f8097c676e826b62">XIntc</a><li>IsStarted
: <a class="el" href="struct_x_intc.html#3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a><li>NumberofIntrs
: <a class="el" href="struct_x_intc___config.html#6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a><li>Options
: <a class="el" href="struct_x_intc___config.html#c3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a><li>UnhandledInterrupts
: <a class="el" href="struct_x_intc.html#bf06c903e68a5569cdf238b185d83ff5">XIntc</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

116
XilinxProcessorIPLib/drivers/intc/doc/html/api/functions_vars.html
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@ -2,88 +2,48 @@
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
Xilinx Driver intc v3_2: Class Members - Variables
Class Members - Variables
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
</head>
<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
<hr class="whs1">
<!-- Generated by Doxygen 1.6.1 -->
<div class="navigation" id="top">
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li class="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li class="current"><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul>
</div>
<div class="tabs">
<ul>
<li><a href="functions.html"><span>All</span></a></li>
<li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
</ul>
</div>
<!-- Generated by Doxygen 1.4.7 -->
<div class="tabs">
<ul>
<li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
<li id="current"><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li><a href="annotated.html"><span>Class&nbsp;List</span></a></li>
<li id="current"><a href="functions.html"><span>Class&nbsp;Members</span></a></li>
</ul></div>
<div class="tabs">
<ul>
<li><a href="functions.html"><span>All</span></a></li>
<li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
</ul>
</div>
<div class="contents">
&nbsp;<ul>
&nbsp;
<p>
<ul>
<li>AckBeforeService
: <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a>
</li>
<li>BaseAddress
: <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a>
, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>
</li>
<li>CallBackRef
: <a class="el" href="struct_x_intc___vector_table_entry.html#a8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry</a>
</li>
<li>CfgPtr
: <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a>
</li>
<li>DeviceId
: <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a>
</li>
<li>FastIntr
: <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config</a>
</li>
<li>Handler
: <a class="el" href="struct_x_intc___vector_table_entry.html#a509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry</a>
</li>
<li>HandlerTable
: <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config</a>
</li>
<li>IntcType
: <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a>
</li>
<li>IntVectorAddr
: <a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a>
</li>
<li>IsReady
: <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc</a>
</li>
<li>IsStarted
: <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a>
</li>
<li>NumberofIntrs
: <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a>
</li>
<li>Options
: <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a>
</li>
<li>UnhandledInterrupts
: <a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">XIntc</a>
</li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
: <a class="el" href="struct_x_intc___config.html#172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a><li>BaseAddress
: <a class="el" href="struct_x_intc.html#9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>, <a class="el" href="struct_x_intc___config.html#c0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a><li>CallBackRef
: <a class="el" href="struct_x_intc___vector_table_entry.html#8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry</a><li>CfgPtr
: <a class="el" href="struct_x_intc.html#c76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a><li>DeviceId
: <a class="el" href="struct_x_intc___config.html#1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a><li>FastIntr
: <a class="el" href="struct_x_intc___config.html#c894d2be382d08d83821c1672615d4d4">XIntc_Config</a><li>Handler
: <a class="el" href="struct_x_intc___vector_table_entry.html#509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry</a><li>HandlerTable
: <a class="el" href="struct_x_intc___config.html#f62197288a9019af6084a1675844e1ca">XIntc_Config</a><li>IntcType
: <a class="el" href="struct_x_intc___config.html#e54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a><li>IntVectorAddr
: <a class="el" href="struct_x_intc___config.html#3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a><li>IsReady
: <a class="el" href="struct_x_intc.html#277e8f00e1f6eb05f8097c676e826b62">XIntc</a><li>IsStarted
: <a class="el" href="struct_x_intc.html#3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a><li>NumberofIntrs
: <a class="el" href="struct_x_intc___config.html#6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a><li>Options
: <a class="el" href="struct_x_intc___config.html#c3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a><li>UnhandledInterrupts
: <a class="el" href="struct_x_intc.html#bf06c903e68a5569cdf238b185d83ff5">XIntc</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

335
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@ -2,254 +2,103 @@
<head>
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Xilinx Driver intc v3_2: Class Members
Class Members
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<li><a href="globals_func.html"><span>Functions</span></a></li>
<li><a href="globals_vars.html"><span>Variables</span></a></li>
<li><a href="globals_type.html"><span>Typedefs</span></a></li>
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<li id="current"><a href="globals.html"><span>All</span></a></li>
<li><a href="globals_func.html"><span>Functions</span></a></li>
<li><a href="globals_vars.html"><span>Variables</span></a></li>
<li><a href="globals_type.html"><span>Typedefs</span></a></li>
<li><a href="globals_defs.html"><span>Defines</span></a></li>
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<li><a href="#index_x"><span>x</span></a></li>
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<p>
Here is a list of all file members with links to the files they belong to:
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<p>
<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
<li>XFastInterruptHandler
: <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">xintc_l.h</a>
</li>
<li>XIN_CIE_OFFSET
: <a class="el" href="xintc__l_8h.html#a1f88cc0f7e4c0fec39f68d4926537461">xintc_l.h</a>
</li>
<li>XIN_CONTROLLER_MAX_INTRS
: <a class="el" href="xintc_8h.html#a842aea1f6663265412f5618f102e8f18">xintc.h</a>
</li>
<li>XIN_IAR_OFFSET
: <a class="el" href="xintc__l_8h.html#af12b5f9e19d0d544e8df96699db615bd">xintc_l.h</a>
</li>
<li>XIN_IER_OFFSET
: <a class="el" href="xintc__l_8h.html#a12fbacf76cabd206d17acefd187fa7b4">xintc_l.h</a>
</li>
<li>XIN_ILR_OFFSET
: <a class="el" href="xintc__l_8h.html#ac92a6982a2d3a0f70a310c6912392765">xintc_l.h</a>
</li>
<li>XIN_IMR_OFFSET
: <a class="el" href="xintc__l_8h.html#a2dc06911d25b46e1ddad8e2938f95b4c">xintc_l.h</a>
</li>
<li>XIN_INT_HARDWARE_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#a399d5f29c768070adc3ac98c54c6634d">xintc_l.h</a>
</li>
<li>XIN_INT_MASTER_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#aa03735b19bf625b8868dd3633554addf">xintc_l.h</a>
</li>
<li>XIN_INTC_LAST
: <a class="el" href="xintc_8h.html#a3805fe4c0c209acc349242d75600646b">xintc.h</a>
</li>
<li>XIN_INTC_NOCASCADE
: <a class="el" href="xintc_8h.html#a6787fa567536384f6133b8ce90cf22f1">xintc.h</a>
</li>
<li>XIN_INTC_PRIMARY
: <a class="el" href="xintc_8h.html#ad8c8fd384185ceae0a8abe0cd8d4c638">xintc.h</a>
</li>
<li>XIN_INTC_SECONDARY
: <a class="el" href="xintc_8h.html#a35bc775ed0e234d9b069700f4825cd7d">xintc.h</a>
</li>
<li>XIN_IPR_OFFSET
: <a class="el" href="xintc__l_8h.html#a35c8f39e63012c1745df6faa39fc7335">xintc_l.h</a>
</li>
<li>XIN_ISR_OFFSET
: <a class="el" href="xintc__l_8h.html#a4c1ce88ba61c2e42054faaef40539556">xintc_l.h</a>
</li>
<li>XIN_IVAR_OFFSET
: <a class="el" href="xintc__l_8h.html#ab675a4446c4ab809551ea73ad2ca962d">xintc_l.h</a>
</li>
<li>XIN_IVR_OFFSET
: <a class="el" href="xintc__l_8h.html#a4704ae1ae4388d4b0187bb2ee79849d1">xintc_l.h</a>
</li>
<li>XIN_MER_OFFSET
: <a class="el" href="xintc__l_8h.html#a1286cdd3996f53dfe62703e6cd949b14">xintc_l.h</a>
</li>
<li>XIN_REAL_MODE
: <a class="el" href="xintc_8h.html#a56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a>
</li>
<li>XIN_SIE_OFFSET
: <a class="el" href="xintc__l_8h.html#ae3d1be1c28564014eba1e6a7da5f870c">xintc_l.h</a>
</li>
<li>XIN_SIMULATION_MODE
: <a class="el" href="xintc_8h.html#aefd5527cecdc1a6444b624d1e1a2514f">xintc.h</a>
</li>
<li>XIN_SVC_ALL_ISRS_OPTION
: <a class="el" href="xintc_8h.html#ad043237f658e83b2e8718ddddab12545">xintc.h</a>
</li>
<li>XIN_SVC_SGL_ISR_OPTION
: <a class="el" href="xintc_8h.html#af4bce8e2035f391b702686e49c66c839">xintc.h</a>
</li>
<li>XIN_TEST_MASK
: <a class="el" href="xintc__selftest_8c.html#a0a3e862d0b6387284dfc91d45dd3374e">xintc_selftest.c</a>
</li>
<li>XIntc_AckIntr
: <a class="el" href="xintc__l_8h.html#a4f699042980f8453713171959183fc49">xintc_l.h</a>
</li>
<li>XIntc_Acknowledge()
: <a class="el" href="xintc_8c.html#a8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a>
, <a class="el" href="xintc_8h.html#a8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.h</a>
</li>
<li>XIntc_BitPosMask
: <a class="el" href="xintc_8c.html#af97a3c0d3620f70f2e01db3237ed5305">xintc.c</a>
, <a class="el" href="xintc__i_8h.html#af0641659204bd99e09c1511b4d39e1a4">xintc_i.h</a>
</li>
<li>XIntc_ConfigTable
: <a class="el" href="xintc__g_8c.html#a2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a>
, <a class="el" href="xintc__i_8h.html#a6afbe6b28aa729c753744cba40ecf5b3">xintc_i.h</a>
</li>
<li>XIntc_Connect()
: <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">xintc.c</a>
, <a class="el" href="xintc_8h.html#aee9ec5873a764994d64b4da35a110084">xintc.h</a>
</li>
<li>XIntc_ConnectFastHandler()
: <a class="el" href="xintc_8c.html#a24a344d15b12b8acd82cd4c49a020d74">xintc.c</a>
, <a class="el" href="xintc_8h.html#a24a344d15b12b8acd82cd4c49a020d74">xintc.h</a>
</li>
<li>XIntc_DeviceInterruptHandler()
: <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a>
, <a class="el" href="xintc__l_8h.html#ace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.h</a>
</li>
<li>XIntc_Disable()
: <a class="el" href="xintc_8c.html#aea44ec361097925f2994558d402988ab">xintc.c</a>
, <a class="el" href="xintc_8h.html#aea44ec361097925f2994558d402988ab">xintc.h</a>
</li>
<li>XIntc_DisableIntr
: <a class="el" href="xintc__l_8h.html#a5df77bd3561a105f1d6b1837762db956">xintc_l.h</a>
</li>
<li>XIntc_Disconnect()
: <a class="el" href="xintc_8c.html#a8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a>
, <a class="el" href="xintc_8h.html#a8f7caaeb26b6b264fffefbd32f90f855">xintc.h</a>
</li>
<li>XIntc_Enable()
: <a class="el" href="xintc_8c.html#ac7f59192d3b3ba2e2283a264677577b8">xintc.c</a>
, <a class="el" href="xintc_8h.html#ac7f59192d3b3ba2e2283a264677577b8">xintc.h</a>
</li>
<li>XIntc_EnableIntr
: <a class="el" href="xintc__l_8h.html#ad35ec3b9b658f26d989b19783954683e">xintc_l.h</a>
</li>
<li>XIntc_GetIntrStatus
: <a class="el" href="xintc__l_8h.html#a13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a>
</li>
<li>XIntc_GetOptions()
: <a class="el" href="xintc_8h.html#a6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a>
, <a class="el" href="xintc__options_8c.html#a6fdbe96b1db87f0c78e68da8bc767a69">xintc_options.c</a>
</li>
<li>XINTC_H
: <a class="el" href="xintc_8h.html#a9e07373b9cba0eafcb65c0dd23f6a4ab">xintc.h</a>
</li>
<li>XINTC_I_H
: <a class="el" href="xintc__i_8h.html#a2d461c0e2b7ab3d3106575c4c3a5adff">xintc_i.h</a>
</li>
<li>XIntc_In32
: <a class="el" href="xintc__l_8h.html#a0254df2003fdd1434617b0477224f748">xintc_l.h</a>
</li>
<li>XIntc_Initialize()
: <a class="el" href="xintc_8c.html#aa7adc53d40c41e1a714ef8857329043d">xintc.c</a>
, <a class="el" href="xintc_8h.html#aa7adc53d40c41e1a714ef8857329043d">xintc.h</a>
</li>
<li>XIntc_InterruptHandler()
: <a class="el" href="xintc_8h.html#a635187ed756cee70b4b4051560cbd7bc">xintc.h</a>
, <a class="el" href="xintc__intr_8c.html#a635187ed756cee70b4b4051560cbd7bc">xintc_intr.c</a>
</li>
<li>XINTC_L_H
: <a class="el" href="xintc__l_8h.html#a2591750e740c97fb30372d7fd6fba9ca">xintc_l.h</a>
</li>
<li>XIntc_LookupConfig()
: <a class="el" href="xintc_8h.html#ab2da07d4eeab07ac1ef67d56af1e1cb7">xintc.h</a>
, <a class="el" href="xintc_8c.html#ab2da07d4eeab07ac1ef67d56af1e1cb7">xintc.c</a>
</li>
<li>XIntc_LowLevelInterruptHandler()
: <a class="el" href="xintc__l_8h.html#abf91e27eb2cc036f84df2e15d14343a8">xintc_l.h</a>
</li>
<li>XIntc_MasterDisable
: <a class="el" href="xintc__l_8h.html#a93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a>
</li>
<li>XIntc_MasterEnable
: <a class="el" href="xintc__l_8h.html#af2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a>
</li>
<li>XIntc_Out32
: <a class="el" href="xintc__l_8h.html#ac245f85f403876d4e23cf5e24439a66a">xintc_l.h</a>
</li>
<li>XIntc_RegisterFastHandler()
: <a class="el" href="xintc__l_8h.html#aed2ddee41f0861539f959522ce2f44af">xintc_l.h</a>
, <a class="el" href="xintc__l_8c.html#aed2ddee41f0861539f959522ce2f44af">xintc_l.c</a>
</li>
<li>XIntc_RegisterHandler()
: <a class="el" href="xintc__l_8c.html#ad1f8540fa2171b00a3af03329677f684">xintc_l.c</a>
, <a class="el" href="xintc__l_8h.html#ad1f8540fa2171b00a3af03329677f684">xintc_l.h</a>
</li>
<li>XIntc_SelfTest()
: <a class="el" href="xintc__selftest_8c.html#af9a9a16180b363930d21bc94dfe71147">xintc_selftest.c</a>
, <a class="el" href="xintc_8h.html#af9a9a16180b363930d21bc94dfe71147">xintc.h</a>
</li>
<li>XIntc_SetIntrSvcOption()
: <a class="el" href="xintc__l_8c.html#ab8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a>
, <a class="el" href="xintc__l_8h.html#ab8e5767995d6318e6fc5cf114cda7b68">xintc_l.h</a>
</li>
<li>XIntc_SetNormalIntrMode()
: <a class="el" href="xintc_8h.html#a881154092f4f8cd5e29a71b284f7b2ae">xintc.h</a>
, <a class="el" href="xintc_8c.html#a881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a>
</li>
<li>XIntc_SetOptions()
: <a class="el" href="xintc_8h.html#a1f0d32716f082a51a751df84312c7d56">xintc.h</a>
, <a class="el" href="xintc__options_8c.html#a1f0d32716f082a51a751df84312c7d56">xintc_options.c</a>
</li>
<li>XIntc_SimulateIntr()
: <a class="el" href="xintc_8h.html#a17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a>
, <a class="el" href="xintc__selftest_8c.html#a17972363ab5a1a8f5f1d135c5b3c22c7">xintc_selftest.c</a>
</li>
<li>XIntc_Start()
: <a class="el" href="xintc_8h.html#a863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.h</a>
, <a class="el" href="xintc_8c.html#a863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a>
</li>
<li>XIntc_Stop()
: <a class="el" href="xintc_8c.html#afabb05cf2e5b62031524a33d1f88f405">xintc.c</a>
, <a class="el" href="xintc_8h.html#afabb05cf2e5b62031524a33d1f88f405">xintc.h</a>
</li>
<li>XIntc_VoidInterruptHandler()
: <a class="el" href="xintc_8h.html#a9c6dc6e838193da3ce51c8cdb3b88943">xintc.h</a>
</li>
<li>XPAR_XINTC_USE_DCR_BRIDGE
: <a class="el" href="xintc__l_8h.html#a06a568b99545df04b6d14da3b04f1da0">xintc_l.h</a>
</li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
: <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">xintc_l.h</a><li>XIN_CIE_OFFSET
: <a class="el" href="xintc__l_8h.html#1f88cc0f7e4c0fec39f68d4926537461">xintc_l.h</a><li>XIN_CONTROLLER_MAX_INTRS
: <a class="el" href="xintc_8h.html#842aea1f6663265412f5618f102e8f18">xintc.h</a><li>XIN_IAR_OFFSET
: <a class="el" href="xintc__l_8h.html#f12b5f9e19d0d544e8df96699db615bd">xintc_l.h</a><li>XIN_IER_OFFSET
: <a class="el" href="xintc__l_8h.html#12fbacf76cabd206d17acefd187fa7b4">xintc_l.h</a><li>XIN_ILR_OFFSET
: <a class="el" href="xintc__l_8h.html#c92a6982a2d3a0f70a310c6912392765">xintc_l.h</a><li>XIN_IMR_OFFSET
: <a class="el" href="xintc__l_8h.html#2dc06911d25b46e1ddad8e2938f95b4c">xintc_l.h</a><li>XIN_INT_HARDWARE_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#399d5f29c768070adc3ac98c54c6634d">xintc_l.h</a><li>XIN_INT_MASTER_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#a03735b19bf625b8868dd3633554addf">xintc_l.h</a><li>XIN_INTC_LAST
: <a class="el" href="xintc_8h.html#3805fe4c0c209acc349242d75600646b">xintc.h</a><li>XIN_INTC_NOCASCADE
: <a class="el" href="xintc_8h.html#6787fa567536384f6133b8ce90cf22f1">xintc.h</a><li>XIN_INTC_PRIMARY
: <a class="el" href="xintc_8h.html#d8c8fd384185ceae0a8abe0cd8d4c638">xintc.h</a><li>XIN_INTC_SECONDARY
: <a class="el" href="xintc_8h.html#35bc775ed0e234d9b069700f4825cd7d">xintc.h</a><li>XIN_IPR_OFFSET
: <a class="el" href="xintc__l_8h.html#35c8f39e63012c1745df6faa39fc7335">xintc_l.h</a><li>XIN_ISR_OFFSET
: <a class="el" href="xintc__l_8h.html#4c1ce88ba61c2e42054faaef40539556">xintc_l.h</a><li>XIN_IVAR_OFFSET
: <a class="el" href="xintc__l_8h.html#b675a4446c4ab809551ea73ad2ca962d">xintc_l.h</a><li>XIN_IVR_OFFSET
: <a class="el" href="xintc__l_8h.html#4704ae1ae4388d4b0187bb2ee79849d1">xintc_l.h</a><li>XIN_MER_OFFSET
: <a class="el" href="xintc__l_8h.html#1286cdd3996f53dfe62703e6cd949b14">xintc_l.h</a><li>XIN_REAL_MODE
: <a class="el" href="xintc_8h.html#56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a><li>XIN_SIE_OFFSET
: <a class="el" href="xintc__l_8h.html#e3d1be1c28564014eba1e6a7da5f870c">xintc_l.h</a><li>XIN_SIMULATION_MODE
: <a class="el" href="xintc_8h.html#efd5527cecdc1a6444b624d1e1a2514f">xintc.h</a><li>XIN_SVC_ALL_ISRS_OPTION
: <a class="el" href="xintc_8h.html#d043237f658e83b2e8718ddddab12545">xintc.h</a><li>XIN_SVC_SGL_ISR_OPTION
: <a class="el" href="xintc_8h.html#f4bce8e2035f391b702686e49c66c839">xintc.h</a><li>XIN_TEST_MASK
: <a class="el" href="xintc__selftest_8c.html#0a3e862d0b6387284dfc91d45dd3374e">xintc_selftest.c</a><li>XIntc_AckIntr
: <a class="el" href="xintc__l_8h.html#4f699042980f8453713171959183fc49">xintc_l.h</a><li>XIntc_Acknowledge()
: <a class="el" href="xintc_8h.html#8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.h</a>, <a class="el" href="xintc_8c.html#8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a><li>XIntc_BitPosMask
: <a class="el" href="xintc__i_8h.html#f0641659204bd99e09c1511b4d39e1a4">xintc_i.h</a>, <a class="el" href="xintc_8c.html#f97a3c0d3620f70f2e01db3237ed5305">xintc.c</a><li>XIntc_ConfigTable
: <a class="el" href="xintc__i_8h.html#6afbe6b28aa729c753744cba40ecf5b3">xintc_i.h</a>, <a class="el" href="xintc__g_8c.html#2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a><li>XIntc_Connect()
: <a class="el" href="xintc_8h.html#ee9ec5873a764994d64b4da35a110084">xintc.h</a>, <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">xintc.c</a><li>XIntc_ConnectFastHandler()
: <a class="el" href="xintc_8h.html#24a344d15b12b8acd82cd4c49a020d74">xintc.h</a>, <a class="el" href="xintc_8c.html#24a344d15b12b8acd82cd4c49a020d74">xintc.c</a><li>XIntc_DeviceInterruptHandler()
: <a class="el" href="xintc__l_8h.html#ce91a1aeaf1a88e1b769decb4ac4a818">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a><li>XIntc_Disable()
: <a class="el" href="xintc_8h.html#ea44ec361097925f2994558d402988ab">xintc.h</a>, <a class="el" href="xintc_8c.html#ea44ec361097925f2994558d402988ab">xintc.c</a><li>XIntc_DisableIntr
: <a class="el" href="xintc__l_8h.html#5df77bd3561a105f1d6b1837762db956">xintc_l.h</a><li>XIntc_Disconnect()
: <a class="el" href="xintc_8h.html#8f7caaeb26b6b264fffefbd32f90f855">xintc.h</a>, <a class="el" href="xintc_8c.html#8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a><li>XIntc_Enable()
: <a class="el" href="xintc_8h.html#c7f59192d3b3ba2e2283a264677577b8">xintc.h</a>, <a class="el" href="xintc_8c.html#c7f59192d3b3ba2e2283a264677577b8">xintc.c</a><li>XIntc_EnableIntr
: <a class="el" href="xintc__l_8h.html#d35ec3b9b658f26d989b19783954683e">xintc_l.h</a><li>XIntc_GetIntrStatus
: <a class="el" href="xintc__l_8h.html#13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a><li>XIntc_GetOptions()
: <a class="el" href="xintc__options_8c.html#6fdbe96b1db87f0c78e68da8bc767a69">xintc_options.c</a>, <a class="el" href="xintc_8h.html#6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a><li>XINTC_H
: <a class="el" href="xintc_8h.html#9e07373b9cba0eafcb65c0dd23f6a4ab">xintc.h</a><li>XINTC_I_H
: <a class="el" href="xintc__i_8h.html#2d461c0e2b7ab3d3106575c4c3a5adff">xintc_i.h</a><li>XIntc_In32
: <a class="el" href="xintc__l_8h.html#0254df2003fdd1434617b0477224f748">xintc_l.h</a><li>XIntc_Initialize()
: <a class="el" href="xintc_8h.html#a7adc53d40c41e1a714ef8857329043d">xintc.h</a>, <a class="el" href="xintc_8c.html#a7adc53d40c41e1a714ef8857329043d">xintc.c</a><li>XIntc_InterruptHandler()
: <a class="el" href="xintc__intr_8c.html#635187ed756cee70b4b4051560cbd7bc">xintc_intr.c</a>, <a class="el" href="xintc_8h.html#635187ed756cee70b4b4051560cbd7bc">xintc.h</a><li>XINTC_L_H
: <a class="el" href="xintc__l_8h.html#2591750e740c97fb30372d7fd6fba9ca">xintc_l.h</a><li>XIntc_LookupConfig()
: <a class="el" href="xintc_8h.html#b2da07d4eeab07ac1ef67d56af1e1cb7">xintc.h</a>, <a class="el" href="xintc_8c.html#b2da07d4eeab07ac1ef67d56af1e1cb7">xintc.c</a><li>XIntc_LowLevelInterruptHandler()
: <a class="el" href="xintc__l_8h.html#bf91e27eb2cc036f84df2e15d14343a8">xintc_l.h</a><li>XIntc_MasterDisable
: <a class="el" href="xintc__l_8h.html#93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a><li>XIntc_MasterEnable
: <a class="el" href="xintc__l_8h.html#f2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a><li>XIntc_Out32
: <a class="el" href="xintc__l_8h.html#c245f85f403876d4e23cf5e24439a66a">xintc_l.h</a><li>XIntc_RegisterFastHandler()
: <a class="el" href="xintc__l_8h.html#ed2ddee41f0861539f959522ce2f44af">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#ed2ddee41f0861539f959522ce2f44af">xintc_l.c</a><li>XIntc_RegisterHandler()
: <a class="el" href="xintc__l_8h.html#d1f8540fa2171b00a3af03329677f684">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#d1f8540fa2171b00a3af03329677f684">xintc_l.c</a><li>XIntc_SelfTest()
: <a class="el" href="xintc__selftest_8c.html#f9a9a16180b363930d21bc94dfe71147">xintc_selftest.c</a>, <a class="el" href="xintc_8h.html#f9a9a16180b363930d21bc94dfe71147">xintc.h</a><li>XIntc_SetIntrSvcOption()
: <a class="el" href="xintc__l_8h.html#b8e5767995d6318e6fc5cf114cda7b68">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#b8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a><li>XIntc_SetNormalIntrMode()
: <a class="el" href="xintc_8h.html#881154092f4f8cd5e29a71b284f7b2ae">xintc.h</a>, <a class="el" href="xintc_8c.html#881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a><li>XIntc_SetOptions()
: <a class="el" href="xintc__options_8c.html#1f0d32716f082a51a751df84312c7d56">xintc_options.c</a>, <a class="el" href="xintc_8h.html#1f0d32716f082a51a751df84312c7d56">xintc.h</a><li>XIntc_SimulateIntr()
: <a class="el" href="xintc__selftest_8c.html#17972363ab5a1a8f5f1d135c5b3c22c7">xintc_selftest.c</a>, <a class="el" href="xintc_8h.html#17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a><li>XIntc_Start()
: <a class="el" href="xintc_8h.html#863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.h</a>, <a class="el" href="xintc_8c.html#863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a><li>XIntc_Stop()
: <a class="el" href="xintc_8h.html#fabb05cf2e5b62031524a33d1f88f405">xintc.h</a>, <a class="el" href="xintc_8c.html#fabb05cf2e5b62031524a33d1f88f405">xintc.c</a><li>XIntc_VoidInterruptHandler()
: <a class="el" href="xintc_8h.html#9c6dc6e838193da3ce51c8cdb3b88943">xintc.h</a><li>XPAR_XINTC_USE_DCR_BRIDGE
: <a class="el" href="xintc__l_8h.html#06a568b99545df04b6d14da3b04f1da0">xintc_l.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: Class Members
Class Members
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<p>
<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
<li>XIN_CIE_OFFSET
: <a class="el" href="xintc__l_8h.html#a1f88cc0f7e4c0fec39f68d4926537461">xintc_l.h</a>
</li>
<li>XIN_CONTROLLER_MAX_INTRS
: <a class="el" href="xintc_8h.html#a842aea1f6663265412f5618f102e8f18">xintc.h</a>
</li>
<li>XIN_IAR_OFFSET
: <a class="el" href="xintc__l_8h.html#af12b5f9e19d0d544e8df96699db615bd">xintc_l.h</a>
</li>
<li>XIN_IER_OFFSET
: <a class="el" href="xintc__l_8h.html#a12fbacf76cabd206d17acefd187fa7b4">xintc_l.h</a>
</li>
<li>XIN_ILR_OFFSET
: <a class="el" href="xintc__l_8h.html#ac92a6982a2d3a0f70a310c6912392765">xintc_l.h</a>
</li>
<li>XIN_IMR_OFFSET
: <a class="el" href="xintc__l_8h.html#a2dc06911d25b46e1ddad8e2938f95b4c">xintc_l.h</a>
</li>
<li>XIN_INT_HARDWARE_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#a399d5f29c768070adc3ac98c54c6634d">xintc_l.h</a>
</li>
<li>XIN_INT_MASTER_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#aa03735b19bf625b8868dd3633554addf">xintc_l.h</a>
</li>
<li>XIN_INTC_LAST
: <a class="el" href="xintc_8h.html#a3805fe4c0c209acc349242d75600646b">xintc.h</a>
</li>
<li>XIN_INTC_NOCASCADE
: <a class="el" href="xintc_8h.html#a6787fa567536384f6133b8ce90cf22f1">xintc.h</a>
</li>
<li>XIN_INTC_PRIMARY
: <a class="el" href="xintc_8h.html#ad8c8fd384185ceae0a8abe0cd8d4c638">xintc.h</a>
</li>
<li>XIN_INTC_SECONDARY
: <a class="el" href="xintc_8h.html#a35bc775ed0e234d9b069700f4825cd7d">xintc.h</a>
</li>
<li>XIN_IPR_OFFSET
: <a class="el" href="xintc__l_8h.html#a35c8f39e63012c1745df6faa39fc7335">xintc_l.h</a>
</li>
<li>XIN_ISR_OFFSET
: <a class="el" href="xintc__l_8h.html#a4c1ce88ba61c2e42054faaef40539556">xintc_l.h</a>
</li>
<li>XIN_IVAR_OFFSET
: <a class="el" href="xintc__l_8h.html#ab675a4446c4ab809551ea73ad2ca962d">xintc_l.h</a>
</li>
<li>XIN_IVR_OFFSET
: <a class="el" href="xintc__l_8h.html#a4704ae1ae4388d4b0187bb2ee79849d1">xintc_l.h</a>
</li>
<li>XIN_MER_OFFSET
: <a class="el" href="xintc__l_8h.html#a1286cdd3996f53dfe62703e6cd949b14">xintc_l.h</a>
</li>
<li>XIN_REAL_MODE
: <a class="el" href="xintc_8h.html#a56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a>
</li>
<li>XIN_SIE_OFFSET
: <a class="el" href="xintc__l_8h.html#ae3d1be1c28564014eba1e6a7da5f870c">xintc_l.h</a>
</li>
<li>XIN_SIMULATION_MODE
: <a class="el" href="xintc_8h.html#aefd5527cecdc1a6444b624d1e1a2514f">xintc.h</a>
</li>
<li>XIN_SVC_ALL_ISRS_OPTION
: <a class="el" href="xintc_8h.html#ad043237f658e83b2e8718ddddab12545">xintc.h</a>
</li>
<li>XIN_SVC_SGL_ISR_OPTION
: <a class="el" href="xintc_8h.html#af4bce8e2035f391b702686e49c66c839">xintc.h</a>
</li>
<li>XIN_TEST_MASK
: <a class="el" href="xintc__selftest_8c.html#a0a3e862d0b6387284dfc91d45dd3374e">xintc_selftest.c</a>
</li>
<li>XIntc_AckIntr
: <a class="el" href="xintc__l_8h.html#a4f699042980f8453713171959183fc49">xintc_l.h</a>
</li>
<li>XIntc_DisableIntr
: <a class="el" href="xintc__l_8h.html#a5df77bd3561a105f1d6b1837762db956">xintc_l.h</a>
</li>
<li>XIntc_EnableIntr
: <a class="el" href="xintc__l_8h.html#ad35ec3b9b658f26d989b19783954683e">xintc_l.h</a>
</li>
<li>XIntc_GetIntrStatus
: <a class="el" href="xintc__l_8h.html#a13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a>
</li>
<li>XINTC_H
: <a class="el" href="xintc_8h.html#a9e07373b9cba0eafcb65c0dd23f6a4ab">xintc.h</a>
</li>
<li>XINTC_I_H
: <a class="el" href="xintc__i_8h.html#a2d461c0e2b7ab3d3106575c4c3a5adff">xintc_i.h</a>
</li>
<li>XIntc_In32
: <a class="el" href="xintc__l_8h.html#a0254df2003fdd1434617b0477224f748">xintc_l.h</a>
</li>
<li>XINTC_L_H
: <a class="el" href="xintc__l_8h.html#a2591750e740c97fb30372d7fd6fba9ca">xintc_l.h</a>
</li>
<li>XIntc_MasterDisable
: <a class="el" href="xintc__l_8h.html#a93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a>
</li>
<li>XIntc_MasterEnable
: <a class="el" href="xintc__l_8h.html#af2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a>
</li>
<li>XIntc_Out32
: <a class="el" href="xintc__l_8h.html#ac245f85f403876d4e23cf5e24439a66a">xintc_l.h</a>
</li>
<li>XPAR_XINTC_USE_DCR_BRIDGE
: <a class="el" href="xintc__l_8h.html#a06a568b99545df04b6d14da3b04f1da0">xintc_l.h</a>
</li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
: <a class="el" href="xintc__l_8h.html#1f88cc0f7e4c0fec39f68d4926537461">xintc_l.h</a><li>XIN_CONTROLLER_MAX_INTRS
: <a class="el" href="xintc_8h.html#842aea1f6663265412f5618f102e8f18">xintc.h</a><li>XIN_IAR_OFFSET
: <a class="el" href="xintc__l_8h.html#f12b5f9e19d0d544e8df96699db615bd">xintc_l.h</a><li>XIN_IER_OFFSET
: <a class="el" href="xintc__l_8h.html#12fbacf76cabd206d17acefd187fa7b4">xintc_l.h</a><li>XIN_ILR_OFFSET
: <a class="el" href="xintc__l_8h.html#c92a6982a2d3a0f70a310c6912392765">xintc_l.h</a><li>XIN_IMR_OFFSET
: <a class="el" href="xintc__l_8h.html#2dc06911d25b46e1ddad8e2938f95b4c">xintc_l.h</a><li>XIN_INT_HARDWARE_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#399d5f29c768070adc3ac98c54c6634d">xintc_l.h</a><li>XIN_INT_MASTER_ENABLE_MASK
: <a class="el" href="xintc__l_8h.html#a03735b19bf625b8868dd3633554addf">xintc_l.h</a><li>XIN_INTC_LAST
: <a class="el" href="xintc_8h.html#3805fe4c0c209acc349242d75600646b">xintc.h</a><li>XIN_INTC_NOCASCADE
: <a class="el" href="xintc_8h.html#6787fa567536384f6133b8ce90cf22f1">xintc.h</a><li>XIN_INTC_PRIMARY
: <a class="el" href="xintc_8h.html#d8c8fd384185ceae0a8abe0cd8d4c638">xintc.h</a><li>XIN_INTC_SECONDARY
: <a class="el" href="xintc_8h.html#35bc775ed0e234d9b069700f4825cd7d">xintc.h</a><li>XIN_IPR_OFFSET
: <a class="el" href="xintc__l_8h.html#35c8f39e63012c1745df6faa39fc7335">xintc_l.h</a><li>XIN_ISR_OFFSET
: <a class="el" href="xintc__l_8h.html#4c1ce88ba61c2e42054faaef40539556">xintc_l.h</a><li>XIN_IVAR_OFFSET
: <a class="el" href="xintc__l_8h.html#b675a4446c4ab809551ea73ad2ca962d">xintc_l.h</a><li>XIN_IVR_OFFSET
: <a class="el" href="xintc__l_8h.html#4704ae1ae4388d4b0187bb2ee79849d1">xintc_l.h</a><li>XIN_MER_OFFSET
: <a class="el" href="xintc__l_8h.html#1286cdd3996f53dfe62703e6cd949b14">xintc_l.h</a><li>XIN_REAL_MODE
: <a class="el" href="xintc_8h.html#56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a><li>XIN_SIE_OFFSET
: <a class="el" href="xintc__l_8h.html#e3d1be1c28564014eba1e6a7da5f870c">xintc_l.h</a><li>XIN_SIMULATION_MODE
: <a class="el" href="xintc_8h.html#efd5527cecdc1a6444b624d1e1a2514f">xintc.h</a><li>XIN_SVC_ALL_ISRS_OPTION
: <a class="el" href="xintc_8h.html#d043237f658e83b2e8718ddddab12545">xintc.h</a><li>XIN_SVC_SGL_ISR_OPTION
: <a class="el" href="xintc_8h.html#f4bce8e2035f391b702686e49c66c839">xintc.h</a><li>XIN_TEST_MASK
: <a class="el" href="xintc__selftest_8c.html#0a3e862d0b6387284dfc91d45dd3374e">xintc_selftest.c</a><li>XIntc_AckIntr
: <a class="el" href="xintc__l_8h.html#4f699042980f8453713171959183fc49">xintc_l.h</a><li>XIntc_DisableIntr
: <a class="el" href="xintc__l_8h.html#5df77bd3561a105f1d6b1837762db956">xintc_l.h</a><li>XIntc_EnableIntr
: <a class="el" href="xintc__l_8h.html#d35ec3b9b658f26d989b19783954683e">xintc_l.h</a><li>XIntc_GetIntrStatus
: <a class="el" href="xintc__l_8h.html#13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a><li>XINTC_H
: <a class="el" href="xintc_8h.html#9e07373b9cba0eafcb65c0dd23f6a4ab">xintc.h</a><li>XINTC_I_H
: <a class="el" href="xintc__i_8h.html#2d461c0e2b7ab3d3106575c4c3a5adff">xintc_i.h</a><li>XIntc_In32
: <a class="el" href="xintc__l_8h.html#0254df2003fdd1434617b0477224f748">xintc_l.h</a><li>XINTC_L_H
: <a class="el" href="xintc__l_8h.html#2591750e740c97fb30372d7fd6fba9ca">xintc_l.h</a><li>XIntc_MasterDisable
: <a class="el" href="xintc__l_8h.html#93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a><li>XIntc_MasterEnable
: <a class="el" href="xintc__l_8h.html#f2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a><li>XIntc_Out32
: <a class="el" href="xintc__l_8h.html#c245f85f403876d4e23cf5e24439a66a">xintc_l.h</a><li>XPAR_XINTC_USE_DCR_BRIDGE
: <a class="el" href="xintc__l_8h.html#06a568b99545df04b6d14da3b04f1da0">xintc_l.h</a></ul>
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Xilinx Driver intc v3_2: Class Members
Class Members
</title>
<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<li class="current"><a href="globals.html"><span>File&nbsp;Members</span></a></li>
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<li><a href="globals.html"><span>All</span></a></li>
<li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
<li><a href="globals_vars.html"><span>Variables</span></a></li>
<li><a href="globals_type.html"><span>Typedefs</span></a></li>
<li><a href="globals_defs.html"><span>Defines</span></a></li>
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<li><a href="#index_x"><span>x</span></a></li>
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<!-- Generated by Doxygen 1.4.7 -->
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<li><a href="files.html"><span>File&nbsp;List</span></a></li>
<li id="current"><a href="globals.html"><span>File&nbsp;Members</span></a></li>
</ul></div>
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<li><a href="globals.html"><span>All</span></a></li>
<li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
<li><a href="globals_vars.html"><span>Variables</span></a></li>
<li><a href="globals_type.html"><span>Typedefs</span></a></li>
<li><a href="globals_defs.html"><span>Defines</span></a></li>
</ul>
</div>
<div class="contents">
&nbsp;
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<p>
<ul>
<li>XIntc_Acknowledge()
: <a class="el" href="xintc_8c.html#a8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a>
, <a class="el" href="xintc_8h.html#a8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.h</a>
</li>
<li>XIntc_Connect()
: <a class="el" href="xintc_8h.html#aee9ec5873a764994d64b4da35a110084">xintc.h</a>
, <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">xintc.c</a>
</li>
<li>XIntc_ConnectFastHandler()
: <a class="el" href="xintc_8c.html#a24a344d15b12b8acd82cd4c49a020d74">xintc.c</a>
, <a class="el" href="xintc_8h.html#a24a344d15b12b8acd82cd4c49a020d74">xintc.h</a>
</li>
<li>XIntc_DeviceInterruptHandler()
: <a class="el" href="xintc__l_8h.html#ace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.h</a>
, <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a>
</li>
<li>XIntc_Disable()
: <a class="el" href="xintc_8c.html#aea44ec361097925f2994558d402988ab">xintc.c</a>
, <a class="el" href="xintc_8h.html#aea44ec361097925f2994558d402988ab">xintc.h</a>
</li>
<li>XIntc_Disconnect()
: <a class="el" href="xintc_8c.html#a8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a>
, <a class="el" href="xintc_8h.html#a8f7caaeb26b6b264fffefbd32f90f855">xintc.h</a>
</li>
<li>XIntc_Enable()
: <a class="el" href="xintc_8c.html#ac7f59192d3b3ba2e2283a264677577b8">xintc.c</a>
, <a class="el" href="xintc_8h.html#ac7f59192d3b3ba2e2283a264677577b8">xintc.h</a>
</li>
<li>XIntc_GetOptions()
: <a class="el" href="xintc__options_8c.html#a6fdbe96b1db87f0c78e68da8bc767a69">xintc_options.c</a>
, <a class="el" href="xintc_8h.html#a6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a>
</li>
<li>XIntc_Initialize()
: <a class="el" href="xintc_8c.html#aa7adc53d40c41e1a714ef8857329043d">xintc.c</a>
, <a class="el" href="xintc_8h.html#aa7adc53d40c41e1a714ef8857329043d">xintc.h</a>
</li>
<li>XIntc_InterruptHandler()
: <a class="el" href="xintc_8h.html#a635187ed756cee70b4b4051560cbd7bc">xintc.h</a>
, <a class="el" href="xintc__intr_8c.html#a635187ed756cee70b4b4051560cbd7bc">xintc_intr.c</a>
</li>
<li>XIntc_LookupConfig()
: <a class="el" href="xintc_8c.html#ab2da07d4eeab07ac1ef67d56af1e1cb7">xintc.c</a>
, <a class="el" href="xintc_8h.html#ab2da07d4eeab07ac1ef67d56af1e1cb7">xintc.h</a>
</li>
<li>XIntc_LowLevelInterruptHandler()
: <a class="el" href="xintc__l_8h.html#abf91e27eb2cc036f84df2e15d14343a8">xintc_l.h</a>
</li>
<li>XIntc_RegisterFastHandler()
: <a class="el" href="xintc__l_8c.html#aed2ddee41f0861539f959522ce2f44af">xintc_l.c</a>
, <a class="el" href="xintc__l_8h.html#aed2ddee41f0861539f959522ce2f44af">xintc_l.h</a>
</li>
<li>XIntc_RegisterHandler()
: <a class="el" href="xintc__l_8h.html#ad1f8540fa2171b00a3af03329677f684">xintc_l.h</a>
, <a class="el" href="xintc__l_8c.html#ad1f8540fa2171b00a3af03329677f684">xintc_l.c</a>
</li>
<li>XIntc_SelfTest()
: <a class="el" href="xintc_8h.html#af9a9a16180b363930d21bc94dfe71147">xintc.h</a>
, <a class="el" href="xintc__selftest_8c.html#af9a9a16180b363930d21bc94dfe71147">xintc_selftest.c</a>
</li>
<li>XIntc_SetIntrSvcOption()
: <a class="el" href="xintc__l_8c.html#ab8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a>
, <a class="el" href="xintc__l_8h.html#ab8e5767995d6318e6fc5cf114cda7b68">xintc_l.h</a>
</li>
<li>XIntc_SetNormalIntrMode()
: <a class="el" href="xintc_8h.html#a881154092f4f8cd5e29a71b284f7b2ae">xintc.h</a>
, <a class="el" href="xintc_8c.html#a881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a>
</li>
<li>XIntc_SetOptions()
: <a class="el" href="xintc__options_8c.html#a1f0d32716f082a51a751df84312c7d56">xintc_options.c</a>
, <a class="el" href="xintc_8h.html#a1f0d32716f082a51a751df84312c7d56">xintc.h</a>
</li>
<li>XIntc_SimulateIntr()
: <a class="el" href="xintc_8h.html#a17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a>
, <a class="el" href="xintc__selftest_8c.html#a17972363ab5a1a8f5f1d135c5b3c22c7">xintc_selftest.c</a>
</li>
<li>XIntc_Start()
: <a class="el" href="xintc_8c.html#a863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a>
, <a class="el" href="xintc_8h.html#a863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.h</a>
</li>
<li>XIntc_Stop()
: <a class="el" href="xintc_8h.html#afabb05cf2e5b62031524a33d1f88f405">xintc.h</a>
, <a class="el" href="xintc_8c.html#afabb05cf2e5b62031524a33d1f88f405">xintc.c</a>
</li>
<li>XIntc_VoidInterruptHandler()
: <a class="el" href="xintc_8h.html#a9c6dc6e838193da3ce51c8cdb3b88943">xintc.h</a>
</li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
: <a class="el" href="xintc_8h.html#8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.h</a>, <a class="el" href="xintc_8c.html#8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a><li>XIntc_Connect()
: <a class="el" href="xintc_8h.html#ee9ec5873a764994d64b4da35a110084">xintc.h</a>, <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">xintc.c</a><li>XIntc_ConnectFastHandler()
: <a class="el" href="xintc_8h.html#24a344d15b12b8acd82cd4c49a020d74">xintc.h</a>, <a class="el" href="xintc_8c.html#24a344d15b12b8acd82cd4c49a020d74">xintc.c</a><li>XIntc_DeviceInterruptHandler()
: <a class="el" href="xintc__l_8h.html#ce91a1aeaf1a88e1b769decb4ac4a818">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a><li>XIntc_Disable()
: <a class="el" href="xintc_8h.html#ea44ec361097925f2994558d402988ab">xintc.h</a>, <a class="el" href="xintc_8c.html#ea44ec361097925f2994558d402988ab">xintc.c</a><li>XIntc_Disconnect()
: <a class="el" href="xintc_8h.html#8f7caaeb26b6b264fffefbd32f90f855">xintc.h</a>, <a class="el" href="xintc_8c.html#8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a><li>XIntc_Enable()
: <a class="el" href="xintc_8h.html#c7f59192d3b3ba2e2283a264677577b8">xintc.h</a>, <a class="el" href="xintc_8c.html#c7f59192d3b3ba2e2283a264677577b8">xintc.c</a><li>XIntc_GetOptions()
: <a class="el" href="xintc__options_8c.html#6fdbe96b1db87f0c78e68da8bc767a69">xintc_options.c</a>, <a class="el" href="xintc_8h.html#6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a><li>XIntc_Initialize()
: <a class="el" href="xintc_8h.html#a7adc53d40c41e1a714ef8857329043d">xintc.h</a>, <a class="el" href="xintc_8c.html#a7adc53d40c41e1a714ef8857329043d">xintc.c</a><li>XIntc_InterruptHandler()
: <a class="el" href="xintc__intr_8c.html#635187ed756cee70b4b4051560cbd7bc">xintc_intr.c</a>, <a class="el" href="xintc_8h.html#635187ed756cee70b4b4051560cbd7bc">xintc.h</a><li>XIntc_LookupConfig()
: <a class="el" href="xintc_8h.html#b2da07d4eeab07ac1ef67d56af1e1cb7">xintc.h</a>, <a class="el" href="xintc_8c.html#b2da07d4eeab07ac1ef67d56af1e1cb7">xintc.c</a><li>XIntc_LowLevelInterruptHandler()
: <a class="el" href="xintc__l_8h.html#bf91e27eb2cc036f84df2e15d14343a8">xintc_l.h</a><li>XIntc_RegisterFastHandler()
: <a class="el" href="xintc__l_8h.html#ed2ddee41f0861539f959522ce2f44af">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#ed2ddee41f0861539f959522ce2f44af">xintc_l.c</a><li>XIntc_RegisterHandler()
: <a class="el" href="xintc__l_8h.html#d1f8540fa2171b00a3af03329677f684">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#d1f8540fa2171b00a3af03329677f684">xintc_l.c</a><li>XIntc_SelfTest()
: <a class="el" href="xintc__selftest_8c.html#f9a9a16180b363930d21bc94dfe71147">xintc_selftest.c</a>, <a class="el" href="xintc_8h.html#f9a9a16180b363930d21bc94dfe71147">xintc.h</a><li>XIntc_SetIntrSvcOption()
: <a class="el" href="xintc__l_8h.html#b8e5767995d6318e6fc5cf114cda7b68">xintc_l.h</a>, <a class="el" href="xintc__l_8c.html#b8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a><li>XIntc_SetNormalIntrMode()
: <a class="el" href="xintc_8h.html#881154092f4f8cd5e29a71b284f7b2ae">xintc.h</a>, <a class="el" href="xintc_8c.html#881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a><li>XIntc_SetOptions()
: <a class="el" href="xintc__options_8c.html#1f0d32716f082a51a751df84312c7d56">xintc_options.c</a>, <a class="el" href="xintc_8h.html#1f0d32716f082a51a751df84312c7d56">xintc.h</a><li>XIntc_SimulateIntr()
: <a class="el" href="xintc__selftest_8c.html#17972363ab5a1a8f5f1d135c5b3c22c7">xintc_selftest.c</a>, <a class="el" href="xintc_8h.html#17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a><li>XIntc_Start()
: <a class="el" href="xintc_8h.html#863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.h</a>, <a class="el" href="xintc_8c.html#863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a><li>XIntc_Stop()
: <a class="el" href="xintc_8h.html#fabb05cf2e5b62031524a33d1f88f405">xintc.h</a>, <a class="el" href="xintc_8c.html#fabb05cf2e5b62031524a33d1f88f405">xintc.c</a><li>XIntc_VoidInterruptHandler()
: <a class="el" href="xintc_8h.html#9c6dc6e838193da3ce51c8cdb3b88943">xintc.h</a></ul>
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Xilinx Driver intc v3_2: Class Members
Class Members
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<li><a href="globals.html"><span>All</span></a></li>
<li><a href="globals_func.html"><span>Functions</span></a></li>
<li><a href="globals_vars.html"><span>Variables</span></a></li>
<li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
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<li>XFastInterruptHandler
: <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">xintc_l.h</a>
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Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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: <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">xintc_l.h</a></ul>
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Xilinx Driver intc v3_2: Class Members
Class Members
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&nbsp;<ul>
&nbsp;
<p>
<ul>
<li>XIntc_BitPosMask
: <a class="el" href="xintc_8c.html#af97a3c0d3620f70f2e01db3237ed5305">xintc.c</a>
, <a class="el" href="xintc__i_8h.html#af0641659204bd99e09c1511b4d39e1a4">xintc_i.h</a>
</li>
<li>XIntc_ConfigTable
: <a class="el" href="xintc__g_8c.html#a2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a>
, <a class="el" href="xintc__i_8h.html#a6afbe6b28aa729c753744cba40ecf5b3">xintc_i.h</a>
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: <a class="el" href="xintc__i_8h.html#6afbe6b28aa729c753744cba40ecf5b3">xintc_i.h</a>, <a class="el" href="xintc__g_8c.html#2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a></ul>
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Xilinx Driver intc v3_2: intc v3_2
intc v3_3
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<h1>intc v3_2</h1><p>The Xilinx interrupt controller driver component. This component supports the Xilinx interrupt controller.</p>
<p>The interrupt controller driver uses the idea of priority for the various handlers. Priority is an integer within the range of 0 and 31 inclusive with 0 being the highest priority interrupt source.</p>
<p>The Xilinx interrupt controller supports the following features:</p>
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<h1>intc v3_3</h1>
<p>
The Xilinx interrupt controller driver component. This component supports the Xilinx interrupt controller.<p>
The interrupt controller driver uses the idea of priority for the various handlers. Priority is an integer within the range of 0 and 31 inclusive with 0 being the highest priority interrupt source.<p>
The Xilinx interrupt controller supports the following features:<p>
<ul>
<li>specific individual interrupt enabling/disabling</li>
<li>specific individual interrupt acknowledging</li>
<li>attaching specific callback function to handle interrupt source</li>
<li>master enable/disable</li>
<li>single callback per interrupt or all pending interrupts handled for each interrupt of the processor</li>
</ul>
<p>The acknowledgement of the interrupt within the interrupt controller is selectable, either prior to the device's handler being called or after the handler is called. This is necessary to support interrupt signal inputs which are either edge or level signals. Edge driven interrupt signals require that the interrupt is acknowledged prior to the interrupt being serviced in order to prevent the loss of interrupts which are occurring extremely close together. A level driven interrupt input signal requires the interrupt to acknowledged after servicing the interrupt to ensure that the interrupt only generates a single interrupt condition.</p>
<p>Details about connecting the interrupt handler of the driver are contained in the source file specific to interrupt processing, <a class="el" href="xintc__intr_8c.html">xintc_intr.c</a>.</p>
<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
<p><b>Interrupt Vector Tables</b></p>
<p>The interrupt vector table for each interrupt controller device is declared statically in <a class="el" href="xintc__g_8c.html">xintc_g.c</a> within the configuration data for each instance. The device ID of the interrupt controller device is used by the driver as a direct index into the configuration data table - to retrieve the vector table for an instance of the interrupt controller. The user should populate the vector table with handlers and callbacks at run-time using the <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a> and <a class="el" href="xintc_8c.html#a8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a> functions.</p>
<p>Each vector table entry corresponds to a device that can generate an interrupt. Each entry contains an interrupt handler function and an argument to be passed to the handler when an interrupt occurs. The tools default this argument to the base address of the interrupting device. Note that the device driver interrupt handlers given in this file do not take a base address as an argument, but instead take a pointer to the driver instance. This means that although the table is created statically, the user must still use <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a> when the interrupt handler takes an argument other than the base address. This is only to say that the existence of the static vector tables should not mislead the user into thinking they no longer need to register/connect interrupt handlers with this driver.</p>
<li>specific individual interrupt enabling/disabling</li><li>specific individual interrupt acknowledging</li><li>attaching specific callback function to handle interrupt source</li><li>master enable/disable</li><li>single callback per interrupt or all pending interrupts handled for each interrupt of the processor</li></ul>
<p>
The acknowledgement of the interrupt within the interrupt controller is selectable, either prior to the device's handler being called or after the handler is called. This is necessary to support interrupt signal inputs which are either edge or level signals. Edge driven interrupt signals require that the interrupt is acknowledged prior to the interrupt being serviced in order to prevent the loss of interrupts which are occurring extremely close together. A level driven interrupt input signal requires the interrupt to acknowledged after servicing the interrupt to ensure that the interrupt only generates a single interrupt condition.<p>
Details about connecting the interrupt handler of the driver are contained in the source file specific to interrupt processing, <a class="el" href="xintc__intr_8c.html">xintc_intr.c</a>.<p>
This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.<p>
<b>Interrupt Vector Tables</b><p>
The interrupt vector table for each interrupt controller device is declared statically in <a class="el" href="xintc__g_8c.html">xintc_g.c</a> within the configuration data for each instance. The device ID of the interrupt controller device is used by the driver as a direct index into the configuration data table - to retrieve the vector table for an instance of the interrupt controller. The user should populate the vector table with handlers and callbacks at run-time using the <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a> and <a class="el" href="xintc_8c.html#8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a> functions.<p>
Each vector table entry corresponds to a device that can generate an interrupt. Each entry contains an interrupt handler function and an argument to be passed to the handler when an interrupt occurs. The tools default this argument to the base address of the interrupting device. Note that the device driver interrupt handlers given in this file do not take a base address as an argument, but instead take a pointer to the driver instance. This means that although the table is created statically, the user must still use <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a> when the interrupt handler takes an argument other than the base address. This is only to say that the existence of the static vector tables should not mislead the user into thinking they no longer need to register/connect interrupt handlers with this driver.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -------------------------------------------------------
1.00a ecm 08/16/01 First release
1.00a rpm 01/09/02 Removed the AckLocation argument from <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>.
1.00a rpm 01/09/02 Removed the AckLocation argument from <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>.
This information is now internal in <a class="el" href="xintc__g_8c.html">xintc_g.c</a>.
1.00b jhl 02/13/02 Repartitioned the driver for smaller files
1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
@ -102,9 +96,10 @@
XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
CR#765931.
Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
correctly(CR#764865).</pre><pre> <dl class="note"><dt><b>Note:</b></dt><dd>For Cascade mode, Interrupt IDs are generated in xparameters.h
correctly(CR#764865).</pre><p>
<pre><dl compact><dt><b>Note:</b></dt><dd>For Cascade mode, Interrupt IDs are generated in xparameters.h
as shown below:</dd></dl>
<p>Master/Primary INTC
Master/Primary INTC
______
| |-0 Secondary INTC
| |-. ______
@ -114,13 +109,15 @@
| |-. | |-.
|______|&lt;-63-------| |-.
| |-.
|______|-95</pre><pre> All driver functions has to be called using DeviceId/
|______|-95</pre><p>
<pre> All driver functions has to be called using DeviceId/
InstancePtr/BaseAddress of Primary/Master Controller and
Interrupts IDs generated in xparameters.h only.
Driver functions takes care of Slave Controllers based on
Interrupt ID passed. User must not use Interrupt source/ID
31 of Primary and Secondary controllers to call driver
functions.</pre><pre> For nested interrupts, XIntc_DeviceInterruptHandler saves
functions.</pre><p>
<pre> For nested interrupts, XIntc_DeviceInterruptHandler saves
microblaze r14 register on entry and restores on exit. This is
required since compiler does not support nesting. It enables
Microblaze interrupts after blocking further interrupts from
@ -136,9 +133,8 @@
3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
the test-app tcl
3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
correctly (CR#799609).</pre><pre> </pre> </div>
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correctly (CR#799609).
3.3 adk 11/3/14 added generation of C_HAS_ILR parameter to
xparameters.h.Changes are made in the driver tcl file
(CR#828046).</pre><p>
<pre> </pre> Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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<h1>XIntc Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc.html">XIntc</a>, including all inherited members.<table>
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<h1>XIntc Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc.html">XIntc</a>, including all inherited members.<p><table>
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Xilinx Driver intc v3_2: XIntc Struct Reference
XIntc Struct Reference
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<h1>XIntc Struct Reference</h1><!-- doxytag: class="XIntc" -->
<p><code>#include &lt;xintc.h&gt;</code></p>
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<h1>XIntc Struct Reference</h1><!-- doxytag: class="XIntc" --><code>#include &lt;xintc.h&gt;</code>
<p>
<a href="struct_x_intc-members.html">List of all members.</a><hr><a name="_details"></a><h2>Detailed Description</h2>
The <a class="el" href="struct_x_intc.html">XIntc</a> driver instance data. The user is required to allocate a variable of this type for every intc device in the system. A pointer to a variable of this type is then passed to the driver API functions.
<p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">BaseAddress</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">IsReady</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">IsStarted</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">UnhandledInterrupts</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">CfgPtr</a></td></tr>
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#9556236b7932be7fb353f47b8dc1dfcf">BaseAddress</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#277e8f00e1f6eb05f8097c676e826b62">IsReady</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#3e45bbc3ed1e84a8d708c25c23fa252e">IsStarted</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#bf06c903e68a5569cdf238b185d83ff5">UnhandledInterrupts</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc.html#c76bb1d794c122fdb86f8e72a9ed22fd">CfgPtr</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>The <a class="el" href="struct_x_intc.html">XIntc</a> driver instance data. The user is required to allocate a variable of this type for every intc device in the system. A pointer to a variable of this type is then passed to the driver API functions. </p>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a9556236b7932be7fb353f47b8dc1dfcf"></a><!-- doxytag: member="XIntc::BaseAddress" ref="a9556236b7932be7fb353f47b8dc1dfcf" args="" -->
<hr><h2>Member Data Documentation</h2>
<a class="anchor" name="9556236b7932be7fb353f47b8dc1dfcf"></a><!-- doxytag: member="XIntc::BaseAddress" ref="9556236b7932be7fb353f47b8dc1dfcf" args="" -->
<div class="memitem">
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<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a> </td>
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<p>Base address of registers </p>
<p>
Base address of registers
</div>
</div>
<a class="anchor" id="ac76bb1d794c122fdb86f8e72a9ed22fd"></a><!-- doxytag: member="XIntc::CfgPtr" ref="ac76bb1d794c122fdb86f8e72a9ed22fd" args="" -->
</div><p>
<a class="anchor" name="c76bb1d794c122fdb86f8e72a9ed22fd"></a><!-- doxytag: member="XIntc::CfgPtr" ref="c76bb1d794c122fdb86f8e72a9ed22fd" args="" -->
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>* <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a></td>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>* <a class="el" href="struct_x_intc.html#c76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Pointer to instance config entry </p>
<p>
Pointer to instance config entry
</div>
</div>
<a class="anchor" id="a277e8f00e1f6eb05f8097c676e826b62"></a><!-- doxytag: member="XIntc::IsReady" ref="a277e8f00e1f6eb05f8097c676e826b62" args="" -->
</div><p>
<a class="anchor" name="277e8f00e1f6eb05f8097c676e826b62"></a><!-- doxytag: member="XIntc::IsReady" ref="277e8f00e1f6eb05f8097c676e826b62" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Device is initialized and ready </p>
<p>
Device is initialized and ready
</div>
</div>
<a class="anchor" id="a3e45bbc3ed1e84a8d708c25c23fa252e"></a><!-- doxytag: member="XIntc::IsStarted" ref="a3e45bbc3ed1e84a8d708c25c23fa252e" args="" -->
</div><p>
<a class="anchor" name="3e45bbc3ed1e84a8d708c25c23fa252e"></a><!-- doxytag: member="XIntc::IsStarted" ref="3e45bbc3ed1e84a8d708c25c23fa252e" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc::IsStarted</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#3e45bbc3ed1e84a8d708c25c23fa252e">XIntc::IsStarted</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Device has been started </p>
<p>
Device has been started
</div>
</div>
<a class="anchor" id="abf06c903e68a5569cdf238b185d83ff5"></a><!-- doxytag: member="XIntc::UnhandledInterrupts" ref="abf06c903e68a5569cdf238b185d83ff5" args="" -->
</div><p>
<a class="anchor" name="bf06c903e68a5569cdf238b185d83ff5"></a><!-- doxytag: member="XIntc::UnhandledInterrupts" ref="bf06c903e68a5569cdf238b185d83ff5" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">XIntc::UnhandledInterrupts</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc.html#bf06c903e68a5569cdf238b185d83ff5">XIntc::UnhandledInterrupts</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Intc Statistics </p>
<p>
Intc Statistics
</div>
</div>
<hr/>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc_8h.html">xintc.h</a></li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc_8h.html">xintc.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: Member List
Member List
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<h1>XIntc_Config Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc___config.html">XIntc_Config</a>, including all inherited members.<table>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">AckBeforeService</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">BaseAddress</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">DeviceId</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">FastIntr</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">HandlerTable</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">IntcType</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">IntVectorAddr</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">NumberofIntrs</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">Options</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
</table></div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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<h1>XIntc_Config Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc___config.html">XIntc_Config</a>, including all inherited members.<p><table>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#172cd1cd58904502d6f3cec734db1d6b">AckBeforeService</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#c0e28544f1ed2f06eda35ba9089e639f">BaseAddress</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#1d58e4660c1f0727b1b29497b050cc2c">DeviceId</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#c894d2be382d08d83821c1672615d4d4">FastIntr</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#f62197288a9019af6084a1675844e1ca">HandlerTable</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#e54682e47e6e506a52c7b6da6314a29a">IntcType</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#3680484ddceab0bc26f7a4ac2e3b7852">IntVectorAddr</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#6e2fc4f937193eb9e665a2e66af97db2">NumberofIntrs</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___config.html#c3efdbf93e34b88aedead2e7ca44cee1">Options</a></td><td><a class="el" href="struct_x_intc___config.html">XIntc_Config</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: XIntc_Config Struct Reference
XIntc_Config Struct Reference
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<h1>XIntc_Config Struct Reference</h1><!-- doxytag: class="XIntc_Config" -->
<p><code>#include &lt;xintc.h&gt;</code></p>
<p><a href="struct_x_intc___config-members.html">List of all members.</a></p>
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<h1>XIntc_Config Struct Reference</h1><!-- doxytag: class="XIntc_Config" --><code>#include &lt;xintc.h&gt;</code>
<p>
<a href="struct_x_intc___config-members.html">List of all members.</a><hr><a name="_details"></a><h2>Detailed Description</h2>
This typedef contains configuration information for the device.
<p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u16&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">DeviceId</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">BaseAddress</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">AckBeforeService</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">FastIntr</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">IntVectorAddr</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">NumberofIntrs</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">Options</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">IntcType</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">HandlerTable</a> [XPAR_INTC_MAX_NUM_INTR_INPUTS]</td></tr>
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u16&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#1d58e4660c1f0727b1b29497b050cc2c">DeviceId</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#c0e28544f1ed2f06eda35ba9089e639f">BaseAddress</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#172cd1cd58904502d6f3cec734db1d6b">AckBeforeService</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#c894d2be382d08d83821c1672615d4d4">FastIntr</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#3680484ddceab0bc26f7a4ac2e3b7852">IntVectorAddr</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#6e2fc4f937193eb9e665a2e66af97db2">NumberofIntrs</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#c3efdbf93e34b88aedead2e7ca44cee1">Options</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#e54682e47e6e506a52c7b6da6314a29a">IntcType</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___config.html#f62197288a9019af6084a1675844e1ca">HandlerTable</a> [XPAR_INTC_MAX_NUM_INTR_INPUTS]</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This typedef contains configuration information for the device. </p>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a172cd1cd58904502d6f3cec734db1d6b"></a><!-- doxytag: member="XIntc_Config::AckBeforeService" ref="a172cd1cd58904502d6f3cec734db1d6b" args="" -->
<hr><h2>Member Data Documentation</h2>
<a class="anchor" name="172cd1cd58904502d6f3cec734db1d6b"></a><!-- doxytag: member="XIntc_Config::AckBeforeService" ref="172cd1cd58904502d6f3cec734db1d6b" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config::AckBeforeService</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#172cd1cd58904502d6f3cec734db1d6b">XIntc_Config::AckBeforeService</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Ack location per interrupt </p>
<p>
Ack location per interrupt
</div>
</div>
<a class="anchor" id="ac0e28544f1ed2f06eda35ba9089e639f"></a><!-- doxytag: member="XIntc_Config::BaseAddress" ref="ac0e28544f1ed2f06eda35ba9089e639f" args="" -->
</div><p>
<a class="anchor" name="c0e28544f1ed2f06eda35ba9089e639f"></a><!-- doxytag: member="XIntc_Config::BaseAddress" ref="c0e28544f1ed2f06eda35ba9089e639f" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#c0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Register base address </p>
<p>
Register base address
</div>
</div>
<a class="anchor" id="a1d58e4660c1f0727b1b29497b050cc2c"></a><!-- doxytag: member="XIntc_Config::DeviceId" ref="a1d58e4660c1f0727b1b29497b050cc2c" args="" -->
</div><p>
<a class="anchor" name="1d58e4660c1f0727b1b29497b050cc2c"></a><!-- doxytag: member="XIntc_Config::DeviceId" ref="1d58e4660c1f0727b1b29497b050cc2c" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u16 <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config::DeviceId</a></td>
<td class="memname">u16 <a class="el" href="struct_x_intc___config.html#1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config::DeviceId</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Unique ID of device </p>
<p>
Unique ID of device
</div>
</div>
<a class="anchor" id="ac894d2be382d08d83821c1672615d4d4"></a><!-- doxytag: member="XIntc_Config::FastIntr" ref="ac894d2be382d08d83821c1672615d4d4" args="" -->
</div><p>
<a class="anchor" name="c894d2be382d08d83821c1672615d4d4"></a><!-- doxytag: member="XIntc_Config::FastIntr" ref="c894d2be382d08d83821c1672615d4d4" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a></td>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#c894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Fast Interrupt enabled </p>
<p>
Fast Interrupt enabled
</div>
</div>
<a class="anchor" id="af62197288a9019af6084a1675844e1ca"></a><!-- doxytag: member="XIntc_Config::HandlerTable" ref="af62197288a9019af6084a1675844e1ca" args="[XPAR_INTC_MAX_NUM_INTR_INPUTS]" -->
</div><p>
<a class="anchor" name="f62197288a9019af6084a1675844e1ca"></a><!-- doxytag: member="XIntc_Config::HandlerTable" ref="f62197288a9019af6084a1675844e1ca" args="[XPAR_INTC_MAX_NUM_INTR_INPUTS]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a> <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>[XPAR_INTC_MAX_NUM_INTR_INPUTS]</td>
<td class="memname"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a> <a class="el" href="struct_x_intc___config.html#f62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>[XPAR_INTC_MAX_NUM_INTR_INPUTS] </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Static vector table of interrupt handlers </p>
<p>
Static vector table of interrupt handlers
</div>
</div>
<a class="anchor" id="ae54682e47e6e506a52c7b6da6314a29a"></a><!-- doxytag: member="XIntc_Config::IntcType" ref="ae54682e47e6e506a52c7b6da6314a29a" args="" -->
</div><p>
<a class="anchor" name="e54682e47e6e506a52c7b6da6314a29a"></a><!-- doxytag: member="XIntc_Config::IntcType" ref="e54682e47e6e506a52c7b6da6314a29a" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a></td>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#e54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Intc type 0 - No Cascade Mode 1 - primary instance 2 - secondary instance 3 - last instance </p>
<p>
Intc type 0 - No Cascade Mode 1 - primary instance 2 - secondary instance 3 - last instance
</div>
</div>
<a class="anchor" id="a3680484ddceab0bc26f7a4ac2e3b7852"></a><!-- doxytag: member="XIntc_Config::IntVectorAddr" ref="a3680484ddceab0bc26f7a4ac2e3b7852" args="" -->
</div><p>
<a class="anchor" name="3680484ddceab0bc26f7a4ac2e3b7852"></a><!-- doxytag: member="XIntc_Config::IntVectorAddr" ref="3680484ddceab0bc26f7a4ac2e3b7852" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config::IntVectorAddr</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config::IntVectorAddr</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Interrupt Vector Address </p>
<p>
Interrupt Vector Address
</div>
</div>
<a class="anchor" id="a6e2fc4f937193eb9e665a2e66af97db2"></a><!-- doxytag: member="XIntc_Config::NumberofIntrs" ref="a6e2fc4f937193eb9e665a2e66af97db2" args="" -->
</div><p>
<a class="anchor" name="6e2fc4f937193eb9e665a2e66af97db2"></a><!-- doxytag: member="XIntc_Config::NumberofIntrs" ref="6e2fc4f937193eb9e665a2e66af97db2" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config::NumberofIntrs</a></td>
<td class="memname">int <a class="el" href="struct_x_intc___config.html#6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config::NumberofIntrs</a> </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Number of Interrupt sources </p>
<p>
Number of Interrupt sources
</div>
</div>
<a class="anchor" id="ac3efdbf93e34b88aedead2e7ca44cee1"></a><!-- doxytag: member="XIntc_Config::Options" ref="ac3efdbf93e34b88aedead2e7ca44cee1" args="" -->
</div><p>
<a class="anchor" name="c3efdbf93e34b88aedead2e7ca44cee1"></a><!-- doxytag: member="XIntc_Config::Options" ref="c3efdbf93e34b88aedead2e7ca44cee1" args="" -->
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<div class="memproto">
<table class="memname">
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<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a></td>
<td class="memname">u32 <a class="el" href="struct_x_intc___config.html#c3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a> </td>
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<div class="memdoc">
<p>Device options </p>
<p>
Device options
</div>
</div>
<hr/>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc_8h.html">xintc.h</a></li>
</ul>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
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</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc_8h.html">xintc.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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<h1>XIntc_VectorTableEntry Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a>, including all inherited members.<table>
<tr class="memlist"><td><a class="el" href="struct_x_intc___vector_table_entry.html#a8badf1d4125bbca6d53404610eb813bc">CallBackRef</a></td><td><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_intc___vector_table_entry.html#a509bc8e96a0777dd929fdece614fe611">Handler</a></td><td><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td><td></td></tr>
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<h1>XIntc_VectorTableEntry Member List</h1>This is the complete list of members for <a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a>, including all inherited members.<p><table>
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<tr class="memlist"><td><a class="el" href="struct_x_intc___vector_table_entry.html#509bc8e96a0777dd929fdece614fe611">Handler</a></td><td><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td><td></td></tr>
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Xilinx Driver intc v3_2: XIntc_VectorTableEntry Struct Reference
XIntc_VectorTableEntry Struct Reference
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<h1>XIntc_VectorTableEntry Struct Reference</h1><!-- doxytag: class="XIntc_VectorTableEntry" --><code>#include &lt;xintc_l.h&gt;</code>
<p>
<a href="struct_x_intc___vector_table_entry-members.html">List of all members.</a><table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">XInterruptHandler&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html#509bc8e96a0777dd929fdece614fe611">Handler</a></td></tr>
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<h1>XIntc_VectorTableEntry Struct Reference</h1><!-- doxytag: class="XIntc_VectorTableEntry" -->
<p><code>#include &lt;xintc_l.h&gt;</code></p>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html#8badf1d4125bbca6d53404610eb813bc">CallBackRef</a></td></tr>
<p><a href="struct_x_intc___vector_table_entry-members.html">List of all members.</a></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">XInterruptHandler&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html#a509bc8e96a0777dd929fdece614fe611">Handler</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html#a8badf1d4125bbca6d53404610eb813bc">CallBackRef</a></td></tr>
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<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a8badf1d4125bbca6d53404610eb813bc"></a><!-- doxytag: member="XIntc_VectorTableEntry::CallBackRef" ref="a8badf1d4125bbca6d53404610eb813bc" args="" -->
<hr><h2>Member Data Documentation</h2>
<a class="anchor" name="8badf1d4125bbca6d53404610eb813bc"></a><!-- doxytag: member="XIntc_VectorTableEntry::CallBackRef" ref="8badf1d4125bbca6d53404610eb813bc" args="" -->
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<td class="memname">void* <a class="el" href="struct_x_intc___vector_table_entry.html#a8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry::CallBackRef</a></td>
<td class="memname">void* <a class="el" href="struct_x_intc___vector_table_entry.html#8badf1d4125bbca6d53404610eb813bc">XIntc_VectorTableEntry::CallBackRef</a> </td>
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<a class="anchor" id="a509bc8e96a0777dd929fdece614fe611"></a><!-- doxytag: member="XIntc_VectorTableEntry::Handler" ref="a509bc8e96a0777dd929fdece614fe611" args="" -->
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<a class="anchor" name="509bc8e96a0777dd929fdece614fe611"></a><!-- doxytag: member="XIntc_VectorTableEntry::Handler" ref="509bc8e96a0777dd929fdece614fe611" args="" -->
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<td class="memname">XInterruptHandler <a class="el" href="struct_x_intc___vector_table_entry.html#a509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry::Handler</a></td>
<td class="memname">XInterruptHandler <a class="el" href="struct_x_intc___vector_table_entry.html#509bc8e96a0777dd929fdece614fe611">XIntc_VectorTableEntry::Handler</a> </td>
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</div>
<hr/>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc__l_8h.html">xintc_l.h</a></li>
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Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xintc__l_8h.html">xintc_l.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: xintc.c File Reference
xintc.c File Reference
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<h1>xintc.c File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#aa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u16 DeviceId)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Mode)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#afabb05cf2e5b62031524a33d1f88f405">XIntc_Stop</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">XIntc_Connect</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#ac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#aea44ec361097925f2994558d402988ab">XIntc_Disable</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#ab2da07d4eeab07ac1ef67d56af1e1cb7">XIntc_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a> Handler)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td colspan="2"><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#af97a3c0d3620f70f2e01db3237ed5305">XIntc_BitPosMask</a> [XIN_CONTROLLER_MAX_INTRS]</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Contains required functions for the <a class="el" href="struct_x_intc.html">XIntc</a> driver for the Xilinx Interrupt Controller. See <a class="el" href="xintc_8h.html">xintc.h</a> for a detailed description of the driver.</p>
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<h1>xintc.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
Contains required functions for the <a class="el" href="struct_x_intc.html">XIntc</a> driver for the Xilinx Interrupt Controller. See <a class="el" href="xintc_8h.html">xintc.h</a> for a detailed description of the driver.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- --------------------------------------------------------
1.00a ecm 08/16/01 First release
1.00b jhl 02/21/02 Repartitioned the driver for smaller files
@ -79,13 +53,50 @@
Added XIntc_InitializeSlaves API.
3.0 bss 01/28/13 Modified to initialize IVAR register with
XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
CR#765931</pre><pre> </pre> <hr/><h2>Function Documentation</h2>
<a class="anchor" id="a8604653ac3a24bbb49c5fecb6a9ebfc7"></a><!-- doxytag: member="xintc.c::XIntc_Acknowledge" ref="a8604653ac3a24bbb49c5fecb6a9ebfc7" args="(XIntc *InstancePtr, u8 Id)" -->
CR#765931</pre><p>
<pre> </pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#a7adc53d40c41e1a714ef8857329043d">XIntc_Initialize</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u16 DeviceId)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Mode)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#fabb05cf2e5b62031524a33d1f88f405">XIntc_Stop</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">XIntc_Connect</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#c7f59192d3b3ba2e2283a264677577b8">XIntc_Enable</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#ea44ec361097925f2994558d402988ab">XIntc_Disable</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#b2da07d4eeab07ac1ef67d56af1e1cb7">XIntc_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a> Handler)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc_8c.html#f97a3c0d3620f70f2e01db3237ed5305">XIntc_BitPosMask</a> [XIN_CONTROLLER_MAX_INTRS]</td></tr>
</table>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="8604653ac3a24bbb49c5fecb6a9ebfc7"></a><!-- doxytag: member="xintc.c::XIntc_Acknowledge" ref="8604653ac3a24bbb49c5fecb6a9ebfc7" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">void XIntc_Acknowledge </td>
<td class="memname">void XIntc_Acknowledge </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -99,30 +110,31 @@
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<td></td>
<td>)</td>
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<p>Acknowledges the interrupt source provided as the argument Id. When the interrupt is acknowledged, it causes the interrupt controller to clear its interrupt condition.In Cascade mode, acknowledges corresponding interrupt source of Slave controllers depending on the Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Acknowledges the interrupt source provided as the argument Id. When the interrupt is acknowledged, it causes the interrupt controller to clear its interrupt condition.In Cascade mode, acknowledges corresponding interrupt source of Slave controllers depending on the Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="aee9ec5873a764994d64b4da35a110084"></a><!-- doxytag: member="xintc.c::XIntc_Connect" ref="aee9ec5873a764994d64b4da35a110084" args="(XIntc *InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef)" -->
</div><p>
<a class="anchor" name="ee9ec5873a764994d64b4da35a110084"></a><!-- doxytag: member="xintc.c::XIntc_Connect" ref="ee9ec5873a764994d64b4da35a110084" args="(XIntc *InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef)" -->
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<td class="memname">int XIntc_Connect </td>
<td class="memname">int XIntc_Connect </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -148,36 +160,36 @@
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<td>)</td>
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<p>Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. The argument provided in this call as the Callbackref is used as the argument for the handler when it is called. In Cascade mode, connects handler to Slave controller handler table depending on the interrupt Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. The argument provided in this call as the Callbackref is used as the argument for the handler when it is called. In Cascade mode, connects handler to Slave controller handler table depending on the interrupt Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Handler</em>&nbsp;</td><td>to the handler for that interrupt. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>CallBackRef</em>&nbsp;</td><td>is the callback reference, usually the instance pointer of the connecting driver.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd></dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd></dd></dl>
<ul>
<li>XST_SUCCESS if the handler was connected correctly.</li>
</ul>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>
<li>XST_SUCCESS if the handler was connected correctly.</li></ul>
<p>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
WARNING: The handler provided as an argument will overwrite any handler that was previously connected.
</div>
</div>
<a class="anchor" id="a24a344d15b12b8acd82cd4c49a020d74"></a><!-- doxytag: member="xintc.c::XIntc_ConnectFastHandler" ref="a24a344d15b12b8acd82cd4c49a020d74" args="(XIntc *InstancePtr, u8 Id, XFastInterruptHandler Handler)" -->
</div><p>
<a class="anchor" name="24a344d15b12b8acd82cd4c49a020d74"></a><!-- doxytag: member="xintc.c::XIntc_ConnectFastHandler" ref="24a344d15b12b8acd82cd4c49a020d74" args="(XIntc *InstancePtr, u8 Id, XFastInterruptHandler Handler)" -->
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<td class="memname">int XIntc_ConnectFastHandler </td>
<td class="memname">int XIntc_ConnectFastHandler </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -191,41 +203,40 @@
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramtype"><a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramname"> <em>Handler</em></td><td>&nbsp;</td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
<td></td><td></td><td width="100%"></td>
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<div class="memdoc">
<p>Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.In Cascade mode, connects handler to corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as fast interrupts.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.In Cascade mode, connects handler to corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as fast interrupts.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Handler</em>&nbsp;</td><td>to the handler for that interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS</li>
</ul>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported</dd></dl>
<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>
<dl compact><dt><b>Note:</b></dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported</dd></dl>
WARNING: The handler provided as an argument will overwrite any handler that was previously connected.
</div>
</div>
<a class="anchor" id="aea44ec361097925f2994558d402988ab"></a><!-- doxytag: member="xintc.c::XIntc_Disable" ref="aea44ec361097925f2994558d402988ab" args="(XIntc *InstancePtr, u8 Id)" -->
</div><p>
<a class="anchor" name="ea44ec361097925f2994558d402988ab"></a><!-- doxytag: member="xintc.c::XIntc_Disable" ref="ea44ec361097925f2994558d402988ab" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">void XIntc_Disable </td>
<td class="memname">void XIntc_Disable </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -239,30 +250,31 @@
<tr>
<td></td>
<td>)</td>
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<div class="memdoc">
<p>Disables the interrupt source provided as the argument Id such that the interrupt controller will not cause interrupts for the specified Id. The interrupt controller will continue to hold an interrupt condition for the Id, but will not cause an interrupt.In Cascade mode, disables corresponding interrupt of Slave controllers depending on the Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Disables the interrupt source provided as the argument Id such that the interrupt controller will not cause interrupts for the specified Id. The interrupt controller will continue to hold an interrupt condition for the Id, but will not cause an interrupt.In Cascade mode, disables corresponding interrupt of Slave controllers depending on the Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="a8f7caaeb26b6b264fffefbd32f90f855"></a><!-- doxytag: member="xintc.c::XIntc_Disconnect" ref="a8f7caaeb26b6b264fffefbd32f90f855" args="(XIntc *InstancePtr, u8 Id)" -->
</div><p>
<a class="anchor" name="8f7caaeb26b6b264fffefbd32f90f855"></a><!-- doxytag: member="xintc.c::XIntc_Disconnect" ref="8f7caaeb26b6b264fffefbd32f90f855" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">void XIntc_Disconnect </td>
<td class="memname">void XIntc_Disconnect </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -276,30 +288,31 @@
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<td></td>
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<div class="memdoc">
<p>Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Id. This effectively disconnects that interrupt source from any handler. The interrupt is disabled also. In Cascade mode, disconnects handler from Slave controller handler table depending on the interrupt Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Id. This effectively disconnects that interrupt source from any handler. The interrupt is disabled also. In Cascade mode, disconnects handler from Slave controller handler table depending on the interrupt Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="ac7f59192d3b3ba2e2283a264677577b8"></a><!-- doxytag: member="xintc.c::XIntc_Enable" ref="ac7f59192d3b3ba2e2283a264677577b8" args="(XIntc *InstancePtr, u8 Id)" -->
</div><p>
<a class="anchor" name="c7f59192d3b3ba2e2283a264677577b8"></a><!-- doxytag: member="xintc.c::XIntc_Enable" ref="c7f59192d3b3ba2e2283a264677577b8" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">void XIntc_Enable </td>
<td class="memname">void XIntc_Enable </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
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<p>Enables the interrupt source provided as the argument Id. Any pending interrupt condition for the specified Id will occur after this function is called. In Cascade mode, enables corresponding interrupt of Slave controllers depending on the Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Enables the interrupt source provided as the argument Id. Any pending interrupt condition for the specified Id will occur after this function is called. In Cascade mode, enables corresponding interrupt of Slave controllers depending on the Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="aa7adc53d40c41e1a714ef8857329043d"></a><!-- doxytag: member="xintc.c::XIntc_Initialize" ref="aa7adc53d40c41e1a714ef8857329043d" args="(XIntc *InstancePtr, u16 DeviceId)" -->
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<a class="anchor" name="a7adc53d40c41e1a714ef8857329043d"></a><!-- doxytag: member="xintc.c::XIntc_Initialize" ref="a7adc53d40c41e1a714ef8857329043d" args="(XIntc *InstancePtr, u16 DeviceId)" -->
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<td class="memname">int XIntc_Initialize </td>
<td class="memname">int XIntc_Initialize </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
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<p>Initialize a specific interrupt controller instance/driver. The initialization entails:</p>
<p>
Initialize a specific interrupt controller instance/driver. The initialization entails:<p>
<ul>
<li>Initialize fields of the <a class="el" href="struct_x_intc.html">XIntc</a> structure</li>
<li>Initial vector table with stub function calls</li>
<li>All interrupt sources are disabled</li>
<li>Interrupt output is disabled</li>
</ul>
<dl><dt><b>Parameters:</b></dt><dd>
<li>Initialize fields of the <a class="el" href="struct_x_intc.html">XIntc</a> structure</li><li>Initial vector table with stub function calls</li><li>All interrupt sources are disabled</li><li>Interrupt output is disabled</li></ul>
<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>DeviceId</em>&nbsp;</td><td>is the unique id of the device controlled by this <a class="el" href="struct_x_intc.html">XIntc</a> instance. Passing in a device id associates the generic <a class="el" href="struct_x_intc.html">XIntc</a> instance to a specific device, as chosen by the caller or application developer.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if initialization was successful</li>
<li>XST_DEVICE_IS_STARTED if the device has already been started</li>
<li>XST_DEVICE_NOT_FOUND if device configuration information was not found for a device with the supplied device ID.</li>
</ul>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if initialization was successful</li><li>XST_DEVICE_IS_STARTED if the device has already been started</li><li>XST_DEVICE_NOT_FOUND if device configuration information was not found for a device with the supplied device ID.</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>In Cascade mode this function calls XIntc_InitializeSlaves to initialiaze Slave Interrupt controllers. </dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>In Cascade mode this function calls XIntc_InitializeSlaves to initialiaze Slave Interrupt controllers. </dd></dl>
</div>
</div>
<a class="anchor" id="ab2da07d4eeab07ac1ef67d56af1e1cb7"></a><!-- doxytag: member="xintc.c::XIntc_LookupConfig" ref="ab2da07d4eeab07ac1ef67d56af1e1cb7" args="(u16 DeviceId)" -->
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<a class="anchor" name="b2da07d4eeab07ac1ef67d56af1e1cb7"></a><!-- doxytag: member="xintc.c::XIntc_LookupConfig" ref="b2da07d4eeab07ac1ef67d56af1e1cb7" args="(u16 DeviceId)" -->
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<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>* XIntc_LookupConfig </td>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>* XIntc_LookupConfig </td>
<td>(</td>
<td class="paramtype">u16&nbsp;</td>
<td class="paramname"> <em>DeviceId</em></td>
<td class="paramname"> <em>DeviceId</em> </td>
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<p>Looks up the device configuration based on the unique device ID. A table contains the configuration info for each device in the system.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Looks up the device configuration based on the unique device ID. A table contains the configuration info for each device in the system.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>DeviceId</em>&nbsp;</td><td>is the unique identifier for a device.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>A pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> configuration structure for the specified device, or NULL if the device was not found.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>A pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> configuration structure for the specified device, or NULL if the device was not found.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="a881154092f4f8cd5e29a71b284f7b2ae"></a><!-- doxytag: member="xintc.c::XIntc_SetNormalIntrMode" ref="a881154092f4f8cd5e29a71b284f7b2ae" args="(XIntc *InstancePtr, u8 Id)" -->
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<a class="anchor" name="881154092f4f8cd5e29a71b284f7b2ae"></a><!-- doxytag: member="xintc.c::XIntc_SetNormalIntrMode" ref="881154092f4f8cd5e29a71b284f7b2ae" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">void XIntc_SetNormalIntrMode </td>
<td class="memname">void XIntc_SetNormalIntrMode </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -425,30 +435,31 @@
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<p>Sets the normal interrupt mode for the specified interrupt in the Interrupt Mode Register. In Cascade mode disconnects handler from corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as normal interrupts.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Sets the normal interrupt mode for the specified interrupt in the Interrupt Mode Register. In Cascade mode disconnects handler from corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as normal interrupts.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported </dd></dl>
</div>
</div>
<a class="anchor" id="a863eb58a3ae9419c7ac5da7c9fa9cb50"></a><!-- doxytag: member="xintc.c::XIntc_Start" ref="a863eb58a3ae9419c7ac5da7c9fa9cb50" args="(XIntc *InstancePtr, u8 Mode)" -->
</div><p>
<a class="anchor" name="863eb58a3ae9419c7ac5da7c9fa9cb50"></a><!-- doxytag: member="xintc.c::XIntc_Start" ref="863eb58a3ae9419c7ac5da7c9fa9cb50" args="(XIntc *InstancePtr, u8 Mode)" -->
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<td class="memname">int XIntc_Start </td>
<td class="memname">int XIntc_Start </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -462,78 +473,73 @@
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<p>Starts the interrupt controller by enabling the output from the controller to the processor. Interrupts may be generated by the interrupt controller after this function is called.</p>
<p>It is necessary for the caller to connect the interrupt handler of this component to the proper interrupt source. This function also starts Slave controllers in Cascade mode.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Starts the interrupt controller by enabling the output from the controller to the processor. Interrupts may be generated by the interrupt controller after this function is called.<p>
It is necessary for the caller to connect the interrupt handler of this component to the proper interrupt source. This function also starts Slave controllers in Cascade mode.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Mode</em>&nbsp;</td><td>determines if software is allowed to simulate interrupts or real interrupts are allowed to occur. Note that these modes are mutually exclusive. The interrupt controller hardware resets in a mode that allows software to simulate interrupts until this mode is exited. It cannot be reentered once it has been exited.</td></tr>
</table>
</dd>
</dl>
<p>One of the following values should be used for the mode.</p>
<ul>
<li>XIN_SIMULATION_MODE enables simulation of interrupts only</li>
<li>XIN_REAL_MODE enables hardware interrupts only</li>
</ul>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the device was started successfully</li>
<li>XST_FAILURE if simulation mode was specified and it could not be set because real mode has already been entered.</li>
</ul>
One of the following values should be used for the mode.<ul>
<li>XIN_SIMULATION_MODE enables simulation of interrupts only</li><li>XIN_REAL_MODE enables hardware interrupts only</li></ul>
<p>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the device was started successfully</li><li>XST_FAILURE if simulation mode was specified and it could not be set because real mode has already been entered.</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>Must be called after <a class="el" href="struct_x_intc.html">XIntc</a> initialization is completed. </dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>Must be called after <a class="el" href="struct_x_intc.html">XIntc</a> initialization is completed. </dd></dl>
</div>
</div>
<a class="anchor" id="afabb05cf2e5b62031524a33d1f88f405"></a><!-- doxytag: member="xintc.c::XIntc_Stop" ref="afabb05cf2e5b62031524a33d1f88f405" args="(XIntc *InstancePtr)" -->
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<a class="anchor" name="fabb05cf2e5b62031524a33d1f88f405"></a><!-- doxytag: member="xintc.c::XIntc_Stop" ref="fabb05cf2e5b62031524a33d1f88f405" args="(XIntc *InstancePtr)" -->
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<td class="memname">void XIntc_Stop </td>
<td class="memname">void XIntc_Stop </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em></td>
<td class="paramname"> <em>InstancePtr</em> </td>
<td>&nbsp;)&nbsp;</td>
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<p>Stops the interrupt controller by disabling the output from the controller so that no interrupts will be caused by the interrupt controller.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Stops the interrupt controller by disabling the output from the controller so that no interrupts will be caused by the interrupt controller.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<hr/><h2>Variable Documentation</h2>
<a class="anchor" id="af97a3c0d3620f70f2e01db3237ed5305"></a><!-- doxytag: member="xintc.c::XIntc_BitPosMask" ref="af97a3c0d3620f70f2e01db3237ed5305" args="[XIN_CONTROLLER_MAX_INTRS]" -->
</div><p>
<hr><h2>Variable Documentation</h2>
<a class="anchor" name="f97a3c0d3620f70f2e01db3237ed5305"></a><!-- doxytag: member="xintc.c::XIntc_BitPosMask" ref="f97a3c0d3620f70f2e01db3237ed5305" args="[XIN_CONTROLLER_MAX_INTRS]" -->
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<td class="memname">u32 <a class="el" href="xintc__i_8h.html#af0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a>[XIN_CONTROLLER_MAX_INTRS]</td>
<td class="memname">u32 <a class="el" href="xintc__i_8h.html#f0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a>[XIN_CONTROLLER_MAX_INTRS] </td>
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<p>
</div>
</div>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
</div><p>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: xintc_g.c File Reference
xintc_g.c File Reference
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<h1>xintc_g.c File Reference</h1><code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<code>#include &quot;xparameters.h&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__g_8c.html#a2187e69fdc39ef945a992d2602d0c1c1">XIntc_ConfigTable</a> [XPAR_XINTC_NUM_INSTANCES]</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This file contains a configuration table that specifies the configuration of interrupt controller devices in the system.</p>
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<h1>xintc_g.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
This file contains a configuration table that specifies the configuration of interrupt controller devices in the system.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a rpm 01/09/02 First release
1.00b jhl 02/21/02 Repartitioned the driver for smaller files
@ -44,17 +33,29 @@
1.00c rpm 10/17/03 New release. Support the static vector table created
in the <a class="el" href="xintc__g_8c.html">xintc_g.c</a> configuration table.
1.10c mta 03/21/07 Updated to new coding style
</pre> <hr/><h2>Variable Documentation</h2>
<a class="anchor" id="a2187e69fdc39ef945a992d2602d0c1c1"></a><!-- doxytag: member="xintc_g.c::XIntc_ConfigTable" ref="a2187e69fdc39ef945a992d2602d0c1c1" args="[XPAR_XINTC_NUM_INSTANCES]" -->
</pre>
<p>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<code>#include &quot;xparameters.h&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__g_8c.html#2187e69fdc39ef945a992d2602d0c1c1">XIntc_ConfigTable</a> [XPAR_XINTC_NUM_INSTANCES]</td></tr>
</table>
<hr><h2>Variable Documentation</h2>
<a class="anchor" name="2187e69fdc39ef945a992d2602d0c1c1"></a><!-- doxytag: member="xintc_g.c::XIntc_ConfigTable" ref="2187e69fdc39ef945a992d2602d0c1c1" args="[XPAR_XINTC_NUM_INSTANCES]" -->
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<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> <a class="el" href="xintc__i_8h.html#a6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a>[XPAR_XINTC_NUM_INSTANCES]</td>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> <a class="el" href="xintc__i_8h.html#6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a>[XPAR_XINTC_NUM_INSTANCES] </td>
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<div class="memdoc">
<p>
<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
{
XPAR_INTC_0_DEVICE_ID,
@ -70,14 +71,8 @@
0
}
}
</pre></div><p>This table contains configuration information for each intc device in the system. The <a class="el" href="struct_x_intc.html">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_intc___config.html">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized. </p>
</pre></div>This table contains configuration information for each intc device in the system. The <a class="el" href="struct_x_intc.html">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.<p>
Refer to the <a class="el" href="struct_x_intc___config.html">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized.
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Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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Xilinx Driver intc v3_2: xintc_i.h File Reference
xintc_i.h File Reference
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<h1>xintc_i.h File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#a2d461c0e2b7ab3d3106575c4c3a5adff">XINTC_I_H</a></td></tr>
<tr><td colspan="2"><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#af0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a> []</td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#a6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a> []</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This file contains data which is shared between files and internal to the <a class="el" href="struct_x_intc.html">XIntc</a> component. It is intended for internal use only.</p>
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<h1>xintc_i.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
This file contains data which is shared between files and internal to the <a class="el" href="struct_x_intc.html">XIntc</a> component. It is intended for internal use only.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -------------------------------------------------------
1.00b jhl 02/06/02 First release
1.00b jhl 04/24/02 Moved register definitions to <a class="el" href="xintc__l_8h.html">xintc_l.h</a>
@ -48,53 +33,68 @@
pointer.
1.10c mta 03/21/07 Updated to new coding style
2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
</pre> <hr/><h2>Define Documentation</h2>
<a class="anchor" id="a2d461c0e2b7ab3d3106575c4c3a5adff"></a><!-- doxytag: member="xintc_i.h::XINTC_I_H" ref="a2d461c0e2b7ab3d3106575c4c3a5adff" args="" -->
</pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#2d461c0e2b7ab3d3106575c4c3a5adff">XINTC_I_H</a></td></tr>
<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#f0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a> []</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__i_8h.html#6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a> []</td></tr>
</table>
<hr><h2>Define Documentation</h2>
<a class="anchor" name="2d461c0e2b7ab3d3106575c4c3a5adff"></a><!-- doxytag: member="xintc_i.h::XINTC_I_H" ref="2d461c0e2b7ab3d3106575c4c3a5adff" args="" -->
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<td class="memname">#define XINTC_I_H</td>
<td class="memname">#define XINTC_I_H </td>
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<div class="memdoc">
<p>
</div>
</div>
<hr/><h2>Variable Documentation</h2>
<a class="anchor" id="af0641659204bd99e09c1511b4d39e1a4"></a><!-- doxytag: member="xintc_i.h::XIntc_BitPosMask" ref="af0641659204bd99e09c1511b4d39e1a4" args="[]" -->
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<hr><h2>Variable Documentation</h2>
<a class="anchor" name="f0641659204bd99e09c1511b4d39e1a4"></a><!-- doxytag: member="xintc_i.h::XIntc_BitPosMask" ref="f0641659204bd99e09c1511b4d39e1a4" args="[]" -->
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<td class="memname">u32 <a class="el" href="xintc__i_8h.html#af0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a>[]</td>
<td class="memname">u32 <a class="el" href="xintc__i_8h.html#f0641659204bd99e09c1511b4d39e1a4">XIntc_BitPosMask</a>[] </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a6afbe6b28aa729c753744cba40ecf5b3"></a><!-- doxytag: member="xintc_i.h::XIntc_ConfigTable" ref="a6afbe6b28aa729c753744cba40ecf5b3" args="[]" -->
</div><p>
<a class="anchor" name="6afbe6b28aa729c753744cba40ecf5b3"></a><!-- doxytag: member="xintc_i.h::XIntc_ConfigTable" ref="6afbe6b28aa729c753744cba40ecf5b3" args="[]" -->
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> <a class="el" href="xintc__i_8h.html#a6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a>[]</td>
<td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> <a class="el" href="xintc__i_8h.html#6afbe6b28aa729c753744cba40ecf5b3">XIntc_ConfigTable</a>[] </td>
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<div class="memdoc">
<p>This table contains configuration information for each intc device in the system. The <a class="el" href="struct_x_intc.html">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_intc___config.html">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized. </p>
<p>
This table contains configuration information for each intc device in the system. The <a class="el" href="struct_x_intc.html">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.<p>
Refer to the <a class="el" href="struct_x_intc___config.html">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized.
</div>
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<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
</div><p>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: xintc_intr.c File Reference
xintc_intr.c File Reference
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<h1>xintc_intr.c File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;xparameters.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__intr_8c.html#a635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This file contains the interrupt processing for the <a class="el" href="struct_x_intc.html">XIntc</a> component which is the driver for the Xilinx Interrupt Controller. The interrupt processing is partitioned seperately such that users are not required to use the provided interrupt processing. This file requires other files of the driver to be linked in also.</p>
<p>Two different interrupt handlers are provided for this driver such that the user must select the appropriate handler for the application. The first interrupt handler, XIntc_VoidInterruptHandler, is provided for systems which use only a single interrupt controller or for systems that cannot otherwise provide an argument to the <a class="el" href="struct_x_intc.html">XIntc</a> interrupt handler (e.g., the RTOS interrupt vector handler may not provide such a facility). The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver. The second interrupt handler, XIntc_InterruptHandler, uses an input argument which is an instance pointer to an interrupt controller driver such that multiple interrupt controllers can be supported. This handler requires the calling function to pass it the appropriate argument, so another level of indirection may be required.</p>
<p>Note that both of these handlers are now only provided for backward compatibility. The handler defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a> is the recommended handler.</p>
<p>The interrupt processing may be used by connecting one of the interrupt handlers to the interrupt system. These handlers do not save and restore the processor context but only handle the processing of the Interrupt Controller. The two handlers are provided as working examples. The user is encouraged to supply their own interrupt handler when performance tuning is deemed necessary.</p>
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<h1>xintc_intr.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
This file contains the interrupt processing for the <a class="el" href="struct_x_intc.html">XIntc</a> component which is the driver for the Xilinx Interrupt Controller. The interrupt processing is partitioned seperately such that users are not required to use the provided interrupt processing. This file requires other files of the driver to be linked in also.<p>
Two different interrupt handlers are provided for this driver such that the user must select the appropriate handler for the application. The first interrupt handler, XIntc_VoidInterruptHandler, is provided for systems which use only a single interrupt controller or for systems that cannot otherwise provide an argument to the <a class="el" href="struct_x_intc.html">XIntc</a> interrupt handler (e.g., the RTOS interrupt vector handler may not provide such a facility). The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver. The second interrupt handler, XIntc_InterruptHandler, uses an input argument which is an instance pointer to an interrupt controller driver such that multiple interrupt controllers can be supported. This handler requires the calling function to pass it the appropriate argument, so another level of indirection may be required.<p>
Note that both of these handlers are now only provided for backward compatibility. The handler defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a> is the recommended handler.<p>
The interrupt processing may be used by connecting one of the interrupt handlers to the interrupt system. These handlers do not save and restore the processor context but only handle the processing of the Interrupt Controller. The two handlers are provided as working examples. The user is encouraged to supply their own interrupt handler when performance tuning is deemed necessary.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- ---------------------------------------------------------
1.00b jhl 02/13/02 First release
1.00c rpm 10/17/03 New release. Support the static vector table created
in the <a class="el" href="xintc__g_8c.html">xintc_g.c</a> configuration table. Collapse handlers
to use the <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> in <a class="el" href="xintc__l_8c.html">xintc_l.c</a>.
to use the <a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> in <a class="el" href="xintc__l_8c.html">xintc_l.c</a>.
1.00c rpm 04/09/04 Added conditional compilation around the old handler
<a class="el" href="xintc_8h.html#a9c6dc6e838193da3ce51c8cdb3b88943">XIntc_VoidInterruptHandler()</a>. This handler will only be
<a class="el" href="xintc_8h.html#9c6dc6e838193da3ce51c8cdb3b88943">XIntc_VoidInterruptHandler()</a>. This handler will only be
include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
1.10c mta 03/21/07 Updated to new coding style
2.00a ktn 10/20/09 Updated to use HAL Processor APIs.</pre><pre> </pre> <hr/><h2>Function Documentation</h2>
<a class="anchor" id="a635187ed756cee70b4b4051560cbd7bc"></a><!-- doxytag: member="xintc_intr.c::XIntc_InterruptHandler" ref="a635187ed756cee70b4b4051560cbd7bc" args="(XIntc *InstancePtr)" -->
2.00a ktn 10/20/09 Updated to use HAL Processor APIs.</pre><p>
<pre> </pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;xparameters.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__intr_8c.html#635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
</table>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="635187ed756cee70b4b4051560cbd7bc"></a><!-- doxytag: member="xintc_intr.c::XIntc_InterruptHandler" ref="635187ed756cee70b4b4051560cbd7bc" args="(XIntc *InstancePtr)" -->
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<td class="memname">void XIntc_InterruptHandler </td>
<td class="memname">void XIntc_InterruptHandler </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em></td>
<td class="paramname"> <em>InstancePtr</em> </td>
<td>&nbsp;)&nbsp;</td>
<td></td>
<td width="100%"></td>
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<div class="memdoc">
<p>Interrupt handler for the driver used when there can be no argument passed to the handler. This function is provided mostly for backward compatibility. The user should use <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a>, if possible.</p>
<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver compilation.</p>
<p>The interrupt handler for the driver. This function is provided mostly for backward compatibility. The user should use <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a> when possible and pass the device ID of the interrupt controller device as its argument.</p>
<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
The interrupt handler for the driver. This function is provided mostly for backward compatibility. The user should use <a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a> when possible and pass the device ID of the interrupt controller device as its argument.<p>
The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
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Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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Xilinx Driver intc v3_2: xintc_l.c File Reference
xintc_l.c File Reference
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<h1>xintc_l.c File Reference</h1><code>#include &quot;xparameters.h&quot;</code><br/>
<code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#ab8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption</a> (u32 BaseAddress, int Option)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#ad1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler</a> (u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#aed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler</a> (u32 BaseAddress, u8 Id, <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a> FastHandler)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This file contains low-level driver functions that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation.</p>
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<h1>xintc_l.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
This file contains low-level driver functions that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -------------------------------------------------------
1.00b jhl 04/24/02 First release
1.00c rpm 10/17/03 New release. Support the static vector table created
in the <a class="el" href="xintc__g_8c.html">xintc_g.c</a> configuration table.
1.00c rpm 04/09/04 Added conditional compilation around the old handler
<a class="el" href="xintc__l_8h.html#abf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler()</a>. This handler will only
<a class="el" href="xintc__l_8h.html#bf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler()</a>. This handler will only
be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
defined.
1.10c mta 03/21/07 Updated to new coding style
@ -66,46 +49,61 @@
XIntc_RegisterFastHandler APIs.
Added XIntc_CascadeHandler API.
2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
nested interrupts.</pre><pre> </pre> <hr/><h2>Function Documentation</h2>
<a class="anchor" id="ace91a1aeaf1a88e1b769decb4ac4a818"></a><!-- doxytag: member="xintc_l.c::XIntc_DeviceInterruptHandler" ref="ace91a1aeaf1a88e1b769decb4ac4a818" args="(void *DeviceId)" -->
nested interrupts.</pre><p>
<pre> </pre>
<p>
<code>#include &quot;xparameters.h&quot;</code><br>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#b8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption</a> (u32 BaseAddress, int Option)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#d1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler</a> (u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8c.html#ed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler</a> (u32 BaseAddress, u8 Id, <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a> FastHandler)</td></tr>
</table>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="ce91a1aeaf1a88e1b769decb4ac4a818"></a><!-- doxytag: member="xintc_l.c::XIntc_DeviceInterruptHandler" ref="ce91a1aeaf1a88e1b769decb4ac4a818" args="(void *DeviceId)" -->
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<td class="memname">void XIntc_DeviceInterruptHandler </td>
<td class="memname">void XIntc_DeviceInterruptHandler </td>
<td>(</td>
<td class="paramtype">void *&nbsp;</td>
<td class="paramname"> <em>DeviceId</em></td>
<td class="paramname"> <em>DeviceId</em> </td>
<td>&nbsp;)&nbsp;</td>
<td></td>
<td width="100%"></td>
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<div class="memdoc">
<p>This is the interrupt handler for the driver interface provided in this file when there can be no argument passed to the handler. In this case, we just use the globally defined device ID for the interrupt controller. This function is provided mostly for backward compatibility. The user should use <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> if possible.</p>
<p>This function does not support multiple interrupt controller instances to be handled.</p>
<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver compilation.</p>
<p>This function is the primary interrupt handler for the driver. It must be connected to the interrupt source such that is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the AckBeforeService flag in the configuration data to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first. This function assumes that an interrupt vector table has been previously initialized.It does not verify that entries in the table are valid before calling an interrupt handler. In Cascade mode this function calls XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. This functions also handles interrupts nesting by saving and restoring link register of Microblaze and Interrupt Level register of interrupt controller properly.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
This function is the primary interrupt handler for the driver. It must be connected to the interrupt source such that is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the AckBeforeService flag in the configuration data to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first. This function assumes that an interrupt vector table has been previously initialized.It does not verify that entries in the table are valid before calling an interrupt handler. In Cascade mode this function calls XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. This functions also handles interrupts nesting by saving and restoring link register of Microblaze and Interrupt Level register of interrupt controller properly.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>DeviceId</em>&nbsp;</td><td>is the zero-based device ID defined in xparameters.h of the interrupting interrupt controller. It is used as a direct index into the configuration data, which contains the vector table for the interrupt controller. Note that even though the argument is a void pointer, the value is not a pointer but the actual device ID. The void pointer type is necessary to meet the XInterruptHandler typedef for interrupt handlers.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>For nested interrupts, this function saves microblaze r14 register on entry and restores on exit. This is required since compiler does not support nesting. This function enables Microblaze interrupts after blocking further interrupts from the current interrupt number and interrupts below current interrupt proirity by writing to Interrupt Level Register of INTC on entry. On exit, it disables microblaze interrupts and restores ILR register default value(0xFFFFFFFF)back. It is recommended to increase STACK_SIZE in linker script for nested interrupts. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>For nested interrupts, this function saves microblaze r14 register on entry and restores on exit. This is required since compiler does not support nesting. This function enables Microblaze interrupts after blocking further interrupts from the current interrupt number and interrupts below current interrupt proirity by writing to Interrupt Level Register of INTC on entry. On exit, it disables microblaze interrupts and restores ILR register default value(0xFFFFFFFF)back. It is recommended to increase STACK_SIZE in linker script for nested interrupts. </dd></dl>
</div>
</div>
<a class="anchor" id="aed2ddee41f0861539f959522ce2f44af"></a><!-- doxytag: member="xintc_l.c::XIntc_RegisterFastHandler" ref="aed2ddee41f0861539f959522ce2f44af" args="(u32 BaseAddress, u8 Id, XFastInterruptHandler FastHandler)" -->
</div><p>
<a class="anchor" name="ed2ddee41f0861539f959522ce2f44af"></a><!-- doxytag: member="xintc_l.c::XIntc_RegisterFastHandler" ref="ed2ddee41f0861539f959522ce2f44af" args="(u32 BaseAddress, u8 Id, XFastInterruptHandler FastHandler)" -->
<div class="memitem">
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<td class="memname">void XIntc_RegisterFastHandler </td>
<td class="memname">void XIntc_RegisterFastHandler </td>
<td>(</td>
<td class="paramtype">u32&nbsp;</td>
<td class="paramname"> <em>BaseAddress</em>, </td>
@ -119,38 +117,38 @@
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramtype"><a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramname"> <em>FastHandler</em></td><td>&nbsp;</td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
<td></td><td></td><td width="100%"></td>
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<p>Register a fast handler function for a specific interrupt ID. The handler function will be called when an interrupt occurs for the given interrupt ID. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Register a fast handler function for a specific interrupt ID. The handler function will be called when an interrupt occurs for the given interrupt ID. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>InterruptId</em>&nbsp;</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>FastHandler</em>&nbsp;</td><td>is the function pointer that will be called when interrupt occurs</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
</div>
</div>
<a class="anchor" id="ad1f8540fa2171b00a3af03329677f684"></a><!-- doxytag: member="xintc_l.c::XIntc_RegisterHandler" ref="ad1f8540fa2171b00a3af03329677f684" args="(u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)" -->
</div><p>
<a class="anchor" name="d1f8540fa2171b00a3af03329677f684"></a><!-- doxytag: member="xintc_l.c::XIntc_RegisterHandler" ref="d1f8540fa2171b00a3af03329677f684" args="(u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)" -->
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<td class="memname">void XIntc_RegisterHandler </td>
<td class="memname">void XIntc_RegisterHandler </td>
<td>(</td>
<td class="paramtype">u32&nbsp;</td>
<td class="paramname"> <em>BaseAddress</em>, </td>
@ -176,34 +174,34 @@
<tr>
<td></td>
<td>)</td>
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<p>Register a handler function for a specific interrupt ID. The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.</p>
<p>This function can also be used to remove a handler from the vector table by passing in the XIntc_DefaultHandler() as the handler and NULL as the callback reference. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Register a handler function for a specific interrupt ID. The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.<p>
This function can also be used to remove a handler from the vector table by passing in the XIntc_DefaultHandler() as the handler and NULL as the callback reference. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>InterruptId</em>&nbsp;</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Handler</em>&nbsp;</td><td>is the function pointer that will be added to the vector table for the given interrupt ID. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>CallBackRef</em>&nbsp;</td><td>is the argument that will be passed to the new handler function when it is called. This is user-specific.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
</div>
</div>
<a class="anchor" id="ab8e5767995d6318e6fc5cf114cda7b68"></a><!-- doxytag: member="xintc_l.c::XIntc_SetIntrSvcOption" ref="ab8e5767995d6318e6fc5cf114cda7b68" args="(u32 BaseAddress, int Option)" -->
</div><p>
<a class="anchor" name="b8e5767995d6318e6fc5cf114cda7b68"></a><!-- doxytag: member="xintc_l.c::XIntc_SetIntrSvcOption" ref="b8e5767995d6318e6fc5cf114cda7b68" args="(u32 BaseAddress, int Option)" -->
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<td class="memname">void XIntc_SetIntrSvcOption </td>
<td class="memname">void XIntc_SetIntrSvcOption </td>
<td>(</td>
<td class="paramtype">u32&nbsp;</td>
<td class="paramname"> <em>BaseAddress</em>, </td>
@ -217,28 +215,23 @@
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<td></td>
<td>)</td>
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<p>Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. The default behavior when using the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> file is to service only a single interrupt, whereas the default behavior when using the driver interface given in this file is to service all outstanding interrupts when an interrupt occurs. In Cascade mode same Option is set to Slave controllers.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. The default behavior when using the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> file is to service only a single interrupt, whereas the default behavior when using the driver interface given in this file is to service all outstanding interrupts when an interrupt occurs. In Cascade mode same Option is set to Slave controllers.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the unique identifier for a device. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Option</em>&nbsp;</td><td>is XIN_SVC_SGL_ISR_OPTION if you want only a single interrupt serviced when an interrupt occurs, or XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts serviced when an interrupt occurs.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
</div>
</div>
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Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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<h1>xintc_l.h File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;xparameters.h&quot;</code><br/>
<code>#include &quot;xil_io.h&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Classes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td></tr>
<tr><td colspan="2"><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a2591750e740c97fb30372d7fd6fba9ca">XINTC_L_H</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a06a568b99545df04b6d14da3b04f1da0">XPAR_XINTC_USE_DCR_BRIDGE</a>&nbsp;&nbsp;&nbsp;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a4c1ce88ba61c2e42054faaef40539556">XIN_ISR_OFFSET</a>&nbsp;&nbsp;&nbsp;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a35c8f39e63012c1745df6faa39fc7335">XIN_IPR_OFFSET</a>&nbsp;&nbsp;&nbsp;4</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>&nbsp;&nbsp;&nbsp;8</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#af12b5f9e19d0d544e8df96699db615bd">XIN_IAR_OFFSET</a>&nbsp;&nbsp;&nbsp;12</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ae3d1be1c28564014eba1e6a7da5f870c">XIN_SIE_OFFSET</a>&nbsp;&nbsp;&nbsp;16</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a1f88cc0f7e4c0fec39f68d4926537461">XIN_CIE_OFFSET</a>&nbsp;&nbsp;&nbsp;20</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a4704ae1ae4388d4b0187bb2ee79849d1">XIN_IVR_OFFSET</a>&nbsp;&nbsp;&nbsp;24</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a1286cdd3996f53dfe62703e6cd949b14">XIN_MER_OFFSET</a>&nbsp;&nbsp;&nbsp;28</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a2dc06911d25b46e1ddad8e2938f95b4c">XIN_IMR_OFFSET</a>&nbsp;&nbsp;&nbsp;32</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ac92a6982a2d3a0f70a310c6912392765">XIN_ILR_OFFSET</a>&nbsp;&nbsp;&nbsp;36</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ab675a4446c4ab809551ea73ad2ca962d">XIN_IVAR_OFFSET</a>&nbsp;&nbsp;&nbsp;0x100</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#aa03735b19bf625b8868dd3633554addf">XIN_INT_MASTER_ENABLE_MASK</a>&nbsp;&nbsp;&nbsp;0x1UL</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a399d5f29c768070adc3ac98c54c6634d">XIN_INT_HARDWARE_ENABLE_MASK</a>&nbsp;&nbsp;&nbsp;0x2UL</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a0254df2003fdd1434617b0477224f748">XIntc_In32</a>&nbsp;&nbsp;&nbsp;Xil_In32</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ac245f85f403876d4e23cf5e24439a66a">XIntc_Out32</a>&nbsp;&nbsp;&nbsp;Xil_Out32</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#af2aeec4bbc6e0c5ca2268e5d7c7dd5ce">XIntc_MasterEnable</a>(BaseAddress)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a93be82188a607b0a13a13a96c5787bb6">XIntc_MasterDisable</a>(BaseAddress)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ad35ec3b9b658f26d989b19783954683e">XIntc_EnableIntr</a>(BaseAddress, EnableMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a5df77bd3561a105f1d6b1837762db956">XIntc_DisableIntr</a>(BaseAddress, DisableMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a4f699042980f8453713171959183fc49">XIntc_AckIntr</a>(BaseAddress, AckMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a13c828dcbbdc3441c8abaded5cda888b">XIntc_GetIntrStatus</a>(BaseAddress)</td></tr>
<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">typedef void(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a> )(void)</td></tr>
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#abf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler</a> (void)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ab8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption</a> (u32 BaseAddress, int Option)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ad1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler</a> (u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#aed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler</a> (u32 BaseAddress, u8 Id, <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a> FastHandler)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This header file contains identifiers and low-level driver functions (or macros) that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation.</p>
<p>Note that users of the driver interface given in this file can register an interrupt handler dynamically (at run-time) using the <a class="el" href="xintc__l_8c.html#ad1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler()</a> function. User of the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> should still use <a class="el" href="xintc_8c.html#aee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, as always. Also see the discussion of the interrupt vector tables in <a class="el" href="xintc_8h.html">xintc.h</a>.</p>
<p>There are currently two interrupt handlers specified in this interface.</p>
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<h1>xintc_l.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
This header file contains identifiers and low-level driver functions (or macros) that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation.<p>
Note that users of the driver interface given in this file can register an interrupt handler dynamically (at run-time) using the <a class="el" href="xintc__l_8c.html#d1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler()</a> function. User of the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> should still use <a class="el" href="xintc_8c.html#ee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, as always. Also see the discussion of the interrupt vector tables in <a class="el" href="xintc_8h.html">xintc.h</a>.<p>
There are currently two interrupt handlers specified in this interface.<p>
<ul>
<li><a class="el" href="xintc__l_8h.html#abf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler()</a> is a handler without any arguments that is used in cases where there is a single interrupt controller device in the system and the handler cannot be passed an argument. This function is provided mostly for backward compatibility.</li>
</ul>
<li><a class="el" href="xintc__l_8h.html#bf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler()</a> is a handler without any arguments that is used in cases where there is a single interrupt controller device in the system and the handler cannot be passed an argument. This function is provided mostly for backward compatibility.</li></ul>
<p>
<ul>
<li><a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> is a handler that takes a device ID as an argument, indicating which interrupt controller device in the system is causing the interrupt - thereby supporting multiple interrupt controllers.</li>
</ul>
<li><a class="el" href="xintc__l_8c.html#ce91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> is a handler that takes a device ID as an argument, indicating which interrupt controller device in the system is causing the interrupt - thereby supporting multiple interrupt controllers.</li></ul>
<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------------
1.00b jhl 04/24/02 First release
1.00c rpm 10/17/03 New release. Support the static vector table created
@ -91,484 +46,591 @@
the FAST Interrupt
2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
interrupt handlers using base address.
2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.</pre><pre> </pre> <hr/><h2>Define Documentation</h2>
<a class="anchor" id="a1f88cc0f7e4c0fec39f68d4926537461"></a><!-- doxytag: member="xintc_l.h::XIN_CIE_OFFSET" ref="a1f88cc0f7e4c0fec39f68d4926537461" args="" -->
2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.</pre><p>
<pre> </pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;xparameters.h&quot;</code><br>
<code>#include &quot;xil_io.h&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Classes</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_intc___vector_table_entry.html">XIntc_VectorTableEntry</a></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#2591750e740c97fb30372d7fd6fba9ca">XINTC_L_H</a></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#06a568b99545df04b6d14da3b04f1da0">XPAR_XINTC_USE_DCR_BRIDGE</a>&nbsp;&nbsp;&nbsp;0</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#4c1ce88ba61c2e42054faaef40539556">XIN_ISR_OFFSET</a>&nbsp;&nbsp;&nbsp;0</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#35c8f39e63012c1745df6faa39fc7335">XIN_IPR_OFFSET</a>&nbsp;&nbsp;&nbsp;4</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>&nbsp;&nbsp;&nbsp;8</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#f12b5f9e19d0d544e8df96699db615bd">XIN_IAR_OFFSET</a>&nbsp;&nbsp;&nbsp;12</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#e3d1be1c28564014eba1e6a7da5f870c">XIN_SIE_OFFSET</a>&nbsp;&nbsp;&nbsp;16</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#1f88cc0f7e4c0fec39f68d4926537461">XIN_CIE_OFFSET</a>&nbsp;&nbsp;&nbsp;20</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#4704ae1ae4388d4b0187bb2ee79849d1">XIN_IVR_OFFSET</a>&nbsp;&nbsp;&nbsp;24</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#1286cdd3996f53dfe62703e6cd949b14">XIN_MER_OFFSET</a>&nbsp;&nbsp;&nbsp;28</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#2dc06911d25b46e1ddad8e2938f95b4c">XIN_IMR_OFFSET</a>&nbsp;&nbsp;&nbsp;32</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#c92a6982a2d3a0f70a310c6912392765">XIN_ILR_OFFSET</a>&nbsp;&nbsp;&nbsp;36</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#b675a4446c4ab809551ea73ad2ca962d">XIN_IVAR_OFFSET</a>&nbsp;&nbsp;&nbsp;0x100</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#a03735b19bf625b8868dd3633554addf">XIN_INT_MASTER_ENABLE_MASK</a>&nbsp;&nbsp;&nbsp;0x1UL</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#399d5f29c768070adc3ac98c54c6634d">XIN_INT_HARDWARE_ENABLE_MASK</a>&nbsp;&nbsp;&nbsp;0x2UL</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#0254df2003fdd1434617b0477224f748">XIntc_In32</a>&nbsp;&nbsp;&nbsp;Xil_In32</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#c245f85f403876d4e23cf5e24439a66a">XIntc_Out32</a>&nbsp;&nbsp;&nbsp;Xil_Out32</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#f2aeec4bbc6e0c5ca2268e5d7c7dd5ce">XIntc_MasterEnable</a>(BaseAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#93be82188a607b0a13a13a96c5787bb6">XIntc_MasterDisable</a>(BaseAddress)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#d35ec3b9b658f26d989b19783954683e">XIntc_EnableIntr</a>(BaseAddress, EnableMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#5df77bd3561a105f1d6b1837762db956">XIntc_DisableIntr</a>(BaseAddress, DisableMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#4f699042980f8453713171959183fc49">XIntc_AckIntr</a>(BaseAddress, AckMask)&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#13c828dcbbdc3441c8abaded5cda888b">XIntc_GetIntrStatus</a>(BaseAddress)</td></tr>
<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a> (void)</td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#bf91e27eb2cc036f84df2e15d14343a8">XIntc_LowLevelInterruptHandler</a> (void)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ce91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#b8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption</a> (u32 BaseAddress, int Option)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#d1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler</a> (u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__l_8h.html#ed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler</a> (u32 BaseAddress, u8 Id, <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a> FastHandler)</td></tr>
</table>
<hr><h2>Define Documentation</h2>
<a class="anchor" name="1f88cc0f7e4c0fec39f68d4926537461"></a><!-- doxytag: member="xintc_l.h::XIN_CIE_OFFSET" ref="1f88cc0f7e4c0fec39f68d4926537461" args="" -->
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<td class="memname">#define XIN_CIE_OFFSET&nbsp;&nbsp;&nbsp;20</td>
<td class="memname">#define XIN_CIE_OFFSET&nbsp;&nbsp;&nbsp;20 </td>
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<a class="anchor" id="af12b5f9e19d0d544e8df96699db615bd"></a><!-- doxytag: member="xintc_l.h::XIN_IAR_OFFSET" ref="af12b5f9e19d0d544e8df96699db615bd" args="" -->
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<a class="anchor" name="f12b5f9e19d0d544e8df96699db615bd"></a><!-- doxytag: member="xintc_l.h::XIN_IAR_OFFSET" ref="f12b5f9e19d0d544e8df96699db615bd" args="" -->
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<td class="memname">#define XIN_IAR_OFFSET&nbsp;&nbsp;&nbsp;12</td>
<td class="memname">#define XIN_IAR_OFFSET&nbsp;&nbsp;&nbsp;12 </td>
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</div>
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<a class="anchor" id="a12fbacf76cabd206d17acefd187fa7b4"></a><!-- doxytag: member="xintc_l.h::XIN_IER_OFFSET" ref="a12fbacf76cabd206d17acefd187fa7b4" args="" -->
</div><p>
<a class="anchor" name="12fbacf76cabd206d17acefd187fa7b4"></a><!-- doxytag: member="xintc_l.h::XIN_IER_OFFSET" ref="12fbacf76cabd206d17acefd187fa7b4" args="" -->
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<td class="memname">#define XIN_IER_OFFSET&nbsp;&nbsp;&nbsp;8</td>
<td class="memname">#define XIN_IER_OFFSET&nbsp;&nbsp;&nbsp;8 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="ac92a6982a2d3a0f70a310c6912392765"></a><!-- doxytag: member="xintc_l.h::XIN_ILR_OFFSET" ref="ac92a6982a2d3a0f70a310c6912392765" args="" -->
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<a class="anchor" name="c92a6982a2d3a0f70a310c6912392765"></a><!-- doxytag: member="xintc_l.h::XIN_ILR_OFFSET" ref="c92a6982a2d3a0f70a310c6912392765" args="" -->
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<td class="memname">#define XIN_ILR_OFFSET&nbsp;&nbsp;&nbsp;36</td>
<td class="memname">#define XIN_ILR_OFFSET&nbsp;&nbsp;&nbsp;36 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a2dc06911d25b46e1ddad8e2938f95b4c"></a><!-- doxytag: member="xintc_l.h::XIN_IMR_OFFSET" ref="a2dc06911d25b46e1ddad8e2938f95b4c" args="" -->
</div><p>
<a class="anchor" name="2dc06911d25b46e1ddad8e2938f95b4c"></a><!-- doxytag: member="xintc_l.h::XIN_IMR_OFFSET" ref="2dc06911d25b46e1ddad8e2938f95b4c" args="" -->
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<td class="memname">#define XIN_IMR_OFFSET&nbsp;&nbsp;&nbsp;32</td>
<td class="memname">#define XIN_IMR_OFFSET&nbsp;&nbsp;&nbsp;32 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a399d5f29c768070adc3ac98c54c6634d"></a><!-- doxytag: member="xintc_l.h::XIN_INT_HARDWARE_ENABLE_MASK" ref="a399d5f29c768070adc3ac98c54c6634d" args="" -->
</div><p>
<a class="anchor" name="399d5f29c768070adc3ac98c54c6634d"></a><!-- doxytag: member="xintc_l.h::XIN_INT_HARDWARE_ENABLE_MASK" ref="399d5f29c768070adc3ac98c54c6634d" args="" -->
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<td class="memname">#define XIN_INT_HARDWARE_ENABLE_MASK&nbsp;&nbsp;&nbsp;0x2UL</td>
<td class="memname">#define XIN_INT_HARDWARE_ENABLE_MASK&nbsp;&nbsp;&nbsp;0x2UL </td>
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</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="aa03735b19bf625b8868dd3633554addf"></a><!-- doxytag: member="xintc_l.h::XIN_INT_MASTER_ENABLE_MASK" ref="aa03735b19bf625b8868dd3633554addf" args="" -->
</div><p>
<a class="anchor" name="a03735b19bf625b8868dd3633554addf"></a><!-- doxytag: member="xintc_l.h::XIN_INT_MASTER_ENABLE_MASK" ref="a03735b19bf625b8868dd3633554addf" args="" -->
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<td class="memname">#define XIN_INT_MASTER_ENABLE_MASK&nbsp;&nbsp;&nbsp;0x1UL</td>
<td class="memname">#define XIN_INT_MASTER_ENABLE_MASK&nbsp;&nbsp;&nbsp;0x1UL </td>
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</table>
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<p>
</div>
</div>
<a class="anchor" id="a35c8f39e63012c1745df6faa39fc7335"></a><!-- doxytag: member="xintc_l.h::XIN_IPR_OFFSET" ref="a35c8f39e63012c1745df6faa39fc7335" args="" -->
</div><p>
<a class="anchor" name="35c8f39e63012c1745df6faa39fc7335"></a><!-- doxytag: member="xintc_l.h::XIN_IPR_OFFSET" ref="35c8f39e63012c1745df6faa39fc7335" args="" -->
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<td class="memname">#define XIN_IPR_OFFSET&nbsp;&nbsp;&nbsp;4</td>
<td class="memname">#define XIN_IPR_OFFSET&nbsp;&nbsp;&nbsp;4 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a4c1ce88ba61c2e42054faaef40539556"></a><!-- doxytag: member="xintc_l.h::XIN_ISR_OFFSET" ref="a4c1ce88ba61c2e42054faaef40539556" args="" -->
</div><p>
<a class="anchor" name="4c1ce88ba61c2e42054faaef40539556"></a><!-- doxytag: member="xintc_l.h::XIN_ISR_OFFSET" ref="4c1ce88ba61c2e42054faaef40539556" args="" -->
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<td class="memname">#define XIN_ISR_OFFSET&nbsp;&nbsp;&nbsp;0</td>
<td class="memname">#define XIN_ISR_OFFSET&nbsp;&nbsp;&nbsp;0 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="ab675a4446c4ab809551ea73ad2ca962d"></a><!-- doxytag: member="xintc_l.h::XIN_IVAR_OFFSET" ref="ab675a4446c4ab809551ea73ad2ca962d" args="" -->
</div><p>
<a class="anchor" name="b675a4446c4ab809551ea73ad2ca962d"></a><!-- doxytag: member="xintc_l.h::XIN_IVAR_OFFSET" ref="b675a4446c4ab809551ea73ad2ca962d" args="" -->
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<td class="memname">#define XIN_IVAR_OFFSET&nbsp;&nbsp;&nbsp;0x100</td>
<td class="memname">#define XIN_IVAR_OFFSET&nbsp;&nbsp;&nbsp;0x100 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a4704ae1ae4388d4b0187bb2ee79849d1"></a><!-- doxytag: member="xintc_l.h::XIN_IVR_OFFSET" ref="a4704ae1ae4388d4b0187bb2ee79849d1" args="" -->
</div><p>
<a class="anchor" name="4704ae1ae4388d4b0187bb2ee79849d1"></a><!-- doxytag: member="xintc_l.h::XIN_IVR_OFFSET" ref="4704ae1ae4388d4b0187bb2ee79849d1" args="" -->
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<td class="memname">#define XIN_IVR_OFFSET&nbsp;&nbsp;&nbsp;24</td>
<td class="memname">#define XIN_IVR_OFFSET&nbsp;&nbsp;&nbsp;24 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a1286cdd3996f53dfe62703e6cd949b14"></a><!-- doxytag: member="xintc_l.h::XIN_MER_OFFSET" ref="a1286cdd3996f53dfe62703e6cd949b14" args="" -->
</div><p>
<a class="anchor" name="1286cdd3996f53dfe62703e6cd949b14"></a><!-- doxytag: member="xintc_l.h::XIN_MER_OFFSET" ref="1286cdd3996f53dfe62703e6cd949b14" args="" -->
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<td class="memname">#define XIN_MER_OFFSET&nbsp;&nbsp;&nbsp;28</td>
<td class="memname">#define XIN_MER_OFFSET&nbsp;&nbsp;&nbsp;28 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="ae3d1be1c28564014eba1e6a7da5f870c"></a><!-- doxytag: member="xintc_l.h::XIN_SIE_OFFSET" ref="ae3d1be1c28564014eba1e6a7da5f870c" args="" -->
</div><p>
<a class="anchor" name="e3d1be1c28564014eba1e6a7da5f870c"></a><!-- doxytag: member="xintc_l.h::XIN_SIE_OFFSET" ref="e3d1be1c28564014eba1e6a7da5f870c" args="" -->
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<td class="memname">#define XIN_SIE_OFFSET&nbsp;&nbsp;&nbsp;16</td>
<td class="memname">#define XIN_SIE_OFFSET&nbsp;&nbsp;&nbsp;16 </td>
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</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a4f699042980f8453713171959183fc49"></a><!-- doxytag: member="xintc_l.h::XIntc_AckIntr" ref="a4f699042980f8453713171959183fc49" args="(BaseAddress, AckMask)" -->
</div><p>
<a class="anchor" name="4f699042980f8453713171959183fc49"></a><!-- doxytag: member="xintc_l.h::XIntc_AckIntr" ref="4f699042980f8453713171959183fc49" args="(BaseAddress, AckMask)" -->
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<td class="memname">#define XIntc_AckIntr</td>
<td class="memname">#define XIntc_AckIntr </td>
<td>(</td>
<td class="paramtype">BaseAddress, </td>
</tr>
<tr>
<td class="paramtype">BaseAddress, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">AckMask&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
<td>&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td>
<td width="100%">&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Acknowledge specific interrupt(s) in the interrupt controller.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Acknowledge specific interrupt(s) in the interrupt controller.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device </td></tr>
<tr><td valign="top"></td><td valign="top"><em>AckMask</em>&nbsp;</td><td>is the 32-bit value to write to the acknowledge register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will acknowledge interrupts.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#a4f699042980f8453713171959183fc49">XIntc_AckIntr(u32 BaseAddress, u32 AckMask)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#4f699042980f8453713171959183fc49">XIntc_AckIntr(u32 BaseAddress, u32 AckMask)</a>; </dd></dl>
</div>
</div>
<a class="anchor" id="a5df77bd3561a105f1d6b1837762db956"></a><!-- doxytag: member="xintc_l.h::XIntc_DisableIntr" ref="a5df77bd3561a105f1d6b1837762db956" args="(BaseAddress, DisableMask)" -->
</div><p>
<a class="anchor" name="5df77bd3561a105f1d6b1837762db956"></a><!-- doxytag: member="xintc_l.h::XIntc_DisableIntr" ref="5df77bd3561a105f1d6b1837762db956" args="(BaseAddress, DisableMask)" -->
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<td class="memname">#define XIntc_DisableIntr</td>
<td class="memname">#define XIntc_DisableIntr </td>
<td>(</td>
<td class="paramtype">BaseAddress, </td>
</tr>
<tr>
<td class="paramtype">BaseAddress, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">DisableMask&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
<td>&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td>
<td width="100%">&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Disable specific interrupt(s) in the interrupt controller.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Disable specific interrupt(s) in the interrupt controller.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device </td></tr>
<tr><td valign="top"></td><td valign="top"><em>DisableMask</em>&nbsp;</td><td>is the 32-bit value to write to the enable register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will disable interrupts.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#a5df77bd3561a105f1d6b1837762db956">XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#5df77bd3561a105f1d6b1837762db956">XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask)</a>; </dd></dl>
</div>
</div>
<a class="anchor" id="ad35ec3b9b658f26d989b19783954683e"></a><!-- doxytag: member="xintc_l.h::XIntc_EnableIntr" ref="ad35ec3b9b658f26d989b19783954683e" args="(BaseAddress, EnableMask)" -->
</div><p>
<a class="anchor" name="d35ec3b9b658f26d989b19783954683e"></a><!-- doxytag: member="xintc_l.h::XIntc_EnableIntr" ref="d35ec3b9b658f26d989b19783954683e" args="(BaseAddress, EnableMask)" -->
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<td class="memname">#define XIntc_EnableIntr</td>
<td class="memname">#define XIntc_EnableIntr </td>
<td>(</td>
<td class="paramtype">BaseAddress, </td>
</tr>
<tr>
<td class="paramtype">BaseAddress, <tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">EnableMask&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
<td>&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td>
<td width="100%">&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Enable specific interrupt(s) in the interrupt controller.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Enable specific interrupt(s) in the interrupt controller.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device </td></tr>
<tr><td valign="top"></td><td valign="top"><em>EnableMask</em>&nbsp;</td><td>is the 32-bit value to write to the enable register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will enable interrupts.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#ad35ec3b9b658f26d989b19783954683e">XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#d35ec3b9b658f26d989b19783954683e">XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask)</a>; </dd></dl>
</div>
</div>
<a class="anchor" id="a13c828dcbbdc3441c8abaded5cda888b"></a><!-- doxytag: member="xintc_l.h::XIntc_GetIntrStatus" ref="a13c828dcbbdc3441c8abaded5cda888b" args="(BaseAddress)" -->
</div><p>
<a class="anchor" name="13c828dcbbdc3441c8abaded5cda888b"></a><!-- doxytag: member="xintc_l.h::XIntc_GetIntrStatus" ref="13c828dcbbdc3441c8abaded5cda888b" args="(BaseAddress)" -->
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<td class="memname">#define XIntc_GetIntrStatus</td>
<td class="memname">#define XIntc_GetIntrStatus </td>
<td>(</td>
<td class="paramtype">BaseAddress&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
<td></td>
<td width="100%"></td>
</tr>
</table>
</div>
<div class="memdoc">
<b>Value:</b><div class="fragment"><pre class="fragment">(<a class="code" href="xintc__l_8h.html#a0254df2003fdd1434617b0477224f748">XIntc_In32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#a4c1ce88ba61c2e42054faaef40539556">XIN_ISR_OFFSET</a>) &amp; \
<a class="code" href="xintc__l_8h.html#a0254df2003fdd1434617b0477224f748">XIntc_In32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#a12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>))
</pre></div><p>Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
<b>Value:</b><div class="fragment"><pre class="fragment">(<a class="code" href="xintc__l_8h.html#0254df2003fdd1434617b0477224f748">XIntc_In32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#4c1ce88ba61c2e42054faaef40539556">XIN_ISR_OFFSET</a>) &amp; \
<a class="code" href="xintc__l_8h.html#0254df2003fdd1434617b0477224f748">XIntc_In32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>))
</pre></div>Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>The 32-bit contents of the interrupt status register. Each bit corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Bits which are set indicate an active interrupt which is also enabled.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: u32 <a class="el" href="xintc__l_8h.html#a13c828dcbbdc3441c8abaded5cda888b">XIntc_GetIntrStatus(u32 BaseAddress)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>The 32-bit contents of the interrupt status register. Each bit corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Bits which are set indicate an active interrupt which is also enabled.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: u32 <a class="el" href="xintc__l_8h.html#13c828dcbbdc3441c8abaded5cda888b">XIntc_GetIntrStatus(u32 BaseAddress)</a>; </dd></dl>
</div>
</div>
<a class="anchor" id="a0254df2003fdd1434617b0477224f748"></a><!-- doxytag: member="xintc_l.h::XIntc_In32" ref="a0254df2003fdd1434617b0477224f748" args="" -->
</div><p>
<a class="anchor" name="0254df2003fdd1434617b0477224f748"></a><!-- doxytag: member="xintc_l.h::XIntc_In32" ref="0254df2003fdd1434617b0477224f748" args="" -->
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<td class="memname">#define XIntc_In32&nbsp;&nbsp;&nbsp;Xil_In32</td>
<td class="memname">#define XIntc_In32&nbsp;&nbsp;&nbsp;Xil_In32 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<a class="anchor" id="a2591750e740c97fb30372d7fd6fba9ca"></a><!-- doxytag: member="xintc_l.h::XINTC_L_H" ref="a2591750e740c97fb30372d7fd6fba9ca" args="" -->
</div><p>
<a class="anchor" name="2591750e740c97fb30372d7fd6fba9ca"></a><!-- doxytag: member="xintc_l.h::XINTC_L_H" ref="2591750e740c97fb30372d7fd6fba9ca" args="" -->
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<td class="memname">#define XINTC_L_H</td>
<td class="memname">#define XINTC_L_H </td>
</tr>
</table>
</div>
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<p>
</div>
</div>
<a class="anchor" id="a93be82188a607b0a13a13a96c5787bb6"></a><!-- doxytag: member="xintc_l.h::XIntc_MasterDisable" ref="a93be82188a607b0a13a13a96c5787bb6" args="(BaseAddress)" -->
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<a class="anchor" name="93be82188a607b0a13a13a96c5787bb6"></a><!-- doxytag: member="xintc_l.h::XIntc_MasterDisable" ref="93be82188a607b0a13a13a96c5787bb6" args="(BaseAddress)" -->
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<td class="memname">#define XIntc_MasterDisable</td>
<td class="memname">#define XIntc_MasterDisable </td>
<td>(</td>
<td class="paramtype">BaseAddress&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
<td>&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)</td>
<td width="100%">&nbsp;&nbsp;&nbsp;XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)</td>
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<p>Disable all interrupts in the Master Enable register of the interrupt controller.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Disable all interrupts in the Master Enable register of the interrupt controller.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#a93be82188a607b0a13a13a96c5787bb6">XIntc_MasterDisable(u32 BaseAddress)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#93be82188a607b0a13a13a96c5787bb6">XIntc_MasterDisable(u32 BaseAddress)</a>; </dd></dl>
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<a class="anchor" id="af2aeec4bbc6e0c5ca2268e5d7c7dd5ce"></a><!-- doxytag: member="xintc_l.h::XIntc_MasterEnable" ref="af2aeec4bbc6e0c5ca2268e5d7c7dd5ce" args="(BaseAddress)" -->
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<a class="anchor" name="f2aeec4bbc6e0c5ca2268e5d7c7dd5ce"></a><!-- doxytag: member="xintc_l.h::XIntc_MasterEnable" ref="f2aeec4bbc6e0c5ca2268e5d7c7dd5ce" args="(BaseAddress)" -->
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<td class="memname">#define XIntc_MasterEnable</td>
<td class="memname">#define XIntc_MasterEnable </td>
<td>(</td>
<td class="paramtype">BaseAddress&nbsp;</td>
<td class="paramname"></td>
<td class="paramname"> </td>
<td>&nbsp;)&nbsp;</td>
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<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="xintc__l_8h.html#ac245f85f403876d4e23cf5e24439a66a">XIntc_Out32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#a1286cdd3996f53dfe62703e6cd949b14">XIN_MER_OFFSET</a>, \
<a class="code" href="xintc__l_8h.html#aa03735b19bf625b8868dd3633554addf">XIN_INT_MASTER_ENABLE_MASK</a> | <a class="code" href="xintc__l_8h.html#a399d5f29c768070adc3ac98c54c6634d">XIN_INT_HARDWARE_ENABLE_MASK</a>)
</pre></div><p>Enable all interrupts in the Master Enable register of the interrupt controller. The interrupt controller defaults to all interrupts disabled from reset such that this macro must be used to enable interrupts.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="xintc__l_8h.html#c245f85f403876d4e23cf5e24439a66a">XIntc_Out32</a>((BaseAddress) + <a class="code" href="xintc__l_8h.html#1286cdd3996f53dfe62703e6cd949b14">XIN_MER_OFFSET</a>, \
<a class="code" href="xintc__l_8h.html#a03735b19bf625b8868dd3633554addf">XIN_INT_MASTER_ENABLE_MASK</a> | <a class="code" href="xintc__l_8h.html#399d5f29c768070adc3ac98c54c6634d">XIN_INT_HARDWARE_ENABLE_MASK</a>)
</pre></div>Enable all interrupts in the Master Enable register of the interrupt controller. The interrupt controller defaults to all interrupts disabled from reset such that this macro must be used to enable interrupts.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the device.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#af2aeec4bbc6e0c5ca2268e5d7c7dd5ce">XIntc_MasterEnable(u32 BaseAddress)</a>; </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xintc__l_8h.html#f2aeec4bbc6e0c5ca2268e5d7c7dd5ce">XIntc_MasterEnable(u32 BaseAddress)</a>; </dd></dl>
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<a class="anchor" id="ac245f85f403876d4e23cf5e24439a66a"></a><!-- doxytag: member="xintc_l.h::XIntc_Out32" ref="ac245f85f403876d4e23cf5e24439a66a" args="" -->
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<a class="anchor" name="c245f85f403876d4e23cf5e24439a66a"></a><!-- doxytag: member="xintc_l.h::XIntc_Out32" ref="c245f85f403876d4e23cf5e24439a66a" args="" -->
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<td class="memname">#define XIntc_Out32&nbsp;&nbsp;&nbsp;Xil_Out32</td>
<td class="memname">#define XIntc_Out32&nbsp;&nbsp;&nbsp;Xil_Out32 </td>
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<p>
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<a class="anchor" id="a06a568b99545df04b6d14da3b04f1da0"></a><!-- doxytag: member="xintc_l.h::XPAR_XINTC_USE_DCR_BRIDGE" ref="a06a568b99545df04b6d14da3b04f1da0" args="" -->
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<a class="anchor" name="06a568b99545df04b6d14da3b04f1da0"></a><!-- doxytag: member="xintc_l.h::XPAR_XINTC_USE_DCR_BRIDGE" ref="06a568b99545df04b6d14da3b04f1da0" args="" -->
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<td class="memname">#define XPAR_XINTC_USE_DCR_BRIDGE&nbsp;&nbsp;&nbsp;0</td>
<td class="memname">#define XPAR_XINTC_USE_DCR_BRIDGE&nbsp;&nbsp;&nbsp;0 </td>
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<hr/><h2>Typedef Documentation</h2>
<a class="anchor" id="ab333e5826535071fe60f13b70b6e56dd"></a><!-- doxytag: member="xintc_l.h::XFastInterruptHandler" ref="ab333e5826535071fe60f13b70b6e56dd" args=")(void)" -->
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<hr><h2>Typedef Documentation</h2>
<a class="anchor" name="6de21b6c45b4ee4a4443b8daf9749e07"></a><!-- doxytag: member="xintc_l.h::XFastInterruptHandler" ref="6de21b6c45b4ee4a4443b8daf9749e07" args="(void)" -->
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<td class="memname">typedef void(* <a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a>)(void)</td>
<td class="memname">typedef void(*) <a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a>(void) </td>
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<hr/><h2>Function Documentation</h2>
<a class="anchor" id="ace91a1aeaf1a88e1b769decb4ac4a818"></a><!-- doxytag: member="xintc_l.h::XIntc_DeviceInterruptHandler" ref="ace91a1aeaf1a88e1b769decb4ac4a818" args="(void *DeviceId)" -->
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<hr><h2>Function Documentation</h2>
<a class="anchor" name="ce91a1aeaf1a88e1b769decb4ac4a818"></a><!-- doxytag: member="xintc_l.h::XIntc_DeviceInterruptHandler" ref="ce91a1aeaf1a88e1b769decb4ac4a818" args="(void *DeviceId)" -->
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<td class="memname">void XIntc_DeviceInterruptHandler </td>
<td class="memname">void XIntc_DeviceInterruptHandler </td>
<td>(</td>
<td class="paramtype">void *&nbsp;</td>
<td class="paramname"> <em>DeviceId</em></td>
<td class="paramname"> <em>DeviceId</em> </td>
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<p>This is the interrupt handler for the driver interface provided in this file when there can be no argument passed to the handler. In this case, we just use the globally defined device ID for the interrupt controller. This function is provided mostly for backward compatibility. The user should use <a class="el" href="xintc__l_8c.html#ace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a> if possible.</p>
<p>This function does not support multiple interrupt controller instances to be handled.</p>
<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver compilation.</p>
<p>This function is the primary interrupt handler for the driver. It must be connected to the interrupt source such that is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the AckBeforeService flag in the configuration data to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first. This function assumes that an interrupt vector table has been previously initialized.It does not verify that entries in the table are valid before calling an interrupt handler. In Cascade mode this function calls XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. This functions also handles interrupts nesting by saving and restoring link register of Microblaze and Interrupt Level register of interrupt controller properly.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
This function is the primary interrupt handler for the driver. It must be connected to the interrupt source such that is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the AckBeforeService flag in the configuration data to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first. This function assumes that an interrupt vector table has been previously initialized.It does not verify that entries in the table are valid before calling an interrupt handler. In Cascade mode this function calls XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. This functions also handles interrupts nesting by saving and restoring link register of Microblaze and Interrupt Level register of interrupt controller properly.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>DeviceId</em>&nbsp;</td><td>is the zero-based device ID defined in xparameters.h of the interrupting interrupt controller. It is used as a direct index into the configuration data, which contains the vector table for the interrupt controller. Note that even though the argument is a void pointer, the value is not a pointer but the actual device ID. The void pointer type is necessary to meet the XInterruptHandler typedef for interrupt handlers.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>For nested interrupts, this function saves microblaze r14 register on entry and restores on exit. This is required since compiler does not support nesting. This function enables Microblaze interrupts after blocking further interrupts from the current interrupt number and interrupts below current interrupt proirity by writing to Interrupt Level Register of INTC on entry. On exit, it disables microblaze interrupts and restores ILR register default value(0xFFFFFFFF)back. It is recommended to increase STACK_SIZE in linker script for nested interrupts. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>For nested interrupts, this function saves microblaze r14 register on entry and restores on exit. This is required since compiler does not support nesting. This function enables Microblaze interrupts after blocking further interrupts from the current interrupt number and interrupts below current interrupt proirity by writing to Interrupt Level Register of INTC on entry. On exit, it disables microblaze interrupts and restores ILR register default value(0xFFFFFFFF)back. It is recommended to increase STACK_SIZE in linker script for nested interrupts. </dd></dl>
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<a class="anchor" id="abf91e27eb2cc036f84df2e15d14343a8"></a><!-- doxytag: member="xintc_l.h::XIntc_LowLevelInterruptHandler" ref="abf91e27eb2cc036f84df2e15d14343a8" args="(void)" -->
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<a class="anchor" name="bf91e27eb2cc036f84df2e15d14343a8"></a><!-- doxytag: member="xintc_l.h::XIntc_LowLevelInterruptHandler" ref="bf91e27eb2cc036f84df2e15d14343a8" args="(void)" -->
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<td class="memname">void XIntc_LowLevelInterruptHandler </td>
<td class="memname">void XIntc_LowLevelInterruptHandler </td>
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<a class="anchor" id="aed2ddee41f0861539f959522ce2f44af"></a><!-- doxytag: member="xintc_l.h::XIntc_RegisterFastHandler" ref="aed2ddee41f0861539f959522ce2f44af" args="(u32 BaseAddress, u8 Id, XFastInterruptHandler FastHandler)" -->
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<a class="anchor" name="ed2ddee41f0861539f959522ce2f44af"></a><!-- doxytag: member="xintc_l.h::XIntc_RegisterFastHandler" ref="ed2ddee41f0861539f959522ce2f44af" args="(u32 BaseAddress, u8 Id, XFastInterruptHandler FastHandler)" -->
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<td class="memname">void XIntc_RegisterFastHandler </td>
<td class="memname">void XIntc_RegisterFastHandler </td>
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<td class="paramname"> <em>BaseAddress</em>, </td>
@ -582,38 +644,38 @@
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<td class="paramtype"><a class="el" href="xintc__l_8h.html#ab333e5826535071fe60f13b70b6e56dd">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramtype"><a class="el" href="xintc__l_8h.html#6de21b6c45b4ee4a4443b8daf9749e07">XFastInterruptHandler</a>&nbsp;</td>
<td class="paramname"> <em>FastHandler</em></td><td>&nbsp;</td>
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<p>Register a fast handler function for a specific interrupt ID. The handler function will be called when an interrupt occurs for the given interrupt ID. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Register a fast handler function for a specific interrupt ID. The handler function will be called when an interrupt occurs for the given interrupt ID. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>InterruptId</em>&nbsp;</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>FastHandler</em>&nbsp;</td><td>is the function pointer that will be called when interrupt occurs</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
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<a class="anchor" id="ad1f8540fa2171b00a3af03329677f684"></a><!-- doxytag: member="xintc_l.h::XIntc_RegisterHandler" ref="ad1f8540fa2171b00a3af03329677f684" args="(u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)" -->
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<a class="anchor" name="d1f8540fa2171b00a3af03329677f684"></a><!-- doxytag: member="xintc_l.h::XIntc_RegisterHandler" ref="d1f8540fa2171b00a3af03329677f684" args="(u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)" -->
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<td class="memname">void XIntc_RegisterHandler </td>
<td class="memname">void XIntc_RegisterHandler </td>
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<p>Register a handler function for a specific interrupt ID. The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.</p>
<p>This function can also be used to remove a handler from the vector table by passing in the XIntc_DefaultHandler() as the handler and NULL as the callback reference. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Register a handler function for a specific interrupt ID. The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.<p>
This function can also be used to remove a handler from the vector table by passing in the XIntc_DefaultHandler() as the handler and NULL as the callback reference. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>InterruptId</em>&nbsp;</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Handler</em>&nbsp;</td><td>is the function pointer that will be added to the vector table for the given interrupt ID. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>CallBackRef</em>&nbsp;</td><td>is the argument that will be passed to the new handler function when it is called. This is user-specific.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
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<a class="anchor" id="ab8e5767995d6318e6fc5cf114cda7b68"></a><!-- doxytag: member="xintc_l.h::XIntc_SetIntrSvcOption" ref="ab8e5767995d6318e6fc5cf114cda7b68" args="(u32 BaseAddress, int Option)" -->
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<a class="anchor" name="b8e5767995d6318e6fc5cf114cda7b68"></a><!-- doxytag: member="xintc_l.h::XIntc_SetIntrSvcOption" ref="b8e5767995d6318e6fc5cf114cda7b68" args="(u32 BaseAddress, int Option)" -->
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<td class="memname">void XIntc_SetIntrSvcOption </td>
<td class="memname">void XIntc_SetIntrSvcOption </td>
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<p>Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. The default behavior when using the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> file is to service only a single interrupt, whereas the default behavior when using the driver interface given in this file is to service all outstanding interrupts when an interrupt occurs. In Cascade mode same Option is set to Slave controllers.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. The default behavior when using the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> file is to service only a single interrupt, whereas the default behavior when using the driver interface given in this file is to service all outstanding interrupts when an interrupt occurs. In Cascade mode same Option is set to Slave controllers.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em>&nbsp;</td><td>is the unique identifier for a device. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Option</em>&nbsp;</td><td>is XIN_SVC_SGL_ISR_OPTION if you want only a single interrupt serviced when an interrupt occurs, or XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts serviced when an interrupt occurs.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd></dd></dl>
Note that this function has no effect if the input base address is invalid.
</div>
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<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
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Xilinx Driver intc v3_2: xintc_options.c File Reference
xintc_options.c File Reference
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<h1>xintc_options.c File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__options_8c.html#a1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u32 Options)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__options_8c.html#a6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Contains option functions for the <a class="el" href="struct_x_intc.html">XIntc</a> driver. These functions allow the user to configure an instance of the <a class="el" href="struct_x_intc.html">XIntc</a> driver. This file requires other files of the component to be linked in also.</p>
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<h1>xintc_options.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
Contains option functions for the <a class="el" href="struct_x_intc.html">XIntc</a> driver. These functions allow the user to configure an instance of the <a class="el" href="struct_x_intc.html">XIntc</a> driver. This file requires other files of the component to be linked in also.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------------
1.00b jhl 02/21/02 First release
1.00c rpm 10/17/03 New release. Support the relocation of the options flag
@ -48,40 +35,54 @@
2.00a ktn 10/20/09 Updated to use HAL Processor APIs
2.06a bss 01/28/13 To support Cascade mode:
Modified XIntc_SetOptions API.
</pre> <hr/><h2>Function Documentation</h2>
<a class="anchor" id="a6fdbe96b1db87f0c78e68da8bc767a69"></a><!-- doxytag: member="xintc_options.c::XIntc_GetOptions" ref="a6fdbe96b1db87f0c78e68da8bc767a69" args="(XIntc *InstancePtr)" -->
</pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__options_8c.html#1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u32 Options)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__options_8c.html#6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
</table>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="6fdbe96b1db87f0c78e68da8bc767a69"></a><!-- doxytag: member="xintc_options.c::XIntc_GetOptions" ref="6fdbe96b1db87f0c78e68da8bc767a69" args="(XIntc *InstancePtr)" -->
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<td class="memname">u32 XIntc_GetOptions </td>
<td class="memname">u32 XIntc_GetOptions </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em></td>
<td class="paramname"> <em>InstancePtr</em> </td>
<td>&nbsp;)&nbsp;</td>
<td></td>
<td width="100%"></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Return the currently set options.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Return the currently set options.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>The currently set options. The options are described in <a class="el" href="xintc_8h.html">xintc.h</a>.</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd>The currently set options. The options are described in <a class="el" href="xintc_8h.html">xintc.h</a>.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="a1f0d32716f082a51a751df84312c7d56"></a><!-- doxytag: member="xintc_options.c::XIntc_SetOptions" ref="a1f0d32716f082a51a751df84312c7d56" args="(XIntc *InstancePtr, u32 Options)" -->
</div><p>
<a class="anchor" name="1f0d32716f082a51a751df84312c7d56"></a><!-- doxytag: member="xintc_options.c::XIntc_SetOptions" ref="1f0d32716f082a51a751df84312c7d56" args="(XIntc *InstancePtr, u32 Options)" -->
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<td class="memname">int XIntc_SetOptions </td>
<td class="memname">int XIntc_SetOptions </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -95,31 +96,25 @@
<tr>
<td></td>
<td>)</td>
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<p>Set the options for the interrupt controller driver. In Cascade mode same Option is set to Slave controllers.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Set the options for the interrupt controller driver. In Cascade mode same Option is set to Slave controllers.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Options</em>&nbsp;</td><td>to be set. The available options are described in <a class="el" href="xintc_8h.html">xintc.h</a>.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the options were set successfully</li>
<li>XST_INVALID_PARAM if the specified option was not valid</li>
</ul>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the options were set successfully</li><li>XST_INVALID_PARAM if the specified option was not valid</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
</div><p>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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XilinxProcessorIPLib/drivers/intc/doc/html/api/xintc__selftest_8c.html
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Xilinx Driver intc v3_2: xintc_selftest.c File Reference
xintc_selftest.c File Reference
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<h1>xintc_selftest.c File Reference</h1><code>#include &quot;xil_types.h&quot;</code><br/>
<code>#include &quot;xil_assert.h&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br/>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br/>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#a0a3e862d0b6387284dfc91d45dd3374e">XIN_TEST_MASK</a>&nbsp;&nbsp;&nbsp;1</td></tr>
<tr><td colspan="2"><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#af9a9a16180b363930d21bc94dfe71147">XIntc_SelfTest</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#a17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Contains diagnostic self-test functions for the <a class="el" href="struct_x_intc.html">XIntc</a> component. This file requires other files of the component to be linked in also.</p>
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<h1>xintc_selftest.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
Contains diagnostic self-test functions for the <a class="el" href="struct_x_intc.html">XIntc</a> component. This file requires other files of the component to be linked in also.<p>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00b jhl 02/21/02 First release
1.10c mta 03/21/07 Updated to new coding style
@ -50,59 +34,77 @@
MER register to remove warnings
2.06a bss 01/28/13 To support Cascade mode:
Modified XIntc_SimulateIntr API.
</pre> <hr/><h2>Define Documentation</h2>
<a class="anchor" id="a0a3e862d0b6387284dfc91d45dd3374e"></a><!-- doxytag: member="xintc_selftest.c::XIN_TEST_MASK" ref="a0a3e862d0b6387284dfc91d45dd3374e" args="" -->
</pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
<code>#include &quot;xil_assert.h&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc_8h.html">xintc.h</a>&quot;</code><br>
<code>#include &quot;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&quot;</code><br>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#0a3e862d0b6387284dfc91d45dd3374e">XIN_TEST_MASK</a>&nbsp;&nbsp;&nbsp;1</td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#f9a9a16180b363930d21bc94dfe71147">XIntc_SelfTest</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xintc__selftest_8c.html#17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
</table>
<hr><h2>Define Documentation</h2>
<a class="anchor" name="0a3e862d0b6387284dfc91d45dd3374e"></a><!-- doxytag: member="xintc_selftest.c::XIN_TEST_MASK" ref="0a3e862d0b6387284dfc91d45dd3374e" args="" -->
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<td class="memname">#define XIN_TEST_MASK&nbsp;&nbsp;&nbsp;1</td>
<td class="memname">#define XIN_TEST_MASK&nbsp;&nbsp;&nbsp;1 </td>
</tr>
</table>
</div>
<div class="memdoc">
<p>
</div>
</div>
<hr/><h2>Function Documentation</h2>
<a class="anchor" id="af9a9a16180b363930d21bc94dfe71147"></a><!-- doxytag: member="xintc_selftest.c::XIntc_SelfTest" ref="af9a9a16180b363930d21bc94dfe71147" args="(XIntc *InstancePtr)" -->
</div><p>
<hr><h2>Function Documentation</h2>
<a class="anchor" name="f9a9a16180b363930d21bc94dfe71147"></a><!-- doxytag: member="xintc_selftest.c::XIntc_SelfTest" ref="f9a9a16180b363930d21bc94dfe71147" args="(XIntc *InstancePtr)" -->
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<td class="memname">int XIntc_SelfTest </td>
<td class="memname">int XIntc_SelfTest </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em></td>
<td class="paramname"> <em>InstancePtr</em> </td>
<td>&nbsp;)&nbsp;</td>
<td></td>
<td width="100%"></td>
</tr>
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<div class="memdoc">
<p>Run a self-test on the driver/device. This is a destructive test.</p>
<p>This involves forcing interrupts into the controller and verifying that they are recognized and can be acknowledged. This test will not succeed if the interrupt controller has been started in real mode such that interrupts cannot be forced.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Run a self-test on the driver/device. This is a destructive test.<p>
This involves forcing interrupts into the controller and verifying that they are recognized and can be acknowledged. This test will not succeed if the interrupt controller has been started in real mode such that interrupts cannot be forced.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if self-test is successful.</li>
<li>XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the self-test. It will fail the self test if the device has previously been started in real mode.</li>
</ul>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if self-test is successful.</li><li>XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the self-test. It will fail the self test if the device has previously been started in real mode.</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
<a class="anchor" id="a17972363ab5a1a8f5f1d135c5b3c22c7"></a><!-- doxytag: member="xintc_selftest.c::XIntc_SimulateIntr" ref="a17972363ab5a1a8f5f1d135c5b3c22c7" args="(XIntc *InstancePtr, u8 Id)" -->
</div><p>
<a class="anchor" name="17972363ab5a1a8f5f1d135c5b3c22c7"></a><!-- doxytag: member="xintc_selftest.c::XIntc_SimulateIntr" ref="17972363ab5a1a8f5f1d135c5b3c22c7" args="(XIntc *InstancePtr, u8 Id)" -->
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<td class="memname">int XIntc_SimulateIntr </td>
<td class="memname">int XIntc_SimulateIntr </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -116,31 +118,25 @@
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<div class="memdoc">
<p>Allows software to simulate an interrupt in the interrupt controller. This function will only be successful when the interrupt controller has been started in simulation mode. Once it has been started in real mode, interrupts cannot be simulated. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it. In Cascade mode writes to ISR of appropraite Slave controller depending on Id.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<p>
Allows software to simulate an interrupt in the interrupt controller. This function will only be successful when the interrupt controller has been started in simulation mode. Once it has been started in real mode, interrupts cannot be simulated. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it. In Cascade mode writes to ISR of appropraite Slave controller depending on Id.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_intc.html">XIntc</a> instance to be worked on. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>Id</em>&nbsp;</td><td>is the interrupt ID for which to simulate an interrupt.</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if successful</li>
<li>XST_FAILURE if the interrupt could not be simulated because the interrupt controller is or has previously been in real mode.</li>
</ul>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if successful</li><li>XST_FAILURE if the interrupt could not be simulated because the interrupt controller is or has previously been in real mode.</li></ul>
</dd></dl>
<dl class="note"><dt><b>Note:</b></dt><dd>None. </dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div>
</div>
<p class="Copyright">
Copyright &copy; 1995-2014 Xilinx, Inc. All rights reserved.
</p>
</body>
</html>
</div><p>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.