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iicps: Removed repeated start feature.

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This patch removes the repeated start feature.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2014-10-08 15:16:09 +05:30 • committed by Suneel Garapati
parent 1745f21b76
commit 45db2926b5
4 changed files with 43 additions and 93 deletions
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4
XilinxProcessorIPLib/drivers/iicps/src/xiicps.c
View file

@ -47,6 +47,7 @@
* 2.1 hk 04/25/14 Explicitly reset CR and clear FIFO in Abort function * 2.1 hk 04/25/14 Explicitly reset CR and clear FIFO in Abort function
* and state the same in the comments. CR# 784254. * and state the same in the comments. CR# 784254.
* Fix for CR# 761060 - provision for repeated start. * Fix for CR# 761060 - provision for repeated start.
* 2.3 sk 10/07/14 Repeated start feature removed.
* *
* </pre> * </pre>
* *
@ -129,9 +130,6 @@ int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
*/ */
InstancePtr->Options = XIicPs_GetOptions(InstancePtr); InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
/* Initialize repeated start flag to 0 */
InstancePtr->IsRepeatedStart = 0;
return XST_SUCCESS; return XST_SUCCESS;
} }

3
XilinxProcessorIPLib/drivers/iicps/src/xiicps.h
View file

@ -167,6 +167,7 @@
* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable * 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
* read mode and clear transfer size register. * read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry. * Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/07/14 Repeated start feature deleted.
* *
* </pre> * </pre>
* *
@ -199,7 +200,6 @@ extern "C" {
#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */ #define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */ #define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */ #define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */
/*@}*/ /*@}*/
/** @name Callback events /** @name Callback events
@ -275,7 +275,6 @@ typedef struct {
int UpdateTxSize; /* If tx size register has to be updated */ int UpdateTxSize; /* If tx size register has to be updated */
int IsSend; /* Whether master is sending or receiving */ int IsSend; /* Whether master is sending or receiving */
int IsRepeatedStart; /* Indicates if user set repeated start */
XIicPs_IntrHandler StatusHandler; /* Event handler function */ XIicPs_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */ void *CallBackRef; /* Callback reference for event handler */

104
XilinxProcessorIPLib/drivers/iicps/src/xiicps_master.c
View file

@ -55,6 +55,7 @@
* Disable NACK to avoid interrupts on each retry. * Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/06/14 Fill transmit fifo before address register when sending. * 2.3 sk 10/06/14 Fill transmit fifo before address register when sending.
* Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH. * Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
* Repeated start feature removed.
* *
* </pre> * </pre>
* *
@ -115,21 +116,21 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
InstancePtr->RecvBufferPtr = NULL; InstancePtr->RecvBufferPtr = NULL;
InstancePtr->IsSend = 1; InstancePtr->IsSend = 1;
/*
* Set repeated start if sending more than FIFO of data.
*/
if ((InstancePtr->IsRepeatedStart) ||
(ByteCount > XIICPS_FIFO_DEPTH)) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK);
}
/* /*
* Setup as a master sending role. * Setup as a master sending role.
*/ */
XIicPs_SetupMaster(InstancePtr, SENDING_ROLE); XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
/*
* Set HOLD bit if sending more than FIFO of data.
*/
if (ByteCount > XIICPS_FIFO_DEPTH) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK);
}
TransmitFifoFill(InstancePtr); TransmitFifoFill(InstancePtr);
/* /*
@ -180,9 +181,7 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
InstancePtr->IsSend = 0; InstancePtr->IsSend = 0;
InstancePtr->UpdateTxSize = 0; InstancePtr->UpdateTxSize = 0;
if ((ByteCount > XIICPS_FIFO_DEPTH) || if (ByteCount > XIICPS_FIFO_DEPTH) {
(InstancePtr->IsRepeatedStart))
{
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); XIICPS_CR_HOLD_MASK);
@ -258,8 +257,7 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
InstancePtr->SendBufferPtr = MsgPtr; InstancePtr->SendBufferPtr = MsgPtr;
InstancePtr->SendByteCount = ByteCount; InstancePtr->SendByteCount = ByteCount;
if ((InstancePtr->IsRepeatedStart) || if (ByteCount > XIICPS_FIFO_DEPTH) {
(ByteCount > XIICPS_FIFO_DEPTH)) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); XIICPS_CR_HOLD_MASK);
@ -325,11 +323,9 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
} }
} }
if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK));
(~XIICPS_CR_HOLD_MASK));
}
return XST_SUCCESS; return XST_SUCCESS;
} }
@ -376,17 +372,15 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
InstancePtr->RecvBufferPtr = MsgPtr; InstancePtr->RecvBufferPtr = MsgPtr;
InstancePtr->RecvByteCount = ByteCount; InstancePtr->RecvByteCount = ByteCount;
if((ByteCount > XIICPS_FIFO_DEPTH) || XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
(InstancePtr->IsRepeatedStart))
{ if(ByteCount > XIICPS_FIFO_DEPTH) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); XIICPS_CR_HOLD_MASK);
IsHold = 1; IsHold = 1;
} }
XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
/* /*
* Clear the interrupt status register before use it to monitor. * Clear the interrupt status register before use it to monitor.
*/ */
@ -425,8 +419,7 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
while (StatusReg & XIICPS_SR_RXDV_MASK) { while (StatusReg & XIICPS_SR_RXDV_MASK) {
if ((InstancePtr->RecvByteCount < if ((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && IsHold && XIICPS_DATA_INTR_DEPTH) && IsHold) {
(!(InstancePtr->IsRepeatedStart))) {
IsHold = 0; IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
@ -472,11 +465,9 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
} }
if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK));
(~XIICPS_CR_HOLD_MASK));
}
if (IntrStatusReg & Intrs) { if (IntrStatusReg & Intrs) {
return XST_FAILURE; return XST_FAILURE;
@ -683,8 +674,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) & while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) &
XIICPS_SR_RXDV_MASK) { XIICPS_SR_RXDV_MASK) {
if ((InstancePtr->RecvByteCount < if ((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && IsHold && XIICPS_DATA_INTR_DEPTH) && IsHold) {
(!(InstancePtr->IsRepeatedStart))) {
IsHold = 0; IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
@ -734,12 +724,10 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
* If all done, tell the application. * If all done, tell the application.
*/ */
if (InstancePtr->RecvByteCount == 0){ if (InstancePtr->RecvByteCount == 0){
if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) &
XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK));
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
} }
} }
@ -753,12 +741,10 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
} }
if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) &
XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK));
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_NACK; StatusEvent |= XIICPS_EVENT_NACK;
} }
@ -768,12 +754,10 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
if (0 != (IntrStatusReg & (XIICPS_IXR_NACK_MASK | if (0 != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK |
XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) { XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) {
if (!(InstancePtr->IsRepeatedStart)) { XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_ReadReg(BaseAddr,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) &
XIICPS_CR_OFFSET) & (~XIICPS_CR_HOLD_MASK));
(~XIICPS_CR_HOLD_MASK));
}
StatusEvent |= XIICPS_EVENT_ERROR; StatusEvent |= XIICPS_EVENT_ERROR;
} }
@ -816,7 +800,7 @@ static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
/* /*
* Only check if bus is busy when repeated start option is not set. * Only check if bus is busy when HOLD bit is not set.
*/ */
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) { if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
if (XIicPs_BusIsBusy(InstancePtr)) { if (XIicPs_BusIsBusy(InstancePtr)) {
@ -865,18 +849,10 @@ static void MasterSendData(XIicPs *InstancePtr)
* Clear hold bit if done, so stop can be sent out. * Clear hold bit if done, so stop can be sent out.
*/ */
if (InstancePtr->SendByteCount == 0) { if (InstancePtr->SendByteCount == 0) {
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
/* XIICPS_CR_OFFSET,
* If user has enabled repeated start as an option, XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
* do not disable it. XIICPS_CR_OFFSET) & ~ XIICPS_CR_HOLD_MASK);
*/
if (!(InstancePtr->IsRepeatedStart)) {
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET,
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET) & ~ XIICPS_CR_HOLD_MASK);
}
} }
return; return;

25
XilinxProcessorIPLib/drivers/iicps/src/xiicps_options.c
View file

@ -50,6 +50,7 @@
* 2.0 hk 03/07/14 Limited frequency set when 100KHz or 400KHz is * 2.0 hk 03/07/14 Limited frequency set when 100KHz or 400KHz is
* selected. This is a hardware limitation. CR#779290. * selected. This is a hardware limitation. CR#779290.
* 2.1 hk 04/24/14 Fix for CR# 761060 - provision for repeated start. * 2.1 hk 04/24/14 Fix for CR# 761060 - provision for repeated start.
* 2.3 sk 10/07/14 Repeated start feature removed.
* *
* </pre> * </pre>
* *
@ -86,7 +87,6 @@ static OptionsMap OptionsTable[] = {
{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK}, {XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK}, {XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK}, {XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
}; };
#define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap)) #define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
@ -124,16 +124,6 @@ int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); XIICPS_CR_OFFSET);
/*
* If repeated start option is requested, set the flag.
* The hold bit in CR will be written by driver when the next transfer
* is initiated.
*/
if (Options & XIICPS_REP_START_OPTION) {
InstancePtr->IsRepeatedStart = 1;
Options = Options & (~XIICPS_REP_START_OPTION);
}
/* /*
* Loop through the options table, turning the option on. * Loop through the options table, turning the option on.
*/ */
@ -203,16 +193,6 @@ int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); XIICPS_CR_OFFSET);
/*
* If repeated start option is cleared, set the flag.
* The hold bit in CR will be cleared by driver when the
* following transfer ends.
*/
if (Options & XIICPS_REP_START_OPTION) {
InstancePtr->IsRepeatedStart = 0;
Options = Options & (~XIICPS_REP_START_OPTION);
}
/* /*
* Loop through the options table and clear the specified options. * Loop through the options table and clear the specified options.
*/ */
@ -296,9 +276,6 @@ u32 XIicPs_GetOptions(XIicPs *InstancePtr)
} }
} }
if (InstancePtr->IsRepeatedStart) {
OptionsFlag |= XIICPS_REP_START_OPTION;
}
return OptionsFlag; return OptionsFlag;
} }