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BSP: Enabled asynchronous abort exception and added dafault exception handler for data abort and prefetch abort

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This patch enables asynchronous abort exception in boot.s and
adds default exception handler for data abort and prefetch abort
for debug purpose.

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2014-07-09 15:54:30 +05:30 • committed by Jagannadha Sutradharudu Teki
parent f36791aa29
commit 4830d9527a
5 changed files with 91 additions and 19 deletions
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6
lib/bsp/standalone/src/changelog.txt
View file

@ -175,4 +175,10 @@
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
* cortexa9/armcc/boot.s. Added default exception handlers for data
* abort and prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively in
* cortexa9/xil_exception.c to fix CR#802862.
*
*****************************************************************************************/

5
lib/bsp/standalone/src/cortexa9/armcc/boot.S
View file

@ -49,6 +49,7 @@
; register settings.
; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
; </pre>
;
; @note
@ -342,6 +343,10 @@ mmu_loop:
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
#ifdef PEEP
; Initialize STDOUT to 115200bps

6
lib/bsp/standalone/src/cortexa9/gcc/boot.S
View file

@ -54,6 +54,7 @@
* value of 0x00020202. Fix for CR 697094 (SI#687034).
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
* </pre>
*
* @note
@ -373,6 +374,11 @@ mmu_loop:
orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
b _start /* jump to C startup code */
and r0, r0, r0 /* no op */

91
lib/bsp/standalone/src/cortexa9/xil_exception.c
View file

@ -43,8 +43,13 @@
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 11/04/09 First release
* 3.05a sdm 02/02/12 Updated to resiter a null handler only if a handler
* is not already registered
* 3.05a sdm 02/02/12 Updated to resiter a null handler only if a handler
* is not already registered
* 4.2 pkp 06/19/14 Added default exception handlers for data abort and
* prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively
* Both handlers are registers in vector table entries
* using XExc_VectorTable
* </pre>
*
*****************************************************************************/
@ -55,7 +60,7 @@
#include "xil_assert.h"
#include "xil_exception.h"
#include "xpseudo_asm.h"
#include "xdebug.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
@ -68,12 +73,21 @@ typedef struct {
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
static void Xil_ExceptionNullHandler(void *Data);
/************************** Variable Definitions *****************************/
/*
* Exception vector table to store handlers for each exception vector.
*/
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1];
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
{
{Xil_ExceptionNullHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_PrefetchAbortHandler, NULL},
{Xil_DataAbortHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
};
/*****************************************************************************/
@ -113,20 +127,7 @@ DieLoop: goto DieLoop;
*****************************************************************************/
void Xil_ExceptionInit(void)
{
unsigned long index;
/*
* Initialize the vector table. Register the stub Handler for each
* exception.
*/
for(index = XIL_EXCEPTION_ID_FIRST; index < XIL_EXCEPTION_ID_LAST + 1;
index++) {
if (XExc_VectorTable[index].Handler == NULL) {
Xil_ExceptionRegisterHandler(index,
Xil_ExceptionNullHandler,
NULL);
}
}
return;
}
/*****************************************************************************/
@ -178,3 +179,55 @@ void Xil_ExceptionRemoveHandler(u32 exception_id)
Xil_ExceptionNullHandler,
NULL);
}
/*****************************************************************************/
/**
*
* Default Data abort handler which prints data fault status register through
* which information about data fault can be acquired
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DataAbortHandler(void *CallBackRef){
u32 FaultStatus;
#ifdef __GNUC__
FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
#else
{ volatile register unsigned int Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
FaultStatus = Reg; }
#endif
xdbg_printf(XDBG_DEBUG_ERROR, "Data abort with Data Fault Status Register %x\n",FaultStatus);
while(1);
}
/*****************************************************************************/
/**
*
* Default Prefetch abort handler which prints prefetch fault status register through
* which information about instruction prefetch fault can be acquired
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_PrefetchAbortHandler(void *CallBackRef){
u32 FaultStatus;
#ifdef __GNUC__
FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
#else
{ volatile register unsigned int Reg __asm(XREG_CP15_INST_FAULT_STATUS);
FaultStatus = Reg; }
#endif
xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
while(1);
}

2
lib/bsp/standalone/src/cortexa9/xil_exception.h
View file

@ -224,6 +224,8 @@ extern void Xil_ExceptionRegisterHandler(u32 id,
extern void Xil_ExceptionRemoveHandler(u32 id);
extern void Xil_ExceptionInit(void);
extern void Xil_DataAbortHandler(void *CallBackRef);
extern void Xil_PrefetchAbortHandler(void *CallBackRef);
#ifdef __cplusplus
}