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dptx: Updated documentation for v2_0.

Browse source 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2014-10-03 04:03:37 -07:00 • committed by Suneel Garapati
parent 24a0758d5d
commit 48ac21fccd
63 changed files with 274 additions and 136 deletions
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2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html Normal file → Executable file
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@ -40,4 +40,4 @@
<tr><td class="indexkey"><a class="el" href="struct_x_dptx___topology.html">XDptx_Topology</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="struct_x_dptx___topology_node.html">XDptx_TopologyNode</a></td><td class="indexvalue"></td></tr>
</table>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

0
XilinxProcessorIPLib/drivers/dptx/doc/html/api/doxygen.png Normal file → Executable file
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Side by side Swipe Overlay

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Width:  |  Height:  |  Size: 1.3 KiB

After

Width:  |  Height:  |  Size: 1.3 KiB

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XilinxProcessorIPLib/drivers/dptx/doc/html/api/driver_api_doxygen.css Normal file → Executable file
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@ -72,7 +72,7 @@ P.HeadingGlossary {
P.LinkGlossary {
margin-bottom: .50em;
}
}
P.Note {
}
@ -230,7 +230,7 @@ TD.indexvalue {
border: 1px solid #CCCCCC;
}
TR.memlist {
background-color: #f0f0f0;
background-color: #f0f0f0;
}
P.formulaDsp { text-align: center; }
IMG.formulaDsp { }

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html Normal file → Executable file
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@ -32,4 +32,4 @@
<tr><td class="indexkey"><a class="el" href="xdptx__spm_8c.html">xdptx_spm.c</a></td><td class="indexvalue"></td></tr>
<tr><td class="indexkey"><a class="el" href="xdptx__vidmodetable_8c.html">xdptx_vidmodetable.c</a></td><td class="indexvalue"></td></tr>
</table>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html Normal file → Executable file
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@ -219,4 +219,4 @@ Here is a list of all class members with links to the classes they belong to:
: <a class="el" href="struct_x_dptx___main_stream_attributes.html#24c34bace8bacf777271a956d91f8222">XDptx_MainStreamAttributes</a><li>YCrCbEn
: <a class="el" href="struct_x_dptx___config.html#1fa10c843358db42acdb3d5d14cecdec">XDptx_Config</a><li>YOnlyEn
: <a class="el" href="struct_x_dptx___config.html#99330a915a6ffaf0122ffd6d835175f9">XDptx_Config</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html Normal file → Executable file
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@ -219,4 +219,4 @@
: <a class="el" href="struct_x_dptx___main_stream_attributes.html#24c34bace8bacf777271a956d91f8222">XDptx_MainStreamAttributes</a><li>YCrCbEn
: <a class="el" href="struct_x_dptx___config.html#1fa10c843358db42acdb3d5d14cecdec">XDptx_Config</a><li>YOnlyEn
: <a class="el" href="struct_x_dptx___config.html#99330a915a6ffaf0122ffd6d835175f9">XDptx_Config</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html Normal file → Executable file
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@ -46,4 +46,4 @@ Here is a list of all file members with links to the files they belong to:
<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
<li>GuidTable
: <a class="el" href="xdptx__mst_8c.html#1c88b8aaf478bfe74e0dc1aa9ff29422">xdptx_mst.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x72.html Normal file → Executable file
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@ -47,4 +47,4 @@ Here is a list of all file members with links to the files they belong to:
<li>ResetValues
: <a class="el" href="xdptx__selftest_8c.html#254d7b9aa60f1abeb3c4d86ffe696039">xdptx_selftest.c</a><li>ResetValuesMsa
: <a class="el" href="xdptx__selftest_8c.html#75e026490111a3043f3f5af681d9e3ed">xdptx_selftest.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

19
XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html Normal file → Executable file
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@ -104,7 +104,8 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx__hw_8h.html#768c41baf0f19de032e8951f606a0dcf">xdptx_hw.h</a><li>XDPTX_CORE_ID_TYPE_RX
: <a class="el" href="xdptx__hw_8h.html#fc831ef5eb6d5ac9eec6537478ade75d">xdptx_hw.h</a><li>XDPTX_CORE_ID_TYPE_TX
: <a class="el" href="xdptx__hw_8h.html#a3286f7a30712bf5556860deb2165c9e">xdptx_hw.h</a><li>XDptx_DisableMainLink()
: <a class="el" href="xdptx_8h.html#0086628f0fcfab2389efb4100415df96">xdptx.h</a>, <a class="el" href="xdptx_8c.html#0086628f0fcfab2389efb4100415df96">xdptx.c</a><li>XDptx_DmtModes
: <a class="el" href="xdptx_8h.html#0086628f0fcfab2389efb4100415df96">xdptx.h</a>, <a class="el" href="xdptx_8c.html#0086628f0fcfab2389efb4100415df96">xdptx.c</a><li>XDptx_DiscoverTopology()
: <a class="el" href="xdptx__mst_8c.html#e81134f5cfd2bd5ad5826048c7c2f2dd">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#e81134f5cfd2bd5ad5826048c7c2f2dd">xdptx.h</a><li>XDptx_DmtModes
: <a class="el" href="xdptx__vidmodetable_8c.html#35408b37824862d172606842e26e66e0">xdptx_vidmodetable.c</a>, <a class="el" href="xdptx_8h.html#35408b37824862d172606842e26e66e0">xdptx.h</a><li>XDPTX_DOWNSPREAD_CTRL
: <a class="el" href="xdptx__hw_8h.html#dadb6bd439c17cd13d8fa0fc9ac5187d">xdptx_hw.h</a><li>XDPTX_DPCD_ADAPTER_CAP
: <a class="el" href="xdptx__hw_8h.html#a405c5bce815f00ce14de9b99a8f6141">xdptx_hw.h</a><li>XDPTX_DPCD_ADAPTER_CTRL
@ -420,7 +421,7 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx_8h.html#6f302303735c870085d65253bcc9acdb">xdptx.h</a>, <a class="el" href="xdptx_8c.html#6f302303735c870085d65253bcc9acdb">xdptx.c</a><li>XDPTX_ENHANCED_FRAME_EN
: <a class="el" href="xdptx__hw_8h.html#2505aad381cb4ca9d1c970523229934b">xdptx_hw.h</a><li>XDptx_EstablishLink()
: <a class="el" href="xdptx_8h.html#32b552e953f9c486a6a5e04228dcf6b6">xdptx.h</a>, <a class="el" href="xdptx_8c.html#32b552e953f9c486a6a5e04228dcf6b6">xdptx.c</a><li>XDptx_FindAccessibleDpDevices()
: <a class="el" href="xdptx__mst_8c.html#d4d2ebaad714c817b647f8d21f879eca">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#d4d2ebaad714c817b647f8d21f879eca">xdptx.h</a><li>XDPTX_FORCE_SCRAMBLER_RESET
: <a class="el" href="xdptx__mst_8c.html#03309887289769ac323f0b7e7b004dae">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#03309887289769ac323f0b7e7b004dae">xdptx.h</a><li>XDPTX_FORCE_SCRAMBLER_RESET
: <a class="el" href="xdptx__hw_8h.html#5217c3a80875b6dcda385d57c2116551">xdptx_hw.h</a><li>XDPTX_FRAC_BYTES_PER_TU
: <a class="el" href="xdptx__hw_8h.html#95e419cf6d2c09a29e29584e26120376">xdptx_hw.h</a><li>XDptx_GetEdid()
: <a class="el" href="xdptx_8h.html#23038e52574ffb4620617e4078727a0a">xdptx.h</a>, <a class="el" href="xdptx_8c.html#23038e52574ffb4620617e4078727a0a">xdptx.c</a><li>XDptx_GetGuid()
@ -461,8 +462,9 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx__hw_8h.html#283c90a2f0c3f04323effb5a07471bd8">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK
: <a class="el" href="xdptx__hw_8h.html#88b6d5d033b66d8691fb8c4366b0a86e">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK
: <a class="el" href="xdptx__hw_8h.html#82f787c0109ef901db1b7d6145d566fb">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK
: <a class="el" href="xdptx__hw_8h.html#f30bec15befd3e0c2fbbeebbfbb8f9a1">xdptx_hw.h</a><li>XDptx_IsConnected
: <a class="el" href="xdptx_8h.html#d754af91a71cc550407212fa54831a92">xdptx.h</a><li>XDPTX_LANE_COUNT_SET
: <a class="el" href="xdptx__hw_8h.html#f30bec15befd3e0c2fbbeebbfbb8f9a1">xdptx_hw.h</a><li>XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx_8c.html#b7e1f5ddc501431e93a85de17df88db4">xdptx.c</a><li>XDptx_IsConnected()
: <a class="el" href="xdptx_8h.html#44eafdd44ab545ce448b0c0476455d7c">xdptx.h</a>, <a class="el" href="xdptx_8c.html#44eafdd44ab545ce448b0c0476455d7c">xdptx.c</a><li>XDPTX_LANE_COUNT_SET
: <a class="el" href="xdptx__hw_8h.html#f0852cab2ae824fe3dfd71c8d093f143">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_1
: <a class="el" href="xdptx__hw_8h.html#a6d2c8656516aadde41a33c7a07ab3ce">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_2
: <a class="el" href="xdptx__hw_8h.html#78fa62db9e9f0427f0e24bf25084c769">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_4
@ -512,8 +514,8 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx__hw_8h.html#e1cde89ba2f6c3fdcef7fc5e8aa9c1d9">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK
: <a class="el" href="xdptx__hw_8h.html#2eaf9f11789d40c04fb868b0d8c80319">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK
: <a class="el" href="xdptx__hw_8h.html#b175eaedce85c047e38e6ff17d9d45fe">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT
: <a class="el" href="xdptx__hw_8h.html#1a50b240b33c499a4271db5ee4d4bb62">xdptx_hw.h</a><li>XDPTX_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#2ccc52eda76ccfd8c643dcdb7af55d53">xdptx_mst.c</a><li>XDPTX_MAXIMUM_PE_LEVEL
: <a class="el" href="xdptx__hw_8h.html#1a50b240b33c499a4271db5ee4d4bb62">xdptx_hw.h</a><li>XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#e85abccec81b5307fbf9a638320a7f62">xdptx_mst.c</a><li>XDPTX_MAXIMUM_PE_LEVEL
: <a class="el" href="xdptx_8c.html#e55be64e0c7523c211582a564f32c3d7">xdptx.c</a><li>XDPTX_MAXIMUM_VS_LEVEL
: <a class="el" href="xdptx_8c.html#75ec77e0967dc9325f9cc8dfb38c6079">xdptx.c</a><li>XDPTX_MIN_BYTES_PER_TU
: <a class="el" href="xdptx__hw_8h.html#c0d71f16f11b0debe9e20c47442208bf">xdptx_hw.h</a><li>XDptx_MstCapable()
@ -669,7 +671,8 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx__hw_8h.html#22adbb477c55f0ca7fc3740f53d69fed">xdptx_hw.h</a><li>XDPTX_USER_DATA_COUNT_PER_LANE
: <a class="el" href="xdptx__hw_8h.html#59420080445456a7bae12e8cdebbec5d">xdptx_hw.h</a><li>XDPTX_USER_PIXEL_WIDTH
: <a class="el" href="xdptx__hw_8h.html#2eccd9b84a12fae6acf5fa0fb7e8963d">xdptx_hw.h</a><li>XDPTX_VC_PAYLOAD_BUFFER_ADDR
: <a class="el" href="xdptx__hw_8h.html#011ee90104e02971fe66441090536110">xdptx_hw.h</a><li>XDPTX_VERSION
: <a class="el" href="xdptx__hw_8h.html#011ee90104e02971fe66441090536110">xdptx_hw.h</a><li>XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#8d5d2071b1842667aa49efa4742360ee">xdptx_mst.c</a><li>XDPTX_VERSION
: <a class="el" href="xdptx__hw_8h.html#e92176c8f7b15bf84f9aa8e25100e15c">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_PATCH_MASK
: <a class="el" href="xdptx__hw_8h.html#4f961fb9b541d128e7d7ddd4cf937d8c">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_PATCH_SHIFT
: <a class="el" href="xdptx__hw_8h.html#0043eefcacbbd52840d16b54ad877360">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_VER_MJR_MASK
@ -777,4 +780,4 @@ Here is a list of all file members with links to the files they belong to:
: <a class="el" href="xdptx_8h.html#f60126291b4c1d2ac2d054707c804dce">xdptx.h</a>, <a class="el" href="xdptx_8c.html#f60126291b4c1d2ac2d054707c804dce">xdptx.c</a><li>XDptx_WriteGuid()
: <a class="el" href="xdptx__mst_8c.html#d03f3a2b6a8262cb230ad8bc6022d648">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#d03f3a2b6a8262cb230ad8bc6022d648">xdptx.h</a><li>XDptx_WriteReg
: <a class="el" href="xdptx__hw_8h.html#740519ee4cc95e492351ad8cf9085632">xdptx_hw.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

13
XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html Normal file → Executable file
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@ -424,8 +424,8 @@
: <a class="el" href="xdptx__hw_8h.html#283c90a2f0c3f04323effb5a07471bd8">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK
: <a class="el" href="xdptx__hw_8h.html#88b6d5d033b66d8691fb8c4366b0a86e">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK
: <a class="el" href="xdptx__hw_8h.html#82f787c0109ef901db1b7d6145d566fb">xdptx_hw.h</a><li>XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK
: <a class="el" href="xdptx__hw_8h.html#f30bec15befd3e0c2fbbeebbfbb8f9a1">xdptx_hw.h</a><li>XDptx_IsConnected
: <a class="el" href="xdptx_8h.html#d754af91a71cc550407212fa54831a92">xdptx.h</a><li>XDPTX_LANE_COUNT_SET
: <a class="el" href="xdptx__hw_8h.html#f30bec15befd3e0c2fbbeebbfbb8f9a1">xdptx_hw.h</a><li>XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx_8c.html#b7e1f5ddc501431e93a85de17df88db4">xdptx.c</a><li>XDPTX_LANE_COUNT_SET
: <a class="el" href="xdptx__hw_8h.html#f0852cab2ae824fe3dfd71c8d093f143">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_1
: <a class="el" href="xdptx__hw_8h.html#a6d2c8656516aadde41a33c7a07ab3ce">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_2
: <a class="el" href="xdptx__hw_8h.html#78fa62db9e9f0427f0e24bf25084c769">xdptx_hw.h</a><li>XDPTX_LANE_COUNT_SET_4
@ -474,8 +474,8 @@
: <a class="el" href="xdptx__hw_8h.html#e1cde89ba2f6c3fdcef7fc5e8aa9c1d9">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK
: <a class="el" href="xdptx__hw_8h.html#2eaf9f11789d40c04fb868b0d8c80319">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK
: <a class="el" href="xdptx__hw_8h.html#b175eaedce85c047e38e6ff17d9d45fe">xdptx_hw.h</a><li>XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT
: <a class="el" href="xdptx__hw_8h.html#1a50b240b33c499a4271db5ee4d4bb62">xdptx_hw.h</a><li>XDPTX_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#2ccc52eda76ccfd8c643dcdb7af55d53">xdptx_mst.c</a><li>XDPTX_MAXIMUM_PE_LEVEL
: <a class="el" href="xdptx__hw_8h.html#1a50b240b33c499a4271db5ee4d4bb62">xdptx_hw.h</a><li>XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#e85abccec81b5307fbf9a638320a7f62">xdptx_mst.c</a><li>XDPTX_MAXIMUM_PE_LEVEL
: <a class="el" href="xdptx_8c.html#e55be64e0c7523c211582a564f32c3d7">xdptx.c</a><li>XDPTX_MAXIMUM_VS_LEVEL
: <a class="el" href="xdptx_8c.html#75ec77e0967dc9325f9cc8dfb38c6079">xdptx.c</a><li>XDPTX_MIN_BYTES_PER_TU
: <a class="el" href="xdptx__hw_8h.html#c0d71f16f11b0debe9e20c47442208bf">xdptx_hw.h</a><li>XDPTX_N_VID
@ -593,7 +593,8 @@
: <a class="el" href="xdptx__hw_8h.html#22adbb477c55f0ca7fc3740f53d69fed">xdptx_hw.h</a><li>XDPTX_USER_DATA_COUNT_PER_LANE
: <a class="el" href="xdptx__hw_8h.html#59420080445456a7bae12e8cdebbec5d">xdptx_hw.h</a><li>XDPTX_USER_PIXEL_WIDTH
: <a class="el" href="xdptx__hw_8h.html#2eccd9b84a12fae6acf5fa0fb7e8963d">xdptx_hw.h</a><li>XDPTX_VC_PAYLOAD_BUFFER_ADDR
: <a class="el" href="xdptx__hw_8h.html#011ee90104e02971fe66441090536110">xdptx_hw.h</a><li>XDPTX_VERSION
: <a class="el" href="xdptx__hw_8h.html#011ee90104e02971fe66441090536110">xdptx_hw.h</a><li>XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT
: <a class="el" href="xdptx__mst_8c.html#8d5d2071b1842667aa49efa4742360ee">xdptx_mst.c</a><li>XDPTX_VERSION
: <a class="el" href="xdptx__hw_8h.html#e92176c8f7b15bf84f9aa8e25100e15c">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_PATCH_MASK
: <a class="el" href="xdptx__hw_8h.html#4f961fb9b541d128e7d7ddd4cf937d8c">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_PATCH_SHIFT
: <a class="el" href="xdptx__hw_8h.html#0043eefcacbbd52840d16b54ad877360">xdptx_hw.h</a><li>XDPTX_VERSION_CORE_VER_MJR_MASK
@ -610,4 +611,4 @@
: <a class="el" href="xdptx__hw_8h.html#5d28772a94530d91c12e8aa054380280">xdptx_hw.h</a><li>XDPTX_VS_LEVEL_OFFSET
: <a class="el" href="xdptx__hw_8h.html#7852023a12302535fd5aef02adf966a2">xdptx_hw.h</a><li>XDptx_WriteReg
: <a class="el" href="xdptx__hw_8h.html#740519ee4cc95e492351ad8cf9085632">xdptx_hw.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -38,4 +38,4 @@
<li>XDptx_TrainingState
: <a class="el" href="xdptx_8c.html#cd850705884d914c6c8468f61336f06d">xdptx.c</a><li>XDptx_VideoMode
: <a class="el" href="xdptx_8h.html#af8a64fd1433b74b07e2b2081a9c2fa6">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -137,4 +137,4 @@
: <a class="el" href="xdptx_8h.html#af8a64fd1433b74b07e2b2081a9c2fa68bc8919957e4ed8bc05af5b7d4346d32">xdptx.h</a><li>XDPTX_VM_UHD_60
: <a class="el" href="xdptx_8h.html#af8a64fd1433b74b07e2b2081a9c2fa630e184be3f6863e1e08352ce7c7cdb45">xdptx.h</a><li>XDPTX_VM_USE_EDID_PREFERRED
: <a class="el" href="xdptx_8h.html#af8a64fd1433b74b07e2b2081a9c2fa65ec3529a1af698bc7ec52ebdc532fc7f">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

10
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@ -61,11 +61,12 @@
: <a class="el" href="xdptx_8h.html#e85ec3a02cdf8f8ffd611e026bf9ff01">xdptx.h</a>, <a class="el" href="xdptx_8c.html#e85ec3a02cdf8f8ffd611e026bf9ff01">xdptx.c</a><li>XDptx_ClearMsaValues()
: <a class="el" href="xdptx__spm_8c.html#ed928effbb7778d00af50ecfa3a1dafc">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#ed928effbb7778d00af50ecfa3a1dafc">xdptx.h</a><li>XDptx_ClearPayloadVcIdTable()
: <a class="el" href="xdptx__mst_8c.html#d460e5bed77a33b7f1eb59011bd61641">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#d460e5bed77a33b7f1eb59011bd61641">xdptx.h</a><li>XDptx_DisableMainLink()
: <a class="el" href="xdptx_8h.html#0086628f0fcfab2389efb4100415df96">xdptx.h</a>, <a class="el" href="xdptx_8c.html#0086628f0fcfab2389efb4100415df96">xdptx.c</a><li>XDptx_EnableMainLink()
: <a class="el" href="xdptx_8h.html#0086628f0fcfab2389efb4100415df96">xdptx.h</a>, <a class="el" href="xdptx_8c.html#0086628f0fcfab2389efb4100415df96">xdptx.c</a><li>XDptx_DiscoverTopology()
: <a class="el" href="xdptx__mst_8c.html#e81134f5cfd2bd5ad5826048c7c2f2dd">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#e81134f5cfd2bd5ad5826048c7c2f2dd">xdptx.h</a><li>XDptx_EnableMainLink()
: <a class="el" href="xdptx_8h.html#0f43683ba44e5e1544042be2bcfc45de">xdptx.h</a>, <a class="el" href="xdptx_8c.html#0f43683ba44e5e1544042be2bcfc45de">xdptx.c</a><li>XDptx_EnableTrainAdaptive()
: <a class="el" href="xdptx_8h.html#6f302303735c870085d65253bcc9acdb">xdptx.h</a>, <a class="el" href="xdptx_8c.html#6f302303735c870085d65253bcc9acdb">xdptx.c</a><li>XDptx_EstablishLink()
: <a class="el" href="xdptx_8h.html#32b552e953f9c486a6a5e04228dcf6b6">xdptx.h</a>, <a class="el" href="xdptx_8c.html#32b552e953f9c486a6a5e04228dcf6b6">xdptx.c</a><li>XDptx_FindAccessibleDpDevices()
: <a class="el" href="xdptx__mst_8c.html#d4d2ebaad714c817b647f8d21f879eca">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#d4d2ebaad714c817b647f8d21f879eca">xdptx.h</a><li>XDptx_GetEdid()
: <a class="el" href="xdptx__mst_8c.html#03309887289769ac323f0b7e7b004dae">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#03309887289769ac323f0b7e7b004dae">xdptx.h</a><li>XDptx_GetEdid()
: <a class="el" href="xdptx_8h.html#23038e52574ffb4620617e4078727a0a">xdptx.h</a>, <a class="el" href="xdptx_8c.html#23038e52574ffb4620617e4078727a0a">xdptx.c</a><li>XDptx_GetGuid()
: <a class="el" href="xdptx__mst_8c.html#ef32287d856ac7ab17a50e5600b6a9d6">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#ef32287d856ac7ab17a50e5600b6a9d6">xdptx.h</a><li>XDptx_GetRemoteEdid()
: <a class="el" href="xdptx__mst_8c.html#3cec2b8fa349961931ec5b57c2d614df">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#3cec2b8fa349961931ec5b57c2d614df">xdptx.h</a><li>XDptx_GetRxCapabilities()
@ -73,7 +74,8 @@
: <a class="el" href="xdptx__intr_8c.html#42ad278e82e98ad5440ced0791eb1232">xdptx_intr.c</a>, <a class="el" href="xdptx_8h.html#42ad278e82e98ad5440ced0791eb1232">xdptx.h</a><li>XDptx_IicRead()
: <a class="el" href="xdptx_8h.html#fa48be4f79ab6db64c359ce99b2684f2">xdptx.h</a>, <a class="el" href="xdptx_8c.html#fa48be4f79ab6db64c359ce99b2684f2">xdptx.c</a><li>XDptx_IicWrite()
: <a class="el" href="xdptx_8h.html#4bf3b5bebfa79de9e3fdc1a982559e2c">xdptx.h</a>, <a class="el" href="xdptx_8c.html#4bf3b5bebfa79de9e3fdc1a982559e2c">xdptx.c</a><li>XDptx_InitializeTx()
: <a class="el" href="xdptx_8h.html#b2fbc41e2f0ac4471e4edbf71d877af3">xdptx.h</a>, <a class="el" href="xdptx_8c.html#b2fbc41e2f0ac4471e4edbf71d877af3">xdptx.c</a><li>XDptx_LookupConfig()
: <a class="el" href="xdptx_8h.html#b2fbc41e2f0ac4471e4edbf71d877af3">xdptx.h</a>, <a class="el" href="xdptx_8c.html#b2fbc41e2f0ac4471e4edbf71d877af3">xdptx.c</a><li>XDptx_IsConnected()
: <a class="el" href="xdptx_8h.html#44eafdd44ab545ce448b0c0476455d7c">xdptx.h</a>, <a class="el" href="xdptx_8c.html#44eafdd44ab545ce448b0c0476455d7c">xdptx.c</a><li>XDptx_LookupConfig()
: <a class="el" href="xdptx__sinit_8c.html#32ba0cb6907ed3d2ecfdb31c699db3b4">xdptx_sinit.c</a>, <a class="el" href="xdptx_8h.html#32ba0cb6907ed3d2ecfdb31c699db3b4">xdptx.h</a><li>XDptx_MstCapable()
: <a class="el" href="xdptx__mst_8c.html#04c0a0cf85542a721ce4a0ef4bcf75b0">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#04c0a0cf85542a721ce4a0ef4bcf75b0">xdptx.h</a><li>XDptx_MstCfgModeDisable()
: <a class="el" href="xdptx__mst_8c.html#2ee695f7ae87c5c4562c6476363c0c00">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#2ee695f7ae87c5c4562c6476363c0c00">xdptx.h</a><li>XDptx_MstCfgModeEnable()
@ -107,4 +109,4 @@
: <a class="el" href="xdptx__spm_8c.html#8c94639847747642864da0f053598cea">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#8c94639847747642864da0f053598cea">xdptx.h</a><li>XDptx_WaitUs()
: <a class="el" href="xdptx_8h.html#f60126291b4c1d2ac2d054707c804dce">xdptx.h</a>, <a class="el" href="xdptx_8c.html#f60126291b4c1d2ac2d054707c804dce">xdptx.c</a><li>XDptx_WriteGuid()
: <a class="el" href="xdptx__mst_8c.html#d03f3a2b6a8262cb230ad8bc6022d648">xdptx_mst.c</a>, <a class="el" href="xdptx_8h.html#d03f3a2b6a8262cb230ad8bc6022d648">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -39,4 +39,4 @@
: <a class="el" href="xdptx_8h.html#55e031231c2489c71c5b0187f8b2941e">xdptx.h</a><li>XDptx_HpdPulseHandler
: <a class="el" href="xdptx_8h.html#26acfa8f4b98b86385c7095bd3668313">xdptx.h</a><li>XDptx_TimerHandler
: <a class="el" href="xdptx_8h.html#c09d771f709e37e756d8de2ba627701f">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -41,4 +41,4 @@
: <a class="el" href="xdptx__selftest_8c.html#75e026490111a3043f3f5af681d9e3ed">xdptx_selftest.c</a><li>XDptx_ConfigTable
: <a class="el" href="xdptx__sinit_8c.html#fb75a3dfcbf84256620c004c99e47b47">xdptx_sinit.c</a><li>XDptx_DmtModes
: <a class="el" href="xdptx__vidmodetable_8c.html#35408b37824862d172606842e26e66e0">xdptx_vidmodetable.c</a>, <a class="el" href="xdptx_8h.html#35408b37824862d172606842e26e66e0">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -2,7 +2,7 @@
<head>
<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>
dptx v1_0
dptx v2_0
</title>
<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
</head>
@ -16,7 +16,7 @@
<li><a href="annotated.html"><span>Classes</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul></div>
<h1>dptx v1_0</h1>
<h1>dptx v2_0</h1>
<p>
The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.<p>
The Xilinx DisplayPort soft IP supports the following features:<ul>
@ -46,20 +46,22 @@ The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of inter
The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.<p>
<b>Multi-stream transport (MST) mode</b><p>
The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.<p>
MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy- chain configuration, with each stream having the same resolution. Extensive testing has been done at resolutions of 1080p for each of 1 to 4 streams and UHD/2 for each of 1 or 2 streams. Other resolutions have been tested as well, however with the current version of the driver, some monitors required a power cycle for all streams to come up.<p>
MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy- chain configuration, with each stream having the same resolution. Testing has been done at the following resolutions: 640x480, 720x480, 800x600, 848x480, 1024x768, 1280x720, 1280x1024, 1080p, and UHD (UHD/2 on 2 streams). Each resolutions was tested at 24 bits per pixel using 1, 2, 3, and 4 streams. Color depths of 18, 30, 36, and 48 bits per pixel were also tested.<p>
<b>Audio</b><p>
The driver does not handle audio. For an example as to how to configure and transmit audio, dptx/examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.<p>
<b>Asserts</b><p>
Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.<p>
<b>Limitations and known issues</b><p>
<ul>
<li>For MST mode to correctly display, the current version of the driver requires that each of the DisplayPort TX streams be allocated without skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems were experienced if skipping stream 2 and assigning stream 4 instead). skipping monitors in a daisy chain is OK as long as they are assigned to streams in order.</li><li>In MST mode, the current version of the driver does not support removal of an allocated stream from the virtual channel payload ID table without clearing the entire table.</li><li>Some sideband messages have not been implemented in the current version of the driver for MST mode. Notable, reception of a CONNECTION_STATUS_NOTIFY sideband message.</li><li>Some monitors required a power cycle for all streams to come up at certain resolutions (outside of the 1080p and UHD/2 resolutions) during testing. Different resolutions for different streams were not tested. This will be investigated for the next SDK release.</li><li>The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.</li><li>Limited testing was done with 4-byte GT data width.</li><li>Most testing was done on a KC705 board. Some testing was done on a ZC706 board, mostly with a 2-byte GT data width configuration.</li></ul>
<li>For MST mode to correctly display, the current version of the driver requires that each of the DisplayPort TX streams be allocated without skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems were experienced if skipping stream 2 and assigning stream 4 instead). skipping monitors in a daisy chain is OK as long as they are assigned to streams in order.</li><li>In MST mode, the current version of the driver does not support removal of an allocated stream from the virtual channel payload ID table without clearing the entire table.</li><li>Some sideband messages have not been implemented in the current version of the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY sideband message.</li><li>The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.</li></ul>
<p>
<dl compact><dt><b>Note:</b></dt><dd>For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
als 08/03/14 Initial MST addition.
</pre> Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
2.0 als 09/21/14 Added XDptx_DiscoverTopology function and changed
XDptx_IsConnected from macro to function.
</pre> Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -40,4 +40,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx.html#cec7536fbd35b65e8ef4bba747753408">TrainAdaptive</a></td><td><a class="el" href="struct_x_dptx.html">XDptx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx.html#fbdd98ca9563d3f2fc595ea2d6f6053b">UserTimerPtr</a></td><td><a class="el" href="struct_x_dptx.html">XDptx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx.html#67a7c4a7e698ddb155ceaccbf196e82d">UserTimerWaitUs</a></td><td><a class="el" href="struct_x_dptx.html">XDptx</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -339,4 +339,4 @@ Custom user function for delay/sleep.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -26,4 +26,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___aux_transaction.html#6021746dd336cee5d088c60e392f4715">CmdCode</a></td><td><a class="el" href="struct_x_dptx___aux_transaction.html">XDptx_AuxTransaction</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___aux_transaction.html#640f8650a69e0d84d62a30380e16f1f7">Data</a></td><td><a class="el" href="struct_x_dptx___aux_transaction.html">XDptx_AuxTransaction</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___aux_transaction.html#1094c402f5586820a861ef51b484afc9">NumBytes</a></td><td><a class="el" href="struct_x_dptx___aux_transaction.html">XDptx_AuxTransaction</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -99,4 +99,4 @@ The number of bytes that the AUX transaction will perform work on.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8c.html">xdptx.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -26,4 +26,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___board_char.html#233d67fb074144dc758b374a53656653">TxPeLevels</a></td><td><a class="el" href="struct_x_dptx___board_char.html">XDptx_BoardChar</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___board_char.html#1f86ede802e61054b30ea009ac76388a">TxVsLevels</a></td><td><a class="el" href="struct_x_dptx___board_char.html">XDptx_BoardChar</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___board_char.html#8604c9cef09467cb18d7057d4a33aed4">TxVsOffset</a></td><td><a class="el" href="struct_x_dptx___board_char.html">XDptx_BoardChar</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -101,4 +101,4 @@ Voltage swing compensation offset used when pre-emphasis is used.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -38,4 +38,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___config.html#76a6d413d59c2c6386a2dff120137cb9">SecondaryChEn</a></td><td><a class="el" href="struct_x_dptx___config.html">XDptx_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___config.html#1fa10c843358db42acdb3d5d14cecdec">YCrCbEn</a></td><td><a class="el" href="struct_x_dptx___config.html">XDptx_Config</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___config.html#99330a915a6ffaf0122ffd6d835175f9">YOnlyEn</a></td><td><a class="el" href="struct_x_dptx___config.html">XDptx_Config</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -305,4 +305,4 @@ YOnly format support by this core instance.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -36,4 +36,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___dmt_mode.html#6adcccc2989a52ded87b891dbc0b3269">VResolution</a></td><td><a class="el" href="struct_x_dptx___dmt_mode.html">XDptx_DmtMode</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___dmt_mode.html#78ca69a627d19d1053438e5b33f016eb">VSyncPolarity</a></td><td><a class="el" href="struct_x_dptx___dmt_mode.html">XDptx_DmtMode</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___dmt_mode.html#4bcfd12f87dbbdd45c73e7bfe97f7237">VSyncPulseWidth</a></td><td><a class="el" href="struct_x_dptx___dmt_mode.html">XDptx_DmtMode</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -271,4 +271,4 @@ Vertical synchronization time (pulse width in lines).
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -34,4 +34,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___link_config.html#c1db31ca7c0a5fa2aaae11bda9fb017e">SupportDownspreadControl</a></td><td><a class="el" href="struct_x_dptx___link_config.html">XDptx_LinkConfig</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___link_config.html#59939d764ba165541fba7f0faef7f795">SupportEnhancedFramingMode</a></td><td><a class="el" href="struct_x_dptx___link_config.html">XDptx_LinkConfig</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___link_config.html#b8f73fd6a35a3a71e25647fa6d04e17e">VsLevel</a></td><td><a class="el" href="struct_x_dptx___link_config.html">XDptx_LinkConfig</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -237,4 +237,4 @@ The current voltage swing level for each lane.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -41,4 +41,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#73f075b7b7e23ceca800329dbe17db1c">VClkTotal</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#0da4f2d63d9456f1c3fbce9dff315577">VStart</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#24c34bace8bacf777271a956d91f8222">YCbCrColorimetry</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -356,4 +356,4 @@ The YCbCr colorimetry currently in use by the video stream.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -26,4 +26,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___mst_stream.html#e1c99f9aedb36dbaf64095f508e13143">MstPbn</a></td><td><a class="el" href="struct_x_dptx___mst_stream.html">XDptx_MstStream</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___mst_stream.html#6a69e59854c88800f8d994ae71598eb9">MstStreamEnable</a></td><td><a class="el" href="struct_x_dptx___mst_stream.html">XDptx_MstStream</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___mst_stream.html#abf60ba0177df02815db35457da88503">RelativeAddress</a></td><td><a class="el" href="struct_x_dptx___mst_stream.html">XDptx_MstStream</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -101,4 +101,4 @@ The total number of DisplayPort links from the DisplayPort TX to the sink device
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -27,4 +27,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#1b04f2070c81120203524c760f1164a0">PortDetails</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html">XDptx_SbMsgLinkAddressReplyDeviceInfo</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#9064e55044245b2369c17ac70a817670">ReplyType</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html">XDptx_SbMsgLinkAddressReplyDeviceInfo</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#6036b7308d611ca6c36b1a15aed2aca4">RequestId</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html">XDptx_SbMsgLinkAddressReplyDeviceInfo</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info.html Normal file → Executable file
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@ -118,4 +118,4 @@ The request identifier of the reply. This should correspond to the request ident
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail-members.html Normal file → Executable file
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@ -32,4 +32,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#2f6a6889e2000f58bc7a75f38d0a34b5">NumSdpStreamSinks</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html">XDptx_SbMsgLinkAddressReplyPortDetail</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#a162737e3f61ba2e95dee07d502ffcad">PeerDeviceType</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html">XDptx_SbMsgLinkAddressReplyPortDetail</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#ed947f0acad32ab7418a2c30c2774a18">PortNum</a></td><td><a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html">XDptx_SbMsgLinkAddressReplyPortDetail</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -203,4 +203,4 @@ The port number of this port.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg-members.html Normal file → Executable file
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@ -24,4 +24,4 @@
<h1>XDptx_SidebandMsg Member List</h1>This is the complete list of members for <a class="el" href="struct_x_dptx___sideband_msg.html">XDptx_SidebandMsg</a>, including all inherited members.<p><table>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg.html#c7e8841e3f6d7f14d0ef6dbdbedeed84">Body</a></td><td><a class="el" href="struct_x_dptx___sideband_msg.html">XDptx_SidebandMsg</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg.html#d0b1537142740ed9b1df7d06cea83d92">Header</a></td><td><a class="el" href="struct_x_dptx___sideband_msg.html">XDptx_SidebandMsg</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -65,4 +65,4 @@ The header segment of the sideband message.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx__mst_8c.html">xdptx_mst.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -25,4 +25,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_body.html#b02f1dfe100c7fbfc2327a6b0b21fb86">Crc</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_body.html">XDptx_SidebandMsgBody</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_body.html#adb016273a6859a42be0594f9a90f1c6">MsgData</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_body.html">XDptx_SidebandMsgBody</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_body.html#5ac6d3bcf5323dc28ba7356b1b764f25">MsgDataLength</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_body.html">XDptx_SidebandMsgBody</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -82,4 +82,4 @@ The number of data bytes stored as part of the sideband message body.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx__mst_8c.html">xdptx_mst.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -33,4 +33,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_header.html#5580e4b73c1bd97c43cec826dc7540de">PathMsg</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_header.html">XDptx_SidebandMsgHeader</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_header.html#78b0f0742716a90609747483f7adf824">RelativeAddress</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_header.html">XDptx_SidebandMsgHeader</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_msg_header.html#8ed85ed1a26348f53358da7307400544">StartOfMsgTransaction</a></td><td><a class="el" href="struct_x_dptx___sideband_msg_header.html">XDptx_SidebandMsgHeader</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -218,4 +218,4 @@ This message is the first sideband message in the transaction.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx__mst_8c.html">xdptx_mst.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply-members.html Normal file → Executable file
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@ -24,4 +24,4 @@
<h1>XDptx_SidebandReply Member List</h1>This is the complete list of members for <a class="el" href="struct_x_dptx___sideband_reply.html">XDptx_SidebandReply</a>, including all inherited members.<p><table>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_reply.html#66b3e17b57373f2ff8f14258d0b98efc">Data</a></td><td><a class="el" href="struct_x_dptx___sideband_reply.html">XDptx_SidebandReply</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sideband_reply.html#832603fdaf9c9ab9dba027233995efa5">Length</a></td><td><a class="el" href="struct_x_dptx___sideband_reply.html">XDptx_SidebandReply</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -65,4 +65,4 @@ The number of bytes of reply data.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx__mst_8c.html">xdptx_mst.c</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -24,4 +24,4 @@
<h1>XDptx_SinkConfig Member List</h1>This is the complete list of members for <a class="el" href="struct_x_dptx___sink_config.html">XDptx_SinkConfig</a>, including all inherited members.<p><table>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sink_config.html#e270033c74fec65bcbdc3d71c95de582">DpcdRxCapsField</a></td><td><a class="el" href="struct_x_dptx___sink_config.html">XDptx_SinkConfig</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___sink_config.html#5231c72310b967fc7c2ad13cd7571d52">LaneStatusAdjReqs</a></td><td><a class="el" href="struct_x_dptx___sink_config.html">XDptx_SinkConfig</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -67,4 +67,4 @@ This is a raw read of the RX device's status registers. The first 4 bytes corres
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -26,4 +26,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology.html#ad5b55de5668c6dc5d23b78daf043717">NodeTotal</a></td><td><a class="el" href="struct_x_dptx___topology.html">XDptx_Topology</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology.html#a2226d73d19995d01005a51b5a53f739">SinkList</a></td><td><a class="el" href="struct_x_dptx___topology.html">XDptx_Topology</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology.html#20702947b2076eb482876c65620e64ad">SinkTotal</a></td><td><a class="el" href="struct_x_dptx___topology.html">XDptx_Topology</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -101,4 +101,4 @@ The total number of sinks in the MST topology.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -28,4 +28,4 @@
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology_node.html#2a9bb7fa2249a7c4c0faec1907ac6413">LinkCountTotal</a></td><td><a class="el" href="struct_x_dptx___topology_node.html">XDptx_TopologyNode</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology_node.html#a2d5970c955f2a407f0d2d3329ff3cab">MsgCapStatus</a></td><td><a class="el" href="struct_x_dptx___topology_node.html">XDptx_TopologyNode</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="struct_x_dptx___topology_node.html#77f6e45550ce5917631df34338c60a7e">RelativeAddress</a></td><td><a class="el" href="struct_x_dptx___topology_node.html">XDptx_TopologyNode</a></td><td></td></tr>
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
</table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

2
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@ -135,4 +135,4 @@ The relative address from the DisplayPort TX to this device.
</div><p>
<hr>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="xdptx_8h.html">xdptx.h</a></ul>
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

0
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@ -28,7 +28,8 @@ Contains a minimal set of functions for the <a class="el" href="struct_x_dptx.ht
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
2.0 als 09/21/14 Added XDptx_IsConnected (previously a macro).
</pre>
<p>
<code>#include &quot;<a class="el" href="xdptx_8h.html">xdptx.h</a>&quot;</code><br>
@ -48,6 +49,8 @@ Contains a minimal set of functions for the <a class="el" href="struct_x_dptx.ht
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#262c9ca1b03f1dcd681e8e275f2160df">XDPTX_AUX_MAX_TIMEOUT_COUNT</a>&nbsp;&nbsp;&nbsp;50</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#b7e1f5ddc501431e93a85de17df88db4">XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT</a>&nbsp;&nbsp;&nbsp;50</td></tr>
<tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#cd850705884d914c6c8468f61336f06d">XDptx_TrainingState</a> { <br>
&nbsp;&nbsp;<a class="el" href="xdptx_8c.html#cd850705884d914c6c8468f61336f06d3fa23640bdcae70ef187d6089348d8e8">XDPTX_TS_CLOCK_RECOVERY</a>,
@ -85,6 +88,8 @@ Contains a minimal set of functions for the <a class="el" href="struct_x_dptx.ht
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#a6815e6062e47eecfd9616eaa15a19a1">XDptx_CfgTxPeLevel</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Level, u8 TxLevel)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#44eafdd44ab545ce448b0c0476455d7c">XDptx_IsConnected</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#591d601b5e6913df09ad73ea92881e31">XDptx_AuxRead</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u32 Address, u32 NumBytes, void *Data)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8c.html#690a6ee9d1b4df0624967cb00892347b">XDptx_AuxWrite</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u32 Address, u32 NumBytes, void *Data)</td></tr>
@ -143,6 +148,21 @@ Contains a minimal set of functions for the <a class="el" href="struct_x_dptx.ht
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<a class="anchor" name="b7e1f5ddc501431e93a85de17df88db4"></a><!-- doxytag: member="xdptx.c::XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT" ref="b7e1f5ddc501431e93a85de17df88db4" args="" -->
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<td class="memname">#define XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT&nbsp;&nbsp;&nbsp;50 </td>
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<a class="anchor" name="e55be64e0c7523c211582a564f32c3d7"></a><!-- doxytag: member="xdptx.c::XDPTX_MAXIMUM_PE_LEVEL" ref="e55be64e0c7523c211582a564f32c3d7" args="" -->
@ -903,6 +923,35 @@ This function prepares the DisplayPort TX core for use.<p>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
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<a class="anchor" name="44eafdd44ab545ce448b0c0476455d7c"></a><!-- doxytag: member="xdptx.c::XDptx_IsConnected" ref="44eafdd44ab545ce448b0c0476455d7c" args="(XDptx *InstancePtr)" -->
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<td class="memname">u32 XDptx_IsConnected </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_dptx.html">XDptx</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em> </td>
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This function checks if there is a connected RX device.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance.</td></tr>
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</dl>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>TRUE if there is a connection.</li><li>FALSE if there is no connection. </li></ul>
</dd></dl>
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<a class="anchor" name="a71e17a951f445b9c7bcfcc3104cdf4c"></a><!-- doxytag: member="xdptx.c::XDptx_ResetPhy" ref="a71e17a951f445b9c7bcfcc3104cdf4c" args="(XDptx *InstancePtr, u32 Reset)" -->
@ -1266,4 +1315,4 @@ This function is the delay/sleep function for the <a class="el" href="struct_x_d
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -53,9 +53,6 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx.html">XDptx</a></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#d754af91a71cc550407212fa54831a92">XDptx_IsConnected</a>(InstancePtr)</td></tr>
<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#c09d771f709e37e756d8de2ba627701f">XDptx_TimerHandler</a> (void *InstancePtr, u32 MicroSeconds)</td></tr>
@ -220,6 +217,8 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#3e9dee7b0b7711677c8c39fd14d585c8">XDptx_SetScrambler</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Enable)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#44eafdd44ab545ce448b0c0476455d7c">XDptx_IsConnected</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#0f43683ba44e5e1544042be2bcfc45de">XDptx_EnableMainLink</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#0086628f0fcfab2389efb4100415df96">XDptx_DisableMainLink</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
@ -278,7 +277,9 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#895b0d104c1772fe0f60c879cd0a2b82">XDptx_SetStreamSinkRad</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#d4d2ebaad714c817b647f8d21f879eca">XDptx_FindAccessibleDpDevices</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#e81134f5cfd2bd5ad5826048c7c2f2dd">XDptx_DiscoverTopology</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#03309887289769ac323f0b7e7b004dae">XDptx_FindAccessibleDpDevices</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#a688873fb1701355cbb33ac5d25d3da2">XDptx_AllocatePayloadStreams</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
@ -310,39 +311,6 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct_x_dptx___dmt_mode.html">XDptx_DmtMode</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#35408b37824862d172606842e26e66e0">XDptx_DmtModes</a> []</td></tr>
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<hr><h2>Define Documentation</h2>
<a class="anchor" name="d754af91a71cc550407212fa54831a92"></a><!-- doxytag: member="xdptx.h::XDptx_IsConnected" ref="d754af91a71cc550407212fa54831a92" args="(InstancePtr)" -->
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<td class="memname">#define XDptx_IsConnected </td>
<td>(</td>
<td class="paramtype">InstancePtr&nbsp;</td>
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<b>Value:</b><div class="fragment"><pre class="fragment">(<a class="code" href="xdptx__hw_8h.html#b9ae114efe97122a7a212baf3a27d5fe">XDptx_ReadReg</a>(InstancePtr-&gt;Config.BaseAddr, \
<a class="code" href="xdptx__hw_8h.html#0f779ac12934252a5548f520e776b1e8">XDPTX_INTERRUPT_SIG_STATE</a>) &amp; <a class="code" href="xdptx__hw_8h.html#97bafe03ef5703095f172353e91b1b9c">XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK</a>)
</pre></div>This macro checks if there is a connected RX device.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance.</td></tr>
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</dl>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>TRUE if there is a connection.</li><li>FALSE if there is no connection.</li></ul>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xdptx_8h.html#d754af91a71cc550407212fa54831a92">XDptx_IsConnected(XDptx *InstancePtr)</a> </dd></dl>
</div>
</div><p>
<hr><h2>Typedef Documentation</h2>
<a class="anchor" name="55e031231c2489c71c5b0187f8b2941e"></a><!-- doxytag: member="xdptx.h::XDptx_HpdEventHandler" ref="55e031231c2489c71c5b0187f8b2941e" args="(void *InstancePtr)" -->
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@ -1442,6 +1410,36 @@ This function disables the main link.<p>
<dl compact><dt><b>Returns:</b></dt><dd>None.</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
</div>
</div><p>
<a class="anchor" name="e81134f5cfd2bd5ad5826048c7c2f2dd"></a><!-- doxytag: member="xdptx.h::XDptx_DiscoverTopology" ref="e81134f5cfd2bd5ad5826048c7c2f2dd" args="(XDptx *InstancePtr)" -->
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<td class="memname">u32 XDptx_DiscoverTopology </td>
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<td class="paramtype"><a class="el" href="struct_x_dptx.html">XDptx</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em> </td>
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This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance.</td></tr>
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</dl>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the topology discovery is successful.</li><li>XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.</li></ul>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>The contents of the InstancePtr-&gt;Topology structure will be modified. </dd></dl>
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<a class="anchor" name="0f43683ba44e5e1544042be2bcfc45de"></a><!-- doxytag: member="xdptx.h::XDptx_EnableMainLink" ref="0f43683ba44e5e1544042be2bcfc45de" args="(XDptx *InstancePtr)" -->
@ -1540,12 +1538,12 @@ This function checks if the link needs training and runs the training sequence i
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<a class="anchor" name="d4d2ebaad714c817b647f8d21f879eca"></a><!-- doxytag: member="xdptx.h::XDptx_FindAccessibleDpDevices" ref="d4d2ebaad714c817b647f8d21f879eca" args="(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)" -->
<a class="anchor" name="03309887289769ac323f0b7e7b004dae"></a><!-- doxytag: member="xdptx.h::XDptx_FindAccessibleDpDevices" ref="03309887289769ac323f0b7e7b004dae" args="(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)" -->
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<td class="memname">void XDptx_FindAccessibleDpDevices </td>
<td class="memname">u32 XDptx_FindAccessibleDpDevices </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_dptx.html">XDptx</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em>, </td>
@ -1572,7 +1570,7 @@ This function checks if the link needs training and runs the training sequence i
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<p>
This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance. </td></tr>
@ -1580,7 +1578,9 @@ This function will explore the DisplayPort topology of downstream devices connec
<tr><td valign="top"></td><td valign="top"><em>RelativeAddress</em>&nbsp;</td><td>is the relative address from the DisplayPort source to the current target DisplayPort device in the recursion.</td></tr>
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<dl compact><dt><b>Returns:</b></dt><dd>None - the recursion will exit from nodes that have an error when replying to the LINK_ADDRESS sideband message.</dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the topology discovery is successful.</li><li>XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.</li></ul>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>The contents of the InstancePtr-&gt;Topology structure will be modified. </dd></dl>
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@ -1940,6 +1940,35 @@ This function prepares the DisplayPort TX core for use.<p>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>None. </dd></dl>
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<a class="anchor" name="44eafdd44ab545ce448b0c0476455d7c"></a><!-- doxytag: member="xdptx.h::XDptx_IsConnected" ref="44eafdd44ab545ce448b0c0476455d7c" args="(XDptx *InstancePtr)" -->
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<td class="memname">u32 XDptx_IsConnected </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_dptx.html">XDptx</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em> </td>
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This function checks if there is a connected RX device.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance.</td></tr>
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<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>TRUE if there is a connection.</li><li>FALSE if there is no connection. </li></ul>
</dd></dl>
</div>
</div><p>
<a class="anchor" name="32ba0cb6907ed3d2ecfdb31c699db3b4"></a><!-- doxytag: member="xdptx.h::XDptx_LookupConfig" ref="32ba0cb6907ed3d2ecfdb31c699db3b4" args="(u16 DeviceId)" -->
@ -3417,4 +3446,4 @@ This function will write a global unique identifier (GUID) to the target Display
This table contains the main stream attributes for various standard resolutions. Each entry is of the format: 1) XDPTX_VM_&lt;HRES&gt;x&lt;VRES&gt;_&lt;REFRESH (HZ)&gt;_P(_RB = Reduced Blanking) 2) Display Monitor Timing (DMT) ID 3) Horizontal resolution (pixels) 4) Vertical resolution (lines) 5) Pixel clock (KHz) 6) Interlaced (0=non-interlaced|1=interlaced) 7) Horizontal sync polarity (0=positive|1=negative) 8) Vertical sync polarity (0=positive|1=negative) 9) Horizontal front porch (pixels) 10) Horizontal sync time (pixels) 11) Horizontal back porch (pixels) 12) Vertical front porch (lines) 13) Vertical sync time (lines) 14) Vertical back porch (lines)
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -28,7 +28,7 @@ This header file contains the identifiers and low-level driver functions (or mac
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
als 08/03/14 Initial MST addition.
</pre>
<p>
@ -9661,4 +9661,4 @@ This is a low-level function that writes to the specified register.<p>
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -28,7 +28,7 @@ This file contains functions related to <a class="el" href="struct_x_dptx.html">
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
</pre>
<p>
<code>#include &quot;<a class="el" href="xdptx_8h.html">xdptx.h</a>&quot;</code><br>
@ -162,4 +162,4 @@ This function installs a callback function for when a hot-plug-detect pulse inte
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -26,7 +26,8 @@
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 08/03/14 Initial release.
1.0 als 08/03/14 Initial release.
2.0 als 09/21/14 Improvements to topology discovery and sideband messages.
</pre>
<p>
<code>#include &quot;string.h&quot;</code><br>
@ -44,7 +45,9 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___sideband_reply.html">XDptx_SidebandReply</a></td></tr>
<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#2ccc52eda76ccfd8c643dcdb7af55d53">XDPTX_MAX_TIMEOUT_COUNT</a>&nbsp;&nbsp;&nbsp;100</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#e85abccec81b5307fbf9a638320a7f62">XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT</a>&nbsp;&nbsp;&nbsp;5000</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#8d5d2071b1842667aa49efa4742360ee">XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT</a>&nbsp;&nbsp;&nbsp;30</td></tr>
<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#f15269f0f6d4a121d3f4258f5a51b298">XDptx_MstCfgModeEnable</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
@ -67,7 +70,9 @@
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#895b0d104c1772fe0f60c879cd0a2b82">XDptx_SetStreamSinkRad</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#d4d2ebaad714c817b647f8d21f879eca">XDptx_FindAccessibleDpDevices</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#e81134f5cfd2bd5ad5826048c7c2f2dd">XDptx_DiscoverTopology</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#03309887289769ac323f0b7e7b004dae">XDptx_FindAccessibleDpDevices</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)</td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__mst_8c.html#a688873fb1701355cbb33ac5d25d3da2">XDptx_AllocatePayloadStreams</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr)</td></tr>
@ -100,12 +105,27 @@
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<hr><h2>Define Documentation</h2>
<a class="anchor" name="2ccc52eda76ccfd8c643dcdb7af55d53"></a><!-- doxytag: member="xdptx_mst.c::XDPTX_MAX_TIMEOUT_COUNT" ref="2ccc52eda76ccfd8c643dcdb7af55d53" args="" -->
<a class="anchor" name="e85abccec81b5307fbf9a638320a7f62"></a><!-- doxytag: member="xdptx_mst.c::XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT" ref="e85abccec81b5307fbf9a638320a7f62" args="" -->
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<td class="memname">#define XDPTX_MAX_TIMEOUT_COUNT&nbsp;&nbsp;&nbsp;100 </td>
<td class="memname">#define XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT&nbsp;&nbsp;&nbsp;5000 </td>
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<a class="anchor" name="8d5d2071b1842667aa49efa4742360ee"></a><!-- doxytag: member="xdptx_mst.c::XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT" ref="8d5d2071b1842667aa49efa4742360ee" args="" -->
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<td class="memname">#define XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT&nbsp;&nbsp;&nbsp;30 </td>
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@ -259,12 +279,42 @@ This function will clear the virtual channel payload ID table in both the Displa
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<a class="anchor" name="d4d2ebaad714c817b647f8d21f879eca"></a><!-- doxytag: member="xdptx_mst.c::XDptx_FindAccessibleDpDevices" ref="d4d2ebaad714c817b647f8d21f879eca" args="(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)" -->
<a class="anchor" name="e81134f5cfd2bd5ad5826048c7c2f2dd"></a><!-- doxytag: member="xdptx_mst.c::XDptx_DiscoverTopology" ref="e81134f5cfd2bd5ad5826048c7c2f2dd" args="(XDptx *InstancePtr)" -->
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<td class="memname">void XDptx_FindAccessibleDpDevices </td>
<td class="memname">u32 XDptx_DiscoverTopology </td>
<td>(</td>
<td class="paramtype"><a class="el" href="struct_x_dptx.html">XDptx</a> *&nbsp;</td>
<td class="paramname"> <em>InstancePtr</em> </td>
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This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance.</td></tr>
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<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the topology discovery is successful.</li><li>XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.</li></ul>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>The contents of the InstancePtr-&gt;Topology structure will be modified. </dd></dl>
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<a class="anchor" name="03309887289769ac323f0b7e7b004dae"></a><!-- doxytag: member="xdptx_mst.c::XDptx_FindAccessibleDpDevices" ref="03309887289769ac323f0b7e7b004dae" args="(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)" -->
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<td class="memname">u32 XDptx_FindAccessibleDpDevices </td>
<td>(</td>
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<td class="paramname"> <em>InstancePtr</em>, </td>
@ -291,7 +341,7 @@ This function will clear the virtual channel payload ID table in both the Displa
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<p>
This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.<p>
<dl compact><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>InstancePtr</em>&nbsp;</td><td>is a pointer to the <a class="el" href="struct_x_dptx.html">XDptx</a> instance. </td></tr>
@ -299,7 +349,9 @@ This function will explore the DisplayPort topology of downstream devices connec
<tr><td valign="top"></td><td valign="top"><em>RelativeAddress</em>&nbsp;</td><td>is the relative address from the DisplayPort source to the current target DisplayPort device in the recursion.</td></tr>
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<dl compact><dt><b>Returns:</b></dt><dd>None - the recursion will exit from nodes that have an error when replying to the LINK_ADDRESS sideband message.</dd></dl>
<dl compact><dt><b>Returns:</b></dt><dd><ul>
<li>XST_SUCCESS if the topology discovery is successful.</li><li>XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.</li></ul>
</dd></dl>
<dl compact><dt><b>Note:</b></dt><dd>The contents of the InstancePtr-&gt;Topology structure will be modified. </dd></dl>
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@ -1318,4 +1370,4 @@ This function will write a global unique identifier (GUID) to the target Display
</pre></div>This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDptx_FindAccessibleDpDevices function.
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -28,7 +28,7 @@ This file contains a diagnostic self-test function for the <a class="el" href="s
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
</pre>
<p>
<code>#include &quot;<a class="el" href="xdptx_8h.html">xdptx.h</a>&quot;</code><br>
@ -129,4 +129,4 @@ This table contains the default values for the DisplayPort TX core's general usa
</pre></div>This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

4
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@ -28,7 +28,7 @@ This file contains static initialization methods for the <a class="el" href="str
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
</pre>
<p>
<code>#include &quot;<a class="el" href="xdptx_8h.html">xdptx.h</a>&quot;</code><br>
@ -87,4 +87,4 @@ This function looks for the device configuration based on the unique device ID.
A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

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@ -28,7 +28,7 @@ This file contains the stream policy maker functions for the <a class="el" href=
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
als 08/03/14 Initial MST addition.
</pre>
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@ -446,4 +446,4 @@ This function clears the main stream attributes registers of the DisplayPort TX
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

4
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@ -28,7 +28,7 @@ Contains display monitor timing (DMT) modes for various standard resolutions.<p>
MODIFICATION HISTORY:</pre><p>
<pre> Ver Who Date Changes
----- ---- -------- -----------------------------------------------
1.00a als 05/17/14 Initial release.
1.0 als 05/17/14 Initial release.
</pre>
<p>
<code>#include &quot;xil_types.h&quot;</code><br>
@ -55,4 +55,4 @@ Contains display monitor timing (DMT) modes for various standard resolutions.<p>
This table contains the main stream attributes for various standard resolutions. Each entry is of the format: 1) XDPTX_VM_&lt;HRES&gt;x&lt;VRES&gt;_&lt;REFRESH (HZ)&gt;_P(_RB = Reduced Blanking) 2) Display Monitor Timing (DMT) ID 3) Horizontal resolution (pixels) 4) Vertical resolution (lines) 5) Pixel clock (KHz) 6) Interlaced (0=non-interlaced|1=interlaced) 7) Horizontal sync polarity (0=positive|1=negative) 8) Vertical sync polarity (0=positive|1=negative) 9) Horizontal front porch (pixels) 10) Horizontal sync time (pixels) 11) Horizontal back porch (pixels) 12) Vertical front porch (lines) 13) Vertical sync time (lines) 14) Vertical back porch (lines)
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.