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PMUFW: Headers: Remove unused register definitions from PMU Local

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Some registers in PMU Local register set are not intended to be
published out. So removing all register definitions which are not
used by PMU FW currently.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This commit is contained in:
Jyotheeswar Reddy 2015-08-06 11:02:29 -07:00 • committed by Nava kishore Manne
parent 07377abe62
commit 4ae20ca9bf
2 changed files with 1 additions and 363 deletions
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362
lib/sw_apps/zynqmp_pmufw/src/pmu_local.h
View file

@ -618,27 +618,6 @@ extern "C" {
#define PMU_LOCAL_LOC_AUX_PWR_STATE_L2_WIDTH 1
#define PMU_LOCAL_LOC_AUX_PWR_STATE_L2_MASK ((u32)0X00000080U)
/**
* Register: PMU_LOCAL_LOCAL_RESET
*/
#define PMU_LOCAL_LOCAL_RESET ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000200U) )
#define PMU_LOCAL_LOCAL_RESET_CSU_RST_SHIFT 0
#define PMU_LOCAL_LOCAL_RESET_CSU_RST_WIDTH 1
#define PMU_LOCAL_LOCAL_RESET_CSU_RST_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_LOCAL_CNTRL
*/
#define PMU_LOCAL_LOCAL_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000204U) )
#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_SHIFT 1
#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_WIDTH 1
#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_MASK ((u32)0X00000002U)
#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_SHIFT 0
#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_WIDTH 1
#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_GPO1_READ
@ -858,140 +837,6 @@ extern "C" {
#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_WIDTH 32
#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_LOCAL_GEN_STORAGE0
*/
#define PMU_LOCAL_LOCAL_GEN_STORAGE0 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000300U) )
#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_SHIFT 0
#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_WIDTH 32
#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_LOCAL_GEN_STORAGE1
*/
#define PMU_LOCAL_LOCAL_GEN_STORAGE1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000304U) )
#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_SHIFT 0
#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_WIDTH 32
#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_LOCAL_GEN_STORAGE2
*/
#define PMU_LOCAL_LOCAL_GEN_STORAGE2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000308U) )
#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_SHIFT 0
#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_WIDTH 32
#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_LOCAL_GEN_STORAGE3
*/
#define PMU_LOCAL_LOCAL_GEN_STORAGE3 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000030CU) )
#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_SHIFT 0
#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_WIDTH 32
#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE0
*/
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000310U) )
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_SHIFT 0
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_WIDTH 32
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE1
*/
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000314U) )
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_SHIFT 0
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_WIDTH 32
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE2
*/
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000318U) )
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_SHIFT 0
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_WIDTH 32
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE3
*/
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000031CU) )
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_SHIFT 0
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_WIDTH 32
#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_ADDR_ERROR_STATUS
*/
#define PMU_LOCAL_ADDR_ERROR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000320U) )
#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_SHIFT 0
#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_WIDTH 1
#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_ADDR_ERROR_INT_MASK
*/
#define PMU_LOCAL_ADDR_ERROR_INT_MASK ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000324U) )
#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_SHIFT 0
#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_WIDTH 1
#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_ADDR_ERROR_INT_EN
*/
#define PMU_LOCAL_ADDR_ERROR_INT_EN ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000328U) )
#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_SHIFT 0
#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_WIDTH 1
#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_ADDR_ERROR_INT_DIS
*/
#define PMU_LOCAL_ADDR_ERROR_INT_DIS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000032CU) )
#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_SHIFT 0
#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_WIDTH 1
#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBISR_CNTRL
*/
#define PMU_LOCAL_MBISR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000330U) )
#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_SHIFT 5
#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_WIDTH 1
#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_MASK ((u32)0X00000020U)
#define PMU_LOCAL_MBISR_CNTRL_ENABLE_SHIFT 0
#define PMU_LOCAL_MBISR_CNTRL_ENABLE_WIDTH 1
#define PMU_LOCAL_MBISR_CNTRL_ENABLE_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBISR_STATUS
*/
#define PMU_LOCAL_MBISR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000334U) )
#define PMU_LOCAL_MBISR_STATUS_PASS_SHIFT 4
#define PMU_LOCAL_MBISR_STATUS_PASS_WIDTH 1
#define PMU_LOCAL_MBISR_STATUS_PASS_MASK ((u32)0X00000010U)
#define PMU_LOCAL_MBISR_STATUS_DONE_SHIFT 0
#define PMU_LOCAL_MBISR_STATUS_DONE_WIDTH 1
#define PMU_LOCAL_MBISR_STATUS_DONE_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_PMU_PB_ERR
*/
@ -1022,131 +867,6 @@ extern "C" {
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_WIDTH 20
#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_MASK ((u32)0X000FFFFFU)
/**
* Register: PMU_LOCAL_PWR_ACK_ERR_LPD
*/
#define PMU_LOCAL_PWR_ACK_ERR_LPD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000340U) )
#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_SHIFT 0
#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_WIDTH 32
#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_PWR_ACK_ERR_FPD
*/
#define PMU_LOCAL_PWR_ACK_ERR_FPD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000344U) )
#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_SHIFT 0
#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_WIDTH 32
#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_SERV_LOGCLR_ERR
*/
#define PMU_LOCAL_SERV_LOGCLR_ERR ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000348U) )
#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_SHIFT 0
#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_WIDTH 32
#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_LOGCLR_TRIG
*/
#define PMU_LOCAL_LOGCLR_TRIG ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000350U) )
#define PMU_LOCAL_LOGCLR_TRIG_FP_SHIFT 17
#define PMU_LOCAL_LOGCLR_TRIG_FP_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_FP_MASK ((u32)0X00020000U)
#define PMU_LOCAL_LOGCLR_TRIG_LP_SHIFT 16
#define PMU_LOCAL_LOGCLR_TRIG_LP_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_LP_MASK ((u32)0X00010000U)
#define PMU_LOCAL_LOGCLR_TRIG_USB1_SHIFT 13
#define PMU_LOCAL_LOGCLR_TRIG_USB1_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_USB1_MASK ((u32)0X00002000U)
#define PMU_LOCAL_LOGCLR_TRIG_USB0_SHIFT 12
#define PMU_LOCAL_LOGCLR_TRIG_USB0_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_USB0_MASK ((u32)0X00001000U)
#define PMU_LOCAL_LOGCLR_TRIG_RPU_SHIFT 10
#define PMU_LOCAL_LOGCLR_TRIG_RPU_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_RPU_MASK ((u32)0X00000400U)
#define PMU_LOCAL_LOGCLR_TRIG_PP1_SHIFT 7
#define PMU_LOCAL_LOGCLR_TRIG_PP1_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_PP1_MASK ((u32)0X00000080U)
#define PMU_LOCAL_LOGCLR_TRIG_PP0_SHIFT 6
#define PMU_LOCAL_LOGCLR_TRIG_PP0_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_PP0_MASK ((u32)0X00000040U)
#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_SHIFT 3
#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_MASK ((u32)0X00000008U)
#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_SHIFT 2
#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_MASK ((u32)0X00000004U)
#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_SHIFT 1
#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_MASK ((u32)0X00000002U)
#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_SHIFT 0
#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_WIDTH 1
#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_LOGCLR_ACK
*/
#define PMU_LOCAL_LOGCLR_ACK ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000354U) )
#define PMU_LOCAL_LOGCLR_ACK_FP_SHIFT 17
#define PMU_LOCAL_LOGCLR_ACK_FP_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_FP_MASK ((u32)0X00020000U)
#define PMU_LOCAL_LOGCLR_ACK_LP_SHIFT 16
#define PMU_LOCAL_LOGCLR_ACK_LP_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_LP_MASK ((u32)0X00010000U)
#define PMU_LOCAL_LOGCLR_ACK_USB1_SHIFT 13
#define PMU_LOCAL_LOGCLR_ACK_USB1_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_USB1_MASK ((u32)0X00002000U)
#define PMU_LOCAL_LOGCLR_ACK_USB0_SHIFT 12
#define PMU_LOCAL_LOGCLR_ACK_USB0_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_USB0_MASK ((u32)0X00001000U)
#define PMU_LOCAL_LOGCLR_ACK_RPU_SHIFT 10
#define PMU_LOCAL_LOGCLR_ACK_RPU_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_RPU_MASK ((u32)0X00000400U)
#define PMU_LOCAL_LOGCLR_ACK_PP1_SHIFT 7
#define PMU_LOCAL_LOGCLR_ACK_PP1_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_PP1_MASK ((u32)0X00000080U)
#define PMU_LOCAL_LOGCLR_ACK_PP0_SHIFT 6
#define PMU_LOCAL_LOGCLR_ACK_PP0_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_PP0_MASK ((u32)0X00000040U)
#define PMU_LOCAL_LOGCLR_ACK_ACPU3_SHIFT 3
#define PMU_LOCAL_LOGCLR_ACK_ACPU3_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_ACPU3_MASK ((u32)0X00000008U)
#define PMU_LOCAL_LOGCLR_ACK_ACPU2_SHIFT 2
#define PMU_LOCAL_LOGCLR_ACK_ACPU2_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_ACPU2_MASK ((u32)0X00000004U)
#define PMU_LOCAL_LOGCLR_ACK_ACPU1_SHIFT 1
#define PMU_LOCAL_LOGCLR_ACK_ACPU1_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_ACPU1_MASK ((u32)0X00000002U)
#define PMU_LOCAL_LOGCLR_ACK_ACPU0_SHIFT 0
#define PMU_LOCAL_LOGCLR_ACK_ACPU0_WIDTH 1
#define PMU_LOCAL_LOGCLR_ACK_ACPU0_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_APU_WFI_STATUS
*/
@ -1172,88 +892,6 @@ extern "C" {
#define PMU_LOCAL_APU_WFI_STATUS_ACPU0_WFI_WIDTH 1
#define PMU_LOCAL_APU_WFI_STATUS_ACPU0_WFI_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBIST_RST
*/
#define PMU_LOCAL_MBIST_RST ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000036CU) )
#define PMU_LOCAL_MBIST_RST_CSU_SHIFT 1
#define PMU_LOCAL_MBIST_RST_CSU_WIDTH 1
#define PMU_LOCAL_MBIST_RST_CSU_MASK ((u32)0X00000002U)
#define PMU_LOCAL_MBIST_RST_PMU_SHIFT 0
#define PMU_LOCAL_MBIST_RST_PMU_WIDTH 1
#define PMU_LOCAL_MBIST_RST_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBIST_PG_EN
*/
#define PMU_LOCAL_MBIST_PG_EN ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000370U) )
#define PMU_LOCAL_MBIST_PG_EN_CSU_SHIFT 1
#define PMU_LOCAL_MBIST_PG_EN_CSU_WIDTH 1
#define PMU_LOCAL_MBIST_PG_EN_CSU_MASK ((u32)0X00000002U)
#define PMU_LOCAL_MBIST_PG_EN_PMU_SHIFT 0
#define PMU_LOCAL_MBIST_PG_EN_PMU_WIDTH 1
#define PMU_LOCAL_MBIST_PG_EN_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBIST_SETUP
*/
#define PMU_LOCAL_MBIST_SETUP ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000374U) )
#define PMU_LOCAL_MBIST_SETUP_CSU_SHIFT 1
#define PMU_LOCAL_MBIST_SETUP_CSU_WIDTH 1
#define PMU_LOCAL_MBIST_SETUP_CSU_MASK ((u32)0X00000002U)
#define PMU_LOCAL_MBIST_SETUP_PMU_SHIFT 0
#define PMU_LOCAL_MBIST_SETUP_PMU_WIDTH 1
#define PMU_LOCAL_MBIST_SETUP_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBIST_DONE
*/
#define PMU_LOCAL_MBIST_DONE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000378U) )
#define PMU_LOCAL_MBIST_DONE_CSU_SHIFT 1
#define PMU_LOCAL_MBIST_DONE_CSU_WIDTH 1
#define PMU_LOCAL_MBIST_DONE_CSU_MASK ((u32)0X00000002U)
#define PMU_LOCAL_MBIST_DONE_PMU_SHIFT 0
#define PMU_LOCAL_MBIST_DONE_PMU_WIDTH 1
#define PMU_LOCAL_MBIST_DONE_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_MBIST_GOOD
*/
#define PMU_LOCAL_MBIST_GOOD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000037CU) )
#define PMU_LOCAL_MBIST_GOOD_CSU_SHIFT 1
#define PMU_LOCAL_MBIST_GOOD_CSU_WIDTH 1
#define PMU_LOCAL_MBIST_GOOD_CSU_MASK ((u32)0X00000002U)
#define PMU_LOCAL_MBIST_GOOD_PMU_SHIFT 0
#define PMU_LOCAL_MBIST_GOOD_PMU_WIDTH 1
#define PMU_LOCAL_MBIST_GOOD_PMU_MASK ((u32)0X00000001U)
/**
* Register: PMU_LOCAL_ECO_1
*/
#define PMU_LOCAL_ECO_1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000400U) )
#define PMU_LOCAL_ECO_1_REG_SHIFT 0
#define PMU_LOCAL_ECO_1_REG_WIDTH 32
#define PMU_LOCAL_ECO_1_REG_MASK ((u32)0XFFFFFFFFU)
/**
* Register: PMU_LOCAL_ECO_2
*/
#define PMU_LOCAL_ECO_2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000404U) )
#define PMU_LOCAL_ECO_2_REG_SHIFT 0
#define PMU_LOCAL_ECO_2_REG_WIDTH 32
#define PMU_LOCAL_ECO_2_REG_MASK ((u32)0XFFFFFFFFU)
#ifdef __cplusplus
}

2
lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h
View file

@ -1,4 +1,4 @@
#ifndef ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION "2015.3-rc1-16-gdffcba8f6d56"
#define ZYNQMP_XPFW_VERSION "2015.3-rc1-17-g29451ae9733a"
#endif