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qspipsu: Add driver for Alto Generic QSPI

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Add driver for Alto Generic QSPI.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-01-20 18:32:00 +05:30 • committed by Suneel Garapati
parent ce2a51897d
commit 4b2b01d3e5
11 changed files with 6067 additions and 0 deletions
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42
XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.mdd Executable file
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###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver qspipsu
OPTION supported_peripherals = (ps8_qspi pss_qspi psu_qspi);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = qspipsu;
END driver

53
XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.tcl Executable file
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###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.0 hk 08/21/14 First release
#
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
puts "In qspipsu tcl \n"
puts " Driver is $drv_handle \n"
xdefine_zynq_include_file $drv_handle "xparameters.h" "XQspiPsu" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
xdefine_zynq_config_file $drv_handle "xqspipsu_g.c" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
xdefine_zynq_canonical_xpars $drv_handle "xparameters.h" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
}

1654
XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_interrupt_example.c Executable file
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XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_polled_example.c Executable file
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40
XilinxProcessorIPLib/drivers/qspipsu/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner xqspipsu_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling qspipsu"
xqspipsu_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xqspipsu_includes
xqspipsu_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

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XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c Executable file
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255
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu.h
*
* This is the header file for the implementation of QSPIPSU driver.
* Generic QSPI interface allows for communication to any QSPI slave device.
* GQSPI contains a GENFIFO into which the bus transfers required are to be
* pushed with appropriate configuration. The controller provides TX and RX
* FIFO's and a DMA to be used for RX transfers. The controller executes each
* GENFIFO entry noting the configuration and places data on the bus as required
* The differen options in GENFIFO are as follows:
* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
* number of bytes in transfer.
* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
* EXPONENT : e when 2^e bytes are involved in transfer.
* SPI_MODE : SPI/Dual SPI/Quad SPI
* CS : Lower or Upper CS or Both
* Bus : Lower or Upper Bus or Both
* TX : When selected, controller transmits data in IMM or fetches number of
* bytes mentioned form TX FIFO. If not selected, dummies are pumped.
* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
* of requested number of bytes. If not selected, RX data is discarded.
* Stripe : Byte stripe over lower and upper bus or not.
* Poll : Polls response to match for to a set value (used along with POLL_CFG
* registers) and then proceeds to next GENFIFO entry.
* This feature is not currently used in the driver.
* GENFIFO has manual and auto start options.
* All DMA requests need a 4-byte aligned destination address buffer and
* size of transfer should also be a multiple of 4.
* This driver currently only supports DMA RX and no IO RX.
*
* Initialization:
* This driver uses the GQSPI controller with RX DMA. It supports both
* interrupt and polled transfers. Manual start of GENFIFO is used.
* XQspiPsu_CfgInitialize() initializes the instance variables.
* Additional setting can be done using SetOptions/ClearOptions functions
* and SelectSlave function.
*
* Transfer:
* Polled or Interrupt transfers can be done. The transfer function needs the
* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
* This is supposed to contain the byte count and any TX/RX buffers as required.
* Flags can be used indicate further information such as whether the message
* should be striped. The transfer functions form and write GENFIFO entries,
* check the status of the transfer and report back to the application
* when done.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
*
* </pre>
*
******************************************************************************/
#ifndef _XQSPIPSU_H_ /* prevent circular inclusions */
#define _XQSPIPSU_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xqspipsu_hw.h"
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* handle the asynchronous processing for the QSPIPSU device. The application
* using this driver is expected to define a handler of this type to support
* interrupt driven mode. The handler executes in an interrupt context, so
* only minimal processing should be performed.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent holds one or more status events that have occurred.
* See the XQspiPsu_SetStatusHandler() for details on the status
* events that can be passed in the callback.
* @param ByteCount indicates how many bytes of data were successfully
* transferred. This may be less than the number of bytes
* requested if the status event indicates an error.
*/
typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
/**
* This typedef contains configuration information for a flash message.
*/
typedef struct {
u8 *TxBfrPtr;
u8 *RxBfrPtr;
u32 ByteCount;
u32 BusWidth;
u32 Flags;
} XQspiPsu_Msg;
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
u8 BusWidth; /**< Bus width available on board */
} XQspiPsu_Config;
/**
* The XQspiPsu driver instance data. The user is required to allocate a
* variable of this type for every QSPIPSU device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XQspiPsu_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
u8 *GenFifoBufferPtr; /**< Gen FIFO entries */
int TxBytes; /**< Number of bytes to transfer (state) */
int RxBytes; /**< Number of bytes left to transfer(state) */
int GenFifoEntries; /**< Number of Gen FIFO entries remaining */
u32 IsBusy; /**< A transfer is in progress (state) */
u32 ReadMode; /**< DMA or IO mode */
u32 GenFifoCS;
u32 GenFifoBus;
int NumMsg;
int MsgCnt;
XQspiPsu_Msg *Msg;
XQspiPsu_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
} XQspiPsu;
/***************** Macros (Inline Functions) Definitions *********************/
#define XQSPIPSU_READMODE_DMA 0x0
#define XQSPIPSU_READMODE_IO 0x1
#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3
#define XQSPIPSU_SELECT_MODE_SPI 0x1
#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2
#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4
#define XQSPIPSU_GENFIFO_CS_SETUP 0x04
#define XQSPIPSU_GENFIFO_CS_HOLD 0x03
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2
#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4
#define XQSPIPSU_MANUAL_START_OPTION 0x8
#define XQSPIPSU_GENFIFO_EXP_START 0x100
#define XQSPIPSU_DMA_BYTES_MAX 0x10000000
#define XQSPIPSU_CLK_PRESCALE_2 0x00
#define XQSPIPSU_CLK_PRESCALE_4 0x01
#define XQSPIPSU_CLK_PRESCALE_8 0x02
#define XQSPIPSU_CLK_PRESCALE_16 0x03
#define XQSPIPSU_CLK_PRESCALE_32 0x04
#define XQSPIPSU_CLK_PRESCALE_64 0x05
#define XQSPIPSU_CLK_PRESCALE_128 0x06
#define XQSPIPSU_CLK_PRESCALE_256 0x07
#define XQSPIPSU_CR_PRESC_MAXIMUM 7
#define XQSPIPSU_CONNECTION_MODE_SINGLE 0
#define XQSPIPSU_CONNECTION_MODE_STACKED 1
#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2
/* Add more flags as required */
#define XQSPIPSU_MSG_FLAG_STRIPE 0x1
#define XQspiPsu_Select(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)
#define XQspiPsu_IsManualStart(InstancePtr) ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
/* Initialization and reset */
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
u32 EffectiveAddr);
void XQspiPsu_Reset(XQspiPsu *InstancePtr);
void XQspiPsu_Abort(XQspiPsu *InstancePtr);
/* Transfer functions and handlers */
int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
XQspiPsu_StatusHandler FuncPtr);
/* Configuration functions */
int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* _XQSPIPSU_H_ */

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XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_g.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_g.c
*
* This file contains a configuration table that specifies the configuration of
* QSPIPSU devices in the system.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xqspipsu.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Prototypes ******************************/
/**
* This table contains configuration information for each QSPIPSU device
* in the system.
*/
XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] = {
{
XPAR_XQSPIPSU_0_DEVICE_ID, /* Device ID for instance */
XPAR_XQSPIPSU_0_BASEADDR, /* Device base address */
XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
XPAR_XQSPIPSU_0_QSPI_MODE
},
};

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XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_hw.h
*
* This file contains low level access funcitons using the base address
* directly without an instance.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
*
* </pre>
*
******************************************************************************/
#ifndef _XQSPIPSU_HW_H_ /* prevent circular inclusions */
#define _XQSPIPSU_HW_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**
* QSPI Base Address
*/
#define XQSPIPS_BASEADDR 0XFF0F0000
/**
* GQSPI Base Address
*/
#define XQSPIPSU_BASEADDR 0xFF0F0100
#define XQSPIPSU_OFFSET 0x100
/**
* Register: XQSPIPS_EN_REG
*/
#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014 )
#define XQSPIPS_EN_SHIFT 0
#define XQSPIPS_EN_WIDTH 1
#define XQSPIPS_EN_MASK 0X00000001
/**
* Register: XQSPIPSU_CFG
*/
#define XQSPIPSU_CFG_OFFSET 0X00000000
#define XQSPIPSU_CFG_MODE_EN_SHIFT 30
#define XQSPIPSU_CFG_MODE_EN_WIDTH 2
#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000
#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000
#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28
#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000
#define XQSPIPSU_CFG_ENDIAN_SHIFT 26
#define XQSPIPSU_CFG_ENDIAN_WIDTH 1
#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000
#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20
#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1
#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000
#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19
#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1
#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000
#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038
#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2
#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1
#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004
#define XQSPIPSU_CFG_CLK_POL_SHIFT 1
#define XQSPIPSU_CFG_CLK_POL_WIDTH 1
#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002
/**
* Register: XQSPIPSU_ISR
*/
#define XQSPIPSU_ISR_OFFSET 0X00000004
#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11
#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8
#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_ISR_RXFULL_SHIFT 5
#define XQSPIPSU_ISR_RXFULL_WIDTH 1
#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020
#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_ISR_TXFULL_SHIFT 3
#define XQSPIPSU_ISR_TXFULL_WIDTH 1
#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008
#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002
/**
* Register: XQSPIPSU_IER
*/
#define XQSPIPSU_IER_OFFSET 0X00000008
#define XQSPIPSU_IER_RXEMPTY_SHIFT 11
#define XQSPIPSU_IER_RXEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IER_TXEMPTY_SHIFT 8
#define XQSPIPSU_IER_TXEMPTY_WIDTH 1
#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IER_RXFULL_SHIFT 5
#define XQSPIPSU_IER_RXFULL_WIDTH 1
#define XQSPIPSU_IER_RXFULL_MASK 0X00000020
#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IER_TXFULL_SHIFT 3
#define XQSPIPSU_IER_TXFULL_WIDTH 1
#define XQSPIPSU_IER_TXFULL_MASK 0X00000008
#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002
/**
* Register: XQSPIPSU_IDR
*/
#define XQSPIPSU_IDR_OFFSET 0X0000000C
#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IDR_RXFULL_SHIFT 5
#define XQSPIPSU_IDR_RXFULL_WIDTH 1
#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IDR_TXFULL_SHIFT 3
#define XQSPIPSU_IDR_TXFULL_WIDTH 1
#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_IDR_ALL_MASK 0X0FBE
/**
* Register: XQSPIPSU_IMR
*/
#define XQSPIPSU_IMR_OFFSET 0X00000010
#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IMR_RXFULL_SHIFT 5
#define XQSPIPSU_IMR_RXFULL_WIDTH 1
#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IMR_TXFULL_SHIFT 3
#define XQSPIPSU_IMR_TXFULL_WIDTH 1
#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002
/**
* Register: XQSPIPSU_EN_REG
*/
#define XQSPIPSU_EN_OFFSET 0X00000014
#define XQSPIPSU_EN_SHIFT 0
#define XQSPIPSU_EN_WIDTH 1
#define XQSPIPSU_EN_MASK 0X00000001
/**
* Register: XQSPIPSU_TXD
*/
#define XQSPIPSU_TXD_OFFSET 0X0000001C
#define XQSPIPSU_TXD_SHIFT 0
#define XQSPIPSU_TXD_WIDTH 32
#define XQSPIPSU_TXD_MASK 0XFFFFFFFF
#define XQSPIPSU_TXD_DEPTH 32
/**
* Register: XQSPIPSU_RXD
*/
#define XQSPIPSU_RXD_OFFSET 0X00000020
#define XQSPIPSU_RXD_SHIFT 0
#define XQSPIPSU_RXD_WIDTH 32
#define XQSPIPSU_RXD_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_TX_THRESHOLD
*/
#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028
#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01
/**
* Register: XQSPIPSU_RX_THRESHOLD
*/
#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002C
#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01
#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32
/**
* Register: XQSPIPSU_GPIO
*/
#define XQSPIPSU_GPIO_OFFSET 0X00000030
#define XQSPIPSU_GPIO_WP_N_SHIFT 0
#define XQSPIPSU_GPIO_WP_N_WIDTH 1
#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001
/**
* Register: XQSPIPSU_LPBK_DLY_ADJ
*/
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007
/**
* Register: XQSPIPSU_GEN_FIFO
*/
#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040
#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0
#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20
#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFF
/**
* Register: XQSPIPSU_SEL
*/
#define XQSPIPSU_SEL_OFFSET 0X00000044
#define XQSPIPSU_SEL_SHIFT 0
#define XQSPIPSU_SEL_WIDTH 1
#define XQSPIPSU_SEL_MASK 0X00000001
/**
* Register: XQSPIPSU_FIFO_CTRL
*/
#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004C
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001
/**
* Register: XQSPIPSU_GF_THRESHOLD
*/
#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050
#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5
#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
/**
* Register: XQSPIPSU_POLL_CFG
*/
#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000
#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8
#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8
#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00
#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0
#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8
#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FF
/**
* Register: XQSPIPSU_P_TIMEOUT
*/
#define XQSPIPSU_P_TO_OFFSET 0X00000058
#define XQSPIPSU_P_TO_VALUE_SHIFT 0
#define XQSPIPSU_P_TO_VALUE_WIDTH 32
#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_XFER_STS
*/
#define XQSPIPSU_XFER_STS_OFFSET 0X0000005C
#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0
#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32
#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_GF_SNAPSHOT
*/
#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060
#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0
#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20
#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFF
/**
* Register: XQSPIPSU_RX_COPY
*/
#define XQSPIPSU_RX_COPY_OFFSET 0X00000064
#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8
#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8
#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00
#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0
#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8
#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FF
/**
* Register: XQSPIPSU_MOD_ID
*/
#define XQSPIPSU_MOD_ID_OFFSET 0X000000FC
#define XQSPIPSU_MOD_ID_SHIFT 0
#define XQSPIPSU_MOD_ID_WIDTH 32
#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700
#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30
#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFC
/**
* Register: XQSPIPSU_QSPIDMA_DST_SIZE
*/
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704
#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27
#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFC
/**
* Register: XQSPIPSU_QSPIDMA_DST_STS
*/
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001E
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070C
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FC
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_STS
*/
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_EN
*/
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_DIS
*/
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071C
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_IMR
*/
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL2
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFF
/**
* Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
*/
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFC
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFF
/*
* Generic FIFO masks
*/
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFF
#define XQSPIPSU_GENFIFO_DATA_XFER 0x100
#define XQSPIPSU_GENFIFO_EXP 0x200
#define XQSPIPSU_GENFIFO_MODE_SPI 0x400
#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800
#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00
#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000
#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000
#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000
#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000
#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000 /* inverse is no bus */
#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_TX 0x10000 /* inverse is zero pump */
#define XQSPIPSU_GENFIFO_RX 0x20000 /* inverse is RX discard */
#define XQSPIPSU_GENFIFO_STRIPE 0x40000
#define XQSPIPSU_GENFIFO_POLL 0x80000
/***************** Macros (Inline Functions) Definitions *********************/
#define XQspiPsu_In32 Xil_In32
#define XQspiPsu_Out32 Xil_Out32
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
#ifdef __cplusplus
}
#endif
#endif /* _XQSPIPSU_H_ */

363
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_options.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_options.c
*
* This file implements funcitons to configure the QSPIPSU component,
* specifically some optional settings, clock and flash related information.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xqspipsu.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*
* Create the table of options which are processed to get/set the device
* options. These options are table driven to allow easy maintenance and
* expansion of the options.
*/
typedef struct {
u32 Option;
u32 Mask;
} OptionsMap;
static OptionsMap OptionsTable[] = {
{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
};
#define XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
/*****************************************************************************/
/**
*
* This function sets the options for the QSPIPSU device driver.The options
* control how the device behaves relative to the QSPIPSU bus. The device must be
* idle rather than busy transferring data before setting these device options.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Options contains the specified options to be set. This is a bit
* mask where a 1 indicates the option should be turned ON and
* a 0 indicates no action. One or more bit values may be
* contained in the mask. See the bit definitions named
* XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
*
* @return
* - XST_SUCCESS if options are successfully set.
* - XST_DEVICE_BUSY if the device is currently transferring data.
* The transfer must complete or be aborted before setting options.
*
* @note
* This function is not thread-safe.
*
******************************************************************************/
int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
{
u32 ConfigReg;
unsigned int Index;
u32 QspiPsuOptions;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) {
/* Turn it on */
ConfigReg |= OptionsTable[Index].Mask;
}
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function resets the options for the QSPIPSU device driver.The options
* control how the device behaves relative to the QSPIPSU bus. The device must be
* idle rather than busy transferring data before setting these device options.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Options contains the specified options to be set. This is a bit
* mask where a 1 indicates the option should be turned OFF and
* a 0 indicates no action. One or more bit values may be
* contained in the mask. See the bit definitions named
* XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
*
* @return
* - XST_SUCCESS if options are successfully set.
* - XST_DEVICE_BUSY if the device is currently transferring data.
* The transfer must complete or be aborted before setting options.
*
* @note
* This function is not thread-safe.
*
******************************************************************************/
int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
{
u32 ConfigReg;
unsigned int Index;
u32 QspiPsuOptions;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) {
/* Turn it off */
ConfigReg &= ~OptionsTable[Index].Mask;
}
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function gets the options for the QSPIPSU device. The options control how
* the device behaves relative to the QSPIPSU bus.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
*
* @return
*
* Options contains the specified options currently set. This is a bit value
* where a 1 means the option is on, and a 0 means the option is off.
* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
*
* @note None.
*
******************************************************************************/
u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
{
u32 OptionsFlag = 0;
u32 ConfigReg;
unsigned int Index;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Get the current options from QSPIPSU configuration register.
*/
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/*
* Loop through the options table to grab options
*/
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (ConfigReg & OptionsTable[Index].Mask) {
OptionsFlag |= OptionsTable[Index].Option;
}
}
return OptionsFlag;
}
/*****************************************************************************/
/**
*
* Configures the clock according to the prescaler passed.
*
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Prescaler - clock prescaler to be set.
*
* @return
* - XST_SUCCESS if successful.
* - XST_DEVICE_IS_STARTED if the device is already started.
* It must be stopped to re-initialize.
*
* @note None.
*
******************************************************************************/
int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
{
u32 ConfigReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
/*
* Do not allow the slave select to change while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
/*
* Read the configuration register, mask out the relevant bits, and set
* them with the shifted value passed into the function. Write the
* results back to the configuration register.
*/
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg &= ~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
ConfigReg |= (u32) (Prescaler & XQSPIPSU_CR_PRESC_MAXIMUM) <<
XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This funciton should be used to tell the QSPIPSU driver the HW flash
* configuration being used. This API should be called atleast once in the
* application. If desired, it can be called multiple times when switching
* between communicating to different flahs devices/using different configs.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Prescaler - clock prescaler to be set.
*
* @return
* - XST_SUCCESS if successful.
* - XST_DEVICE_IS_STARTED if the device is already started.
* It must be stopped to re-initialize.
*
* @note If this funciton is not called atleast once in the application,
* the driver assumes there is a single flash connected to the
* lower bus and CS line.
*
******************************************************************************/
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
{
Xil_AssertVoid(InstancePtr != NULL);
/*
* Bus and CS lines selected here will be updated in the instance and
* used for subsequent GENFIFO entries during transfer.
*/
/* Choose slave select line */
switch(FlashCS) {
case XQSPIPSU_SELECT_FLASH_CS_BOTH:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER |
XQSPIPSU_GENFIFO_CS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_CS_UPPER:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_CS_LOWER:
default:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
}
/* Choose bus */
switch(FlashBus) {
case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER |
XQSPIPSU_GENFIFO_BUS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
default:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
}
}

97
XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_sinit.c Executable file
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@ -0,0 +1,97 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_sinit.c
*
* The implementation of the XQspiPsu component's static initialization
* functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xqspipsu.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XQspiPsu_Config XQspiPsu_ConfigTable[];
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to look up the
* configuration for.
*
* @return
*
* A pointer to the configuration found or NULL if the specified device ID was
* not found. See xqspipsu.h for the definition of XQspiPsu_Config.
*
* @note None.
*
******************************************************************************/
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
{
XQspiPsu_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XQspiPsu_ConfigTable[Index];
break;
}
}
return CfgPtr;
}