stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

BSP: A53: clean up xparamters_ps.h

Browse source 
This patch removes the non-required definitions of XPS_*_BASEADDR in xparameters_ps.h

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-01-09 15:00:43 +05:30 • committed by Nava kishore Manne
parent 35c11ded6a
commit 4ff34113d2
1 changed files with 2 additions and 78 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

80
lib/bsp/standalone/src/cortexa53/xparameters_ps.h
View file

@ -118,22 +118,6 @@ extern "C" {
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
@ -141,17 +125,6 @@ extern "C" {
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
@ -160,59 +133,10 @@ extern "C" {
* within the hardblock. These have been put for backwards compatibilty
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xFF000000U
#define XPS_UART1_BASEADDR 0xFF010000U
#define XPS_I2C0_BASEADDR 0xFF020000U
#define XPS_I2C1_BASEADDR 0xFF030000U
#define XPS_SPI0_BASEADDR 0xFF040000U
#define XPS_SPI1_BASEADDR 0xFF050000U
#define XPS_CAN0_BASEADDR 0xFF060000U
#define XPS_CAN1_BASEADDR 0xFF070000U
#define XPS_GPIO_BASEADDR 0xFF0A0000U
#define XPS_GEM0_BASEADDR 0xFF0B0000U
#define XPS_GEM1_BASEADDR 0xFF0C0000U
#define XPS_GEM2_BASEADDR 0xFF0D0000U
#define XPS_GEM3_BASEADDR 0xFF0E0000U
#define XPS_QSPI_BASEADDR 0xFF0F0000U
#define XPS_NAND_BASEADDR 0xFF100000U
#define XPS_TTC0_BASEADDR 0xFF110000U
#define XPS_TTC1_BASEADDR 0xFF120000U
#define XPS_TTC2_BASEADDR 0xFF130000U
#define XPS_TTC3_BASEADDR 0xFF140000U
#define XPS_WDT_BASEADDR 0xFF150000U
#define XPS_SDIO0_BASEADDR 0xFF160000U
#define XPS_SDIO1_BASEADDR 0xFF170000U
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
/*#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000U */
#define XPS_PARPORT_CRTL_BASEADDR 0x0000000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xF0000000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xFE507000U
#define XPS_DMAC0_SEC_BASEADDR 0xFE5F0000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
#define XPS_L2CC_BASEADDR 0xFD3FD000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
/* Shared Peripheral Interrupts (SPI) */