bsp: a9: added support for openamp slave application in BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel
Nava kishore Manne
parent
20f9a33b64
commit
516c7af2cb
8 changed files with 63 additions and 11 deletions
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@ -238,4 +238,12 @@
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* 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
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* to update ECC_FLAGS to fix a bug introduced during new version creation
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* of BSP.
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* 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
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* functionalities are avoided for the OpenAMP slave application(when
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* USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
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* cache for its operation. Also file operations such as read, write,
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* close, open are also avoided for OpenAMP support(when USE_AMP flag is
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* defined for BSP) because XilOpenAMP library contains own file operation.
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* The xil-crt0.S file is modified for not initializing global timer for
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* OpenAMP application as it might be already in use by master CPU
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*****************************************************************************************/
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@ -29,7 +29,7 @@
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#ifndef USE_AMP
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#include <errno.h>
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#include "xil_types.h"
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@ -51,3 +51,4 @@ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
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errno = EIO;
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return (-1);
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}
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#endif
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@ -29,6 +29,7 @@
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#ifndef USE_AMP
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#include "xil_types.h"
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#ifdef __cplusplus
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extern "C" {
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@ -45,3 +46,4 @@ __attribute__((weak)) s32 _close(s32 fd)
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(void)fd;
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return (0);
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}
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#endif
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@ -29,7 +29,7 @@
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#ifndef USE_AMP
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#include <errno.h>
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#include "xil_types.h"
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@ -50,3 +50,4 @@ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
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errno = EIO;
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return (-1);
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}
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#endif
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@ -32,7 +32,7 @@
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/* read.c -- read bytes from a input device.
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*/
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#ifndef USE_AMP
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#include "xil_printf.h"
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#include "xparameters.h"
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@ -109,3 +109,4 @@ _read (s32 fd, char8* buf, s32 nbytes)
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return 0;
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#endif
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}
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#endif
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@ -32,7 +32,7 @@
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/* write.c -- write bytes to an output device.
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*/
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#ifndef USE_AMP
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#include "xil_printf.h"
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#include "xparameters.h"
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@ -109,3 +109,4 @@ _write (sint32 fd, char8* buf, sint32 nbytes)
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return 0;
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#endif
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}
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#endif
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@ -46,6 +46,8 @@
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* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
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* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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* initialization of uart smc nor and sram
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* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
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* timer when USE_AMP flag is defined
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* </pre>
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*
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* @note
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@ -110,7 +112,10 @@ _start:
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/* Reset and start Global Timer */
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mov r0, #0x0
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mov r1, #0x0
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bl XTime_SetTime
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#if USE_AMP != 1
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bl XTime_SetTime
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#endif
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#ifdef PROFILING /* defined in Makefile */
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/* Setup profiling stuff */
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@ -89,6 +89,9 @@
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* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
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* and Xil_L2CacheInvalidate APIs are modified to flush the complete
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* stack instead of just System Stack
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* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
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* application(when USE_AMP flag is defined for BSP) as master CPU
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* would be utilizing L2 cache for its operation
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*
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* </pre>
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*
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@ -117,6 +120,7 @@
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extern s32 __undef_stack;
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#endif
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#ifndef USE_AMP
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/****************************************************************************
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*
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* Access L2 Debug Control Register.
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@ -164,7 +168,7 @@ static void Xil_L2CacheSync(void)
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Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
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#endif
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}
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#endif
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/****************************************************************************
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*
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* Enable the Data cache.
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@ -179,7 +183,9 @@ static void Xil_L2CacheSync(void)
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void Xil_DCacheEnable(void)
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{
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Xil_L1DCacheEnable();
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#ifndef USE_AMP
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Xil_L2CacheEnable();
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#endif
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}
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/****************************************************************************
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@ -195,7 +201,9 @@ void Xil_DCacheEnable(void)
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****************************************************************************/
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void Xil_DCacheDisable(void)
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{
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#ifndef USE_AMP
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Xil_L2CacheDisable();
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#endif
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Xil_L1DCacheDisable();
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}
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@ -216,8 +224,9 @@ void Xil_DCacheInvalidate(void)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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#ifndef USE_AMP
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Xil_L2CacheInvalidate();
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#endif
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Xil_L1DCacheInvalidate();
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mtcpsr(currmask);
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@ -244,8 +253,9 @@ void Xil_DCacheInvalidateLine(u32 adr)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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#ifndef USE_AMP
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Xil_L2CacheInvalidateLine(adr);
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#endif
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Xil_L1DCacheInvalidateLine(adr);
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mtcpsr(currmask);
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@ -335,30 +345,36 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
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tempadr &= (~(cacheline - 1U));
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Xil_L1DCacheFlushLine(tempadr);
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#ifndef USE_AMP
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/* Disable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x3U);
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Xil_L2CacheFlushLine(tempadr);
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/* Enable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x0U);
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Xil_L2CacheSync();
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#endif
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tempadr += cacheline;
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}
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if ((tempend & (cacheline-1U)) != 0U) {
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tempend &= (~(cacheline - 1U));
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Xil_L1DCacheFlushLine(tempend);
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#ifndef USE_AMP
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/* Disable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x3U);
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Xil_L2CacheFlushLine(tempend);
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/* Enable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x0U);
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Xil_L2CacheSync();
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#endif
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}
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while (tempadr < tempend) {
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#ifndef USE_AMP
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/* Invalidate L2 cache line */
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*L2CCOffset = tempadr;
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Xil_L2CacheSync();
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#endif
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#ifdef __GNUC__
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/* Invalidate L1 Data cache line */
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__asm__ __volatile__("mcr " \
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@ -397,8 +413,9 @@ void Xil_DCacheFlush(void)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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Xil_L1DCacheFlush();
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#ifndef USE_AMP
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Xil_L2CacheFlush();
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#endif
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mtcpsr(currmask);
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}
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@ -424,7 +441,7 @@ void Xil_DCacheFlushLine(u32 adr)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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Xil_L1DCacheFlushLine(adr);
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#ifndef USE_AMP
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/* Disable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x3U);
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@ -433,6 +450,7 @@ void Xil_DCacheFlushLine(u32 adr)
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/* Enable Write-back and line fills */
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Xil_L2WriteDebugCtrl(0x0U);
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Xil_L2CacheSync();
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#endif
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mtcpsr(currmask);
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}
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@ -483,9 +501,11 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
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__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
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Reg = LocalAddr; }
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#endif
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#ifndef USE_AMP
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/* Flush L2 cache line */
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*L2CCOffset = LocalAddr;
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Xil_L2CacheSync();
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#endif
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LocalAddr += cacheline;
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}
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}
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@ -515,7 +535,9 @@ void Xil_DCacheStoreLine(u32 adr)
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mtcpsr(currmask | IRQ_FIQ_MASK);
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Xil_L1DCacheStoreLine(adr);
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#ifndef USE_AMP
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Xil_L2CacheStoreLine(adr);
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#endif
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mtcpsr(currmask);
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}
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@ -533,7 +555,9 @@ void Xil_DCacheStoreLine(u32 adr)
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void Xil_ICacheEnable(void)
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{
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Xil_L1ICacheEnable();
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#ifndef USE_AMP
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Xil_L2CacheEnable();
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#endif
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}
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/****************************************************************************
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@ -549,7 +573,9 @@ void Xil_ICacheEnable(void)
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****************************************************************************/
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void Xil_ICacheDisable(void)
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{
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#ifndef USE_AMP
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Xil_L2CacheDisable();
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#endif
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Xil_L1ICacheDisable();
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}
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@ -570,8 +596,9 @@ void Xil_ICacheInvalidate(void)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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#ifndef USE_AMP
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Xil_L2CacheInvalidate();
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#endif
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Xil_L1ICacheInvalidate();
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mtcpsr(currmask);
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@ -596,7 +623,9 @@ void Xil_ICacheInvalidateLine(u32 adr)
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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#ifndef USE_AMP
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Xil_L2CacheInvalidateLine(adr);
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#endif
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Xil_L1ICacheInvalidateLine(adr);
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mtcpsr(currmask);
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}
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@ -640,9 +669,11 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
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while (LocalAddr < end) {
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#ifndef USE_AMP
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/* Invalidate L2 cache line */
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*L2CCOffset = LocalAddr;
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dsb();
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#endif
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#ifdef __GNUC__
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/* Invalidate L1 I-cache line */
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__asm__ __volatile__("mcr " \
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@ -1265,6 +1296,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
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mtcpsr(currmask);
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}
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#ifndef USE_AMP
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/****************************************************************************
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*
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* Enable the L2 cache.
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@ -1609,3 +1641,4 @@ void Xil_L2CacheStoreLine(u32 adr)
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/* synchronize the processor */
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dsb();
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}
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#endif
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