bsp: a9: added support for openamp slave application in BSP

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>

lib/bsp/standalone/src/changelog.txt

@@ -238,4 +238,12 @@
  * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
  *		       to update ECC_FLAGS to fix a bug introduced during new version creation
  *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
  *****************************************************************************************/

lib/bsp/standalone/src/cortexa9/gcc/_open.c

@@ -29,7 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
-
+#ifndef USE_AMP
 #include <errno.h>
 #include "xil_types.h"
 
@@ -51,3 +51,4 @@ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
   errno = EIO;
   return (-1);
 }
+#endif

lib/bsp/standalone/src/cortexa9/gcc/close.c

@@ -29,6 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
+#ifndef USE_AMP
 #include "xil_types.h"
 #ifdef __cplusplus
 extern "C" {
@@ -45,3 +46,4 @@ __attribute__((weak)) s32 _close(s32 fd)
   (void)fd;
   return (0);
 }
+#endif

lib/bsp/standalone/src/cortexa9/gcc/open.c

@@ -29,7 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
-
+#ifndef USE_AMP
 #include <errno.h>
 #include "xil_types.h"
 
@@ -50,3 +50,4 @@ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
   errno = EIO;
   return (-1);
 }
+#endif

lib/bsp/standalone/src/cortexa9/gcc/read.c

@@ -32,7 +32,7 @@
 
 /* read.c -- read bytes from a input device.
  */
-
+#ifndef USE_AMP
 #include "xil_printf.h"
 #include "xparameters.h"
 
@@ -109,3 +109,4 @@ _read (s32 fd, char8* buf, s32 nbytes)
   return 0;
 #endif
 }
+#endif

lib/bsp/standalone/src/cortexa9/gcc/write.c

@@ -32,7 +32,7 @@
 
 /* write.c -- write bytes to an output device.
  */
-
+#ifndef USE_AMP
 #include "xil_printf.h"
 #include "xparameters.h"
 
@@ -109,3 +109,4 @@ _write (sint32 fd, char8* buf, sint32 nbytes)
   return 0;
 #endif
 }
+#endif

lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S

@@ -46,6 +46,8 @@
 * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
 * 4.2	pkp  08/04/14 Removed PEEP board related code which contained
 *		      initialization of uart smc nor and sram
+* 5.3	pkp  10/07/15 Added support for OpenAMP by not initializing global
+*		      timer when USE_AMP flag is defined
 * </pre>
 *
 * @note
@@ -110,7 +112,10 @@ _start:
     /* Reset and start Global Timer */
 	mov	r0, #0x0
 	mov	r1, #0x0
+
+#if USE_AMP != 1
 	bl XTime_SetTime
+#endif
 
 #ifdef PROFILING			/* defined in Makefile */
 	/* Setup profiling stuff */

lib/bsp/standalone/src/cortexa9/xil_cache.c

@@ -89,6 +89,9 @@
 *					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
 *					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
 *					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
 *
 * </pre>
 *
@@ -117,6 +120,7 @@
 	extern s32  __undef_stack;
 #endif
 
+#ifndef USE_AMP
 /****************************************************************************
 *
 * Access L2 Debug Control Register.
@@ -164,7 +168,7 @@ static void Xil_L2CacheSync(void)
 	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
 #endif
 }
-
+#endif
 /****************************************************************************
 *
 * Enable the Data cache.
@@ -179,7 +183,9 @@ static void Xil_L2CacheSync(void)
 void Xil_DCacheEnable(void)
 {
 	Xil_L1DCacheEnable();
+#ifndef USE_AMP
 	Xil_L2CacheEnable();
+#endif
 }
 
 /****************************************************************************
@@ -195,7 +201,9 @@ void Xil_DCacheEnable(void)
 ****************************************************************************/
 void Xil_DCacheDisable(void)
 {
+#ifndef USE_AMP
 	Xil_L2CacheDisable();
+#endif
 	Xil_L1DCacheDisable();
 }
 
@@ -216,8 +224,9 @@ void Xil_DCacheInvalidate(void)
 
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
-
+#ifndef USE_AMP
 	Xil_L2CacheInvalidate();
+#endif
 	Xil_L1DCacheInvalidate();
 
 	mtcpsr(currmask);
@@ -244,8 +253,9 @@ void Xil_DCacheInvalidateLine(u32 adr)
 
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
-
+#ifndef USE_AMP
 	Xil_L2CacheInvalidateLine(adr);
+#endif
 	Xil_L1DCacheInvalidateLine(adr);
 
 	mtcpsr(currmask);
@@ -335,30 +345,36 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
 			tempadr &= (~(cacheline - 1U));
 
 			Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
 			/* Disable Write-back and line fills */
 			Xil_L2WriteDebugCtrl(0x3U);
 			Xil_L2CacheFlushLine(tempadr);
 			/* Enable Write-back and line fills */
 			Xil_L2WriteDebugCtrl(0x0U);
 			Xil_L2CacheSync();
+#endif
 			tempadr += cacheline;
 		}
 		if ((tempend & (cacheline-1U)) != 0U) {
 			tempend &= (~(cacheline - 1U));
 
 			Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
 			/* Disable Write-back and line fills */
 			Xil_L2WriteDebugCtrl(0x3U);
 			Xil_L2CacheFlushLine(tempend);
 			/* Enable Write-back and line fills */
 			Xil_L2WriteDebugCtrl(0x0U);
 			Xil_L2CacheSync();
+#endif
 		}
 
 		while (tempadr < tempend) {
+#ifndef USE_AMP
 			/* Invalidate L2 cache line */
 			*L2CCOffset = tempadr;
 			Xil_L2CacheSync();
+#endif
 #ifdef __GNUC__
 			/* Invalidate L1 Data cache line */
 			__asm__ __volatile__("mcr " \
@@ -397,8 +413,9 @@ void Xil_DCacheFlush(void)
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
 	Xil_L1DCacheFlush();
+#ifndef USE_AMP
 	Xil_L2CacheFlush();
-
+#endif
 	mtcpsr(currmask);
 }
 
@@ -424,7 +441,7 @@ void Xil_DCacheFlushLine(u32 adr)
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
 	Xil_L1DCacheFlushLine(adr);
-
+#ifndef USE_AMP
 	/* Disable Write-back and line fills */
 	Xil_L2WriteDebugCtrl(0x3U);
 
@@ -433,6 +450,7 @@ void Xil_DCacheFlushLine(u32 adr)
 	/* Enable Write-back and line fills */
 	Xil_L2WriteDebugCtrl(0x0U);
 	Xil_L2CacheSync();
+#endif
 	mtcpsr(currmask);
 }
 
@@ -483,9 +501,11 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
 				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
 			  Reg = LocalAddr; }
 #endif
+#ifndef USE_AMP
 			/* Flush L2 cache line */
 			*L2CCOffset = LocalAddr;
 			Xil_L2CacheSync();
+#endif
 			LocalAddr += cacheline;
 		}
 	}
@@ -515,7 +535,9 @@ void Xil_DCacheStoreLine(u32 adr)
 	mtcpsr(currmask | IRQ_FIQ_MASK);
 
 	Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
 	Xil_L2CacheStoreLine(adr);
+#endif
 	mtcpsr(currmask);
 }
 
@@ -533,7 +555,9 @@ void Xil_DCacheStoreLine(u32 adr)
 void Xil_ICacheEnable(void)
 {
 	Xil_L1ICacheEnable();
+#ifndef USE_AMP
 	Xil_L2CacheEnable();
+#endif
 }
 
 /****************************************************************************
@@ -549,7 +573,9 @@ void Xil_ICacheEnable(void)
 ****************************************************************************/
 void Xil_ICacheDisable(void)
 {
+#ifndef USE_AMP
 	Xil_L2CacheDisable();
+#endif
 	Xil_L1ICacheDisable();
 }
 
@@ -570,8 +596,9 @@ void Xil_ICacheInvalidate(void)
 
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
-
+#ifndef USE_AMP
 	Xil_L2CacheInvalidate();
+#endif
 	Xil_L1ICacheInvalidate();
 
 	mtcpsr(currmask);
@@ -596,7 +623,9 @@ void Xil_ICacheInvalidateLine(u32 adr)
 
 	currmask = mfcpsr();
 	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
 	Xil_L2CacheInvalidateLine(adr);
+#endif
 	Xil_L1ICacheInvalidateLine(adr);
 	mtcpsr(currmask);
 }
@@ -640,9 +669,11 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
 		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
 
 		while (LocalAddr < end) {
+#ifndef USE_AMP
 		/* Invalidate L2 cache line */
 		*L2CCOffset = LocalAddr;
 		dsb();
+#endif
 #ifdef __GNUC__
 			/* Invalidate L1 I-cache line */
 			__asm__ __volatile__("mcr " \
@@ -1265,6 +1296,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
 	mtcpsr(currmask);
 }
 
+#ifndef USE_AMP
 /****************************************************************************
 *
 * Enable the L2 cache.
@@ -1609,3 +1641,4 @@ void Xil_L2CacheStoreLine(u32 adr)
 	/* synchronize the processor */
 	dsb();
 }
+#endif